void Permute(EncryptBlk *aBlkPTr, int32_t* aKeyPtr)
{
register char bitPos;
char* ArrayPtr;
register uint32_t keyLo;
register uint32_t keyHi;
register uint32_t loBits;
register uint32_t hiBits;
register uint32_t gTestVal;
register uint32_t gTemp;
register uint32_t arrayByte;
bitPos = 0;
hiBits = 0;
loBits = 0;
keyLo = aBlkPTr->keyLo;
keyHi = aBlkPTr->keyHi;
ArrayPtr = (char*) aKeyPtr;
bitPos = *ArrayPtr ++; /* get source bit */
Loop:
arrayByte = bitPos;
ROLeftLong(hiBits);
BitTest(5, arrayByte);
BEQ(jump20);
BitClear(5,arrayByte);
BitTest(arrayByte,keyLo);
BNE(jump30);
BRA(jump40);
jump20:
BitTest(arrayByte,keyHi);
BEQ(jump40);
jump30:
BitSet(kbit0,hiBits);
jump40:
bitPos = *ArrayPtr++;
if (bitPos >= 0) goto Loop;
EXchange(hiBits,loBits);
if ( bitPos != -1 ) goto jump50;
bitPos = *ArrayPtr++;
goto Loop;
jump50:
aBlkPTr->keyLo = loBits; /* low bits */
aBlkPTr->keyHi = hiBits;
}
/*===================================================================*/
void K6502_Step( WORD wClocks )
{
/*
* Only the specified number of the clocks execute Op.
*
* Parameters
* WORD wClocks (Read)
* The number of the clocks
*/
BYTE byCode;
WORD wA0;
BYTE byD0;
BYTE byD1;
WORD wD0;
// Dispose of it if there is an interrupt requirement
if ( NMI_State != NMI_Wiring )
{
// NMI Interrupt
NMI_State = NMI_Wiring;
CLK( 7 );
PUSHW( PC );
PUSH( F & ~FLAG_B );
RSTF( FLAG_D );
SETF( FLAG_I );
PC = K6502_ReadW( VECTOR_NMI );
}
else
if ( IRQ_State != IRQ_Wiring )
{
// IRQ Interrupt
// Execute IRQ if an I flag isn't being set
if ( !( F & FLAG_I ) )
{
IRQ_State = IRQ_Wiring;
CLK( 7 );
PUSHW( PC );
PUSH( F & ~FLAG_B );
RSTF( FLAG_D );
SETF( FLAG_I );
PC = K6502_ReadW( VECTOR_IRQ );
}
}
// It has a loop until a constant clock passes
while ( g_wPassedClocks < wClocks )
{
// Read an instruction
byCode = K6502_Read( PC++ );
// Execute an instruction.
switch ( byCode )
{
case 0x00: // BRK
++PC; PUSHW( PC ); SETF( FLAG_B ); PUSH( F ); SETF( FLAG_I ); RSTF( FLAG_D ); PC = K6502_ReadW( VECTOR_IRQ ); CLK( 7 );
break;
case 0x01: // ORA (Zpg,X)
ORA( A_IX ); CLK( 6 );
break;
case 0x05: // ORA Zpg
ORA( A_ZP ); CLK( 3 );
break;
case 0x06: // ASL Zpg
ASL( AA_ZP ); CLK( 5 );
break;
case 0x08: // PHP
SETF( FLAG_B ); PUSH( F ); CLK( 3 );
break;
case 0x09: // ORA #Oper
ORA( A_IMM ); CLK( 2 );
break;
case 0x0A: // ASL A
ASLA; CLK( 2 );
break;
case 0x0D: // ORA Abs
ORA( A_ABS ); CLK( 4 );
break;
case 0x0e: // ASL Abs
ASL( AA_ABS ); CLK( 6 );
break;
case 0x10: // BPL Oper
BRA( !( F & FLAG_N ) );
break;
case 0x11: // ORA (Zpg),Y
ORA( A_IY ); CLK( 5 );
break;
case 0x15: // ORA Zpg,X
ORA( A_ZPX ); CLK( 4 );
break;
case 0x16: // ASL Zpg,X
ASL( AA_ZPX ); CLK( 6 );
break;
case 0x18: // CLC
RSTF( FLAG_C ); CLK( 2 );
break;
case 0x19: // ORA Abs,Y
ORA( A_ABSY ); CLK( 4 );
break;
case 0x1D: // ORA Abs,X
ORA( A_ABSX ); CLK( 4 );
break;
case 0x1E: // ASL Abs,X
ASL( AA_ABSX ); CLK( 7 );
break;
case 0x20: // JSR Abs
JSR; CLK( 6 );
break;
case 0x21: // AND (Zpg,X)
AND( A_IX ); CLK( 6 );
break;
case 0x24: // BIT Zpg
BIT( A_ZP ); CLK( 3 );
break;
case 0x25: // AND Zpg
AND( A_ZP ); CLK( 3 );
break;
case 0x26: // ROL Zpg
ROL( AA_ZP ); CLK( 5 );
break;
case 0x28: // PLP
POP( F ); SETF( FLAG_R ); CLK( 4 );
break;
case 0x29: // AND #Oper
AND( A_IMM ); CLK( 2 );
break;
case 0x2A: // ROL A
ROLA; CLK( 2 );
break;
case 0x2C: // BIT Abs
BIT( A_ABS ); CLK( 4 );
break;
case 0x2D: // AND Abs
AND( A_ABS ); CLK( 4 );
break;
case 0x2E: // ROL Abs
ROL( AA_ABS ); CLK( 6 );
break;
case 0x30: // BMI Oper
BRA( F & FLAG_N );
break;
case 0x31: // AND (Zpg),Y
AND( A_IY ); CLK( 5 );
break;
case 0x35: // AND Zpg,X
AND( A_ZPX ); CLK( 4 );
break;
case 0x36: // ROL Zpg,X
ROL( AA_ZPX ); CLK( 6 );
break;
case 0x38: // SEC
SETF( FLAG_C ); CLK( 2 );
break;
case 0x39: // AND Abs,Y
AND( A_ABSY ); CLK( 4 );
break;
case 0x3D: // AND Abs,X
AND( A_ABSX ); CLK( 4 );
break;
case 0x3E: // ROL Abs,X
ROL( AA_ABSX ); CLK( 7 );
break;
case 0x40: // RTI
POP( F ); SETF( FLAG_R ); POPW( PC ); CLK( 6 );
break;
case 0x41: // EOR (Zpg,X)
EOR( A_IX ); CLK( 6 );
break;
case 0x45: // EOR Zpg
EOR( A_ZP ); CLK( 3 );
break;
case 0x46: // LSR Zpg
LSR( AA_ZP ); CLK( 5 );
break;
case 0x48: // PHA
PUSH( A ); CLK( 3 );
break;
case 0x49: // EOR #Oper
EOR( A_IMM ); CLK( 2 );
break;
case 0x4A: // LSR A
LSRA; CLK( 2 );
break;
case 0x4C: // JMP Abs
JMP( AA_ABS ); CLK( 3 );
break;
case 0x4D: // EOR Abs
EOR( A_ABS ); CLK( 4 );
break;
case 0x4E: // LSR Abs
LSR( AA_ABS ); CLK( 6 );
break;
case 0x50: // BVC
BRA( !( F & FLAG_V ) );
break;
case 0x51: // EOR (Zpg),Y
EOR( A_IY ); CLK( 5 );
break;
case 0x55: // EOR Zpg,X
EOR( A_ZPX ); CLK( 4 );
break;
case 0x56: // LSR Zpg,X
LSR( AA_ZPX ); CLK( 6 );
break;
case 0x58: // CLI
byD0 = F;
RSTF( FLAG_I ); CLK( 2 );
if ( ( byD0 & FLAG_I ) && IRQ_State != IRQ_Wiring )
{
IRQ_State = IRQ_Wiring;
CLK( 7 );
PUSHW( PC );
PUSH( F & ~FLAG_B );
RSTF( FLAG_D );
SETF( FLAG_I );
PC = K6502_ReadW( VECTOR_IRQ );
}
break;
case 0x59: // EOR Abs,Y
EOR( A_ABSY ); CLK( 4 );
break;
case 0x5D: // EOR Abs,X
EOR( A_ABSX ); CLK( 4 );
break;
case 0x5E: // LSR Abs,X
LSR( AA_ABSX ); CLK( 7 );
break;
case 0x60: // RTS
POPW( PC ); ++PC; CLK( 6 );
break;
case 0x61: // ADC (Zpg,X)
ADC( A_IX ); CLK( 6 );
break;
case 0x65: // ADC Zpg
ADC( A_ZP ); CLK( 3 );
break;
case 0x66: // ROR Zpg
ROR( AA_ZP ); CLK( 5 );
break;
case 0x68: // PLA
POP( A ); TEST( A ); CLK( 4 );
break;
case 0x69: // ADC #Oper
ADC( A_IMM ); CLK( 2 );
break;
case 0x6A: // ROR A
RORA; CLK( 2 );
break;
case 0x6C: // JMP (Abs)
JMP( K6502_ReadW2( AA_ABS ) ); CLK( 5 );
break;
case 0x6D: // ADC Abs
ADC( A_ABS ); CLK( 4 );
break;
case 0x6E: // ROR Abs
ROR( AA_ABS ); CLK( 6 );
break;
case 0x70: // BVS
BRA( F & FLAG_V );
break;
case 0x71: // ADC (Zpg),Y
ADC( A_IY ); CLK( 5 );
break;
case 0x75: // ADC Zpg,X
ADC( A_ZPX ); CLK( 4 );
break;
case 0x76: // ROR Zpg,X
ROR( AA_ZPX ); CLK( 6 );
break;
case 0x78: // SEI
SETF( FLAG_I ); CLK( 2 );
break;
case 0x79: // ADC Abs,Y
ADC( A_ABSY ); CLK( 4 );
break;
case 0x7D: // ADC Abs,X
ADC( A_ABSX ); CLK( 4 );
break;
case 0x7E: // ROR Abs,X
ROR( AA_ABSX ); CLK( 7 );
break;
case 0x81: // STA (Zpg,X)
STA( AA_IX ); CLK( 6 );
break;
case 0x84: // STY Zpg
STY( AA_ZP ); CLK( 3 );
break;
case 0x85: // STA Zpg
STA( AA_ZP ); CLK( 3 );
break;
case 0x86: // STX Zpg
STX( AA_ZP ); CLK( 3 );
break;
case 0x88: // DEY
--Y; TEST( Y ); CLK( 2 );
break;
case 0x8A: // TXA
A = X; TEST( A ); CLK( 2 );
break;
case 0x8C: // STY Abs
STY( AA_ABS ); CLK( 4 );
break;
case 0x8D: // STA Abs
STA( AA_ABS ); CLK( 4 );
break;
case 0x8E: // STX Abs
STX( AA_ABS ); CLK( 4 );
break;
case 0x90: // BCC
BRA( !( F & FLAG_C ) );
break;
case 0x91: // STA (Zpg),Y
STA( AA_IY ); CLK( 6 );
break;
case 0x94: // STY Zpg,X
STY( AA_ZPX ); CLK( 4 );
break;
case 0x95: // STA Zpg,X
STA( AA_ZPX ); CLK( 4 );
break;
case 0x96: // STX Zpg,Y
STX( AA_ZPY ); CLK( 4 );
break;
case 0x98: // TYA
A = Y; TEST( A ); CLK( 2 );
break;
case 0x99: // STA Abs,Y
STA( AA_ABSY ); CLK( 5 );
break;
case 0x9A: // TXS
SP = X; CLK( 2 );
break;
case 0x9D: // STA Abs,X
STA( AA_ABSX ); CLK( 5 );
break;
case 0xA0: // LDY #Oper
LDY( A_IMM ); CLK( 2 );
break;
case 0xA1: // LDA (Zpg,X)
LDA( A_IX ); CLK( 6 );
break;
case 0xA2: // LDX #Oper
LDX( A_IMM ); CLK( 2 );
break;
case 0xA4: // LDY Zpg
LDY( A_ZP ); CLK( 3 );
break;
case 0xA5: // LDA Zpg
LDA( A_ZP ); CLK( 3 );
break;
case 0xA6: // LDX Zpg
LDX( A_ZP ); CLK( 3 );
break;
case 0xA8: // TAY
Y = A; TEST( A ); CLK( 2 );
break;
case 0xA9: // LDA #Oper
LDA( A_IMM ); CLK( 2 );
break;
case 0xAA: // TAX
X = A; TEST( A ); CLK( 2 );
break;
case 0xAC: // LDY Abs
LDY( A_ABS ); CLK( 4 );
break;
case 0xAD: // LDA Abs
LDA( A_ABS ); CLK( 4 );
break;
case 0xAE: // LDX Abs
LDX( A_ABS ); CLK( 4 );
break;
case 0xB0: // BCS
BRA( F & FLAG_C );
break;
case 0xB1: // LDA (Zpg),Y
LDA( A_IY ); CLK( 5 );
break;
case 0xB4: // LDY Zpg,X
LDY( A_ZPX ); CLK( 4 );
break;
case 0xB5: // LDA Zpg,X
LDA( A_ZPX ); CLK( 4 );
break;
case 0xB6: // LDX Zpg,Y
LDX( A_ZPY ); CLK( 4 );
break;
case 0xB8: // CLV
RSTF( FLAG_V ); CLK( 2 );
break;
case 0xB9: // LDA Abs,Y
LDA( A_ABSY ); CLK( 4 );
break;
case 0xBA: // TSX
X = SP; TEST( X ); CLK( 2 );
break;
case 0xBC: // LDY Abs,X
LDY( A_ABSX ); CLK( 4 );
break;
case 0xBD: // LDA Abs,X
LDA( A_ABSX ); CLK( 4 );
break;
case 0xBE: // LDX Abs,Y
LDX( A_ABSY ); CLK( 4 );
break;
case 0xC0: // CPY #Oper
CPY( A_IMM ); CLK( 2 );
break;
case 0xC1: // CMP (Zpg,X)
CMP( A_IX ); CLK( 6 );
break;
case 0xC4: // CPY Zpg
CPY( A_ZP ); CLK( 3 );
break;
case 0xC5: // CMP Zpg
CMP( A_ZP ); CLK( 3 );
break;
case 0xC6: // DEC Zpg
DEC( AA_ZP ); CLK( 5 );
break;
case 0xC8: // INY
++Y; TEST( Y ); CLK( 2 );
break;
case 0xC9: // CMP #Oper
CMP( A_IMM ); CLK( 2 );
break;
case 0xCA: // DEX
--X; TEST( X ); CLK( 2 );
break;
case 0xCC: // CPY Abs
CPY( A_ABS ); CLK( 4 );
break;
case 0xCD: // CMP Abs
CMP( A_ABS ); CLK( 4 );
break;
case 0xCE: // DEC Abs
DEC( AA_ABS ); CLK( 6 );
break;
case 0xD0: // BNE
BRA( !( F & FLAG_Z ) );
break;
case 0xD1: // CMP (Zpg),Y
CMP( A_IY ); CLK( 5 );
break;
case 0xD5: // CMP Zpg,X
CMP( A_ZPX ); CLK( 4 );
break;
case 0xD6: // DEC Zpg,X
DEC( AA_ZPX ); CLK( 6 );
break;
case 0xD8: // CLD
RSTF( FLAG_D ); CLK( 2 );
break;
case 0xD9: // CMP Abs,Y
CMP( A_ABSY ); CLK( 4 );
break;
case 0xDD: // CMP Abs,X
CMP( A_ABSX ); CLK( 4 );
break;
case 0xDE: // DEC Abs,X
DEC( AA_ABSX ); CLK( 7 );
break;
case 0xE0: // CPX #Oper
CPX( A_IMM ); CLK( 2 );
break;
case 0xE1: // SBC (Zpg,X)
SBC( A_IX ); CLK( 6 );
break;
case 0xE4: // CPX Zpg
CPX( A_ZP ); CLK( 3 );
break;
case 0xE5: // SBC Zpg
SBC( A_ZP ); CLK( 3 );
break;
case 0xE6: // INC Zpg
INC( AA_ZP ); CLK( 5 );
break;
case 0xE8: // INX
++X; TEST( X ); CLK( 2 );
break;
case 0xE9: // SBC #Oper
SBC( A_IMM ); CLK( 2 );
break;
case 0xEA: // NOP
CLK( 2 );
break;
case 0xEC: // CPX Abs
CPX( A_ABS ); CLK( 4 );
break;
case 0xED: // SBC Abs
SBC( A_ABS ); CLK( 4 );
break;
case 0xEE: // INC Abs
INC( AA_ABS ); CLK( 6 );
break;
case 0xF0: // BEQ
BRA( F & FLAG_Z );
break;
case 0xF1: // SBC (Zpg),Y
SBC( A_IY ); CLK( 5 );
break;
case 0xF5: // SBC Zpg,X
SBC( A_ZPX ); CLK( 4 );
break;
case 0xF6: // INC Zpg,X
INC( AA_ZPX ); CLK( 6 );
break;
case 0xF8: // SED
SETF( FLAG_D ); CLK( 2 );
break;
case 0xF9: // SBC Abs,Y
SBC( A_ABSY ); CLK( 4 );
break;
case 0xFD: // SBC Abs,X
SBC( A_ABSX ); CLK( 4 );
break;
case 0xFE: // INC Abs,X
INC( AA_ABSX ); CLK( 7 );
break;
/*-----------------------------------------------------------*/
/* Unlisted Instructions ( thanks to virtualnes ) */
/*-----------------------------------------------------------*/
case 0x1A: // NOP (Unofficial)
case 0x3A: // NOP (Unofficial)
case 0x5A: // NOP (Unofficial)
case 0x7A: // NOP (Unofficial)
case 0xDA: // NOP (Unofficial)
case 0xFA: // NOP (Unofficial)
CLK( 2 );
break;
case 0x80: // DOP (CYCLES 2)
case 0x82: // DOP (CYCLES 2)
case 0x89: // DOP (CYCLES 2)
case 0xC2: // DOP (CYCLES 2)
case 0xE2: // DOP (CYCLES 2)
PC++;
CLK( 2 );
break;
case 0x04: // DOP (CYCLES 3)
case 0x44: // DOP (CYCLES 3)
case 0x64: // DOP (CYCLES 3)
PC++;
CLK( 3 );
break;
case 0x14: // DOP (CYCLES 4)
case 0x34: // DOP (CYCLES 4)
case 0x54: // DOP (CYCLES 4)
case 0x74: // DOP (CYCLES 4)
case 0xD4: // DOP (CYCLES 4)
case 0xF4: // DOP (CYCLES 4)
PC++;
CLK( 4 );
break;
case 0x0C: // TOP
case 0x1C: // TOP
case 0x3C: // TOP
case 0x5C: // TOP
case 0x7C: // TOP
case 0xDC: // TOP
case 0xFC: // TOP
PC+=2;
CLK( 4 );
break;
default: // Unknown Instruction
CLK( 2 );
#if 0
InfoNES_MessageBox( "0x%02x is unknown instruction.\n", byCode ) ;
#endif
break;
} /* end of switch ( byCode ) */
} /* end of while ... */
// Correct the number of the clocks
g_wPassedClocks -= wClocks;
}
int assignExprCodegen(c_tree tree, int *registerNo, int topLevel,
int getAddress, const char *breakLabel, const char *continueLabel)
{
c_tree rhs = TREE_EXPR_OPERAND(tree,1);
c_tree lhs = TREE_EXPR_OPERAND(tree,0);
if (TREE_CODE(lhs) == TREE_DECL && (strcmp(DECL_NAME_STRING(lhs), COUT)
== 0))
{
int rhsValue = c_codegen_recurse(rhs, registerNo, FALSE, FALSE,
breakLabel, continueLabel);
ADDi(R0, rhsValue, 0, "copying into R0", NULL);
COUTASM("Displaying to COUT", "");
return R0;
}
else
{
c_tree type = get_type_for_uid(TYPE(TREE_TYPE(lhs))->uid);
int typeSize = getSize(TREE_TYPE(lhs));
if(TYPE(type)->code!=STRUCT_TYPE || typeSize==1 )
{
int rhsValue = c_codegen_recurse(rhs, registerNo, FALSE, FALSE,
breakLabel, continueLabel);
int lhsAddress = c_codegen_recurse(lhs, registerNo, FALSE, TRUE,
breakLabel, continueLabel);
STRi(rhsValue, lhsAddress, 0, "assignment", NULL);
}
else
{
int rhsAddress = c_codegen_recurse(rhs, registerNo, FALSE, TRUE,
breakLabel, continueLabel);
int lhsAddress = c_codegen_recurse(lhs, registerNo, FALSE, TRUE,
breakLabel, continueLabel);
static int copyCondLabelNo = 0;
static char copyCondLabelPrefix[] = "SCC";
char copyCondLabelArray[LABEL_ARRAY_LENGTH];
static int copyEndLabelNo = 0;
static char copyEndLabelPrefix[] = "SCE";
char copyEndLabelArray[LABEL_ARRAY_LENGTH];
sprintf(copyCondLabelArray, "%s%d", copyCondLabelPrefix,
copyCondLabelNo++);
sprintf(copyEndLabelArray, "%s%d", copyEndLabelPrefix,
copyEndLabelNo++);
int counterRegister = (*registerNo)++;
int subResultRegister = (*registerNo)++;
int tempCopyRegister = (*registerNo)++;
// loop for copying
SET(counterRegister, 0, "struct copy counter initial value", NULL);
SUBi(subResultRegister, counterRegister, typeSize,
"struct copy condition to end copying", copyCondLabelArray);
BRnzp(subResultRegister, copyEndLabelArray,
"struct copy branch to end", NULL, "z");
LDR(tempCopyRegister, rhsAddress, counterRegister, "struct assignment", NULL);
STR(tempCopyRegister, lhsAddress, counterRegister, "struct assignment", NULL);
ADDi(counterRegister, counterRegister, 1, "struct copy increment counter", NULL);
BRA(copyCondLabelArray, "struct copy branch to condition", NULL);
NOP("end of struct copying", copyEndLabelArray);
}
return c_codegen_recurse(lhs, registerNo,
topLevel, getAddress, breakLabel, continueLabel);
}
}
