BRANCH_INST ("bgt", 0x76),
BRANCH_INST ("ble", 0x77),
BRANCH_INST ("bfs", 0x78),
BRANCH_INST ("bfc", 0x79),
BRANCH_INST ("blo", 0x7A),
BRANCH_INST ("bhs", 0x7B),
BRANCH_INST ("blt", 0x7C),
BRANCH_INST ("bge", 0x7D),
BRANCH_INST ("br", 0x7E),
/* Create a 'Branch if Equal to 0' instruction. */
#define BRANCH_NEQ_INST(NAME, OPC) \
/* opc8 dispu5 r */ \
{NAME, 1, OPC, 24, BRANCH_NEQ_INS, {{regr,16}, {d5,20}}}
BRANCH_NEQ_INST ("beq0b", 0xB0),
BRANCH_NEQ_INST ("bne0b", 0xB1),
BRANCH_NEQ_INST ("beq0w", 0xB2),
BRANCH_NEQ_INST ("bne0w", 0xB3),
BRANCH_NEQ_INST ("beq0d", 0xB4),
BRANCH_NEQ_INST ("bne0d", 0xB5),
/* Create instruction with no operands. */
#define NO_OP_INST(NAME, OPC) \
/* opc16 */ \
{NAME, 1, OPC, 16, 0, {{0, 0}}}
NO_OP_INST ("nop", 0x3002),
NO_OP_INST ("retx", 0x3003),
NO_OP_INST ("di", 0x3004),
NO_OP_INST ("ei", 0x3005),
#define BRANCH_INST(NAME, OPC) \
/* opc4 c4 dispe9 */ \
{NAME, 1, OPC, 28, BRANCH_INS | RELAXABLE, {{cc,20}, {dispe9,16}}},\
/* opc4 c4 disps17 */ \
{NAME, 2, ((OPC<<4)+0x8), 24, BRANCH_INS | RELAXABLE, {{cc,20}, {disps17,0}}},\
/* opc4 c4 disps25 */ \
{NAME, 3, (OPC<<4), 16 , BRANCH_INS | RELAXABLE, {{cc,4}, {disps25,16}}}
BRANCH_INST ("b", 0x1),
/* Create a 'Branch if Equal to 0' instruction. */
#define BRANCH_NEQ_INST(NAME, OPC) \
/* opc8 disps5 r */ \
{NAME, 1, OPC, 24, BRANCH_NEQ_INS, {{regr,16}, {disps5,20}}}
BRANCH_NEQ_INST ("beq0b", 0x0C),
BRANCH_NEQ_INST ("bne0b", 0x0D),
BRANCH_NEQ_INST ("beq0w", 0x0E),
BRANCH_NEQ_INST ("bne0w", 0x0F),
/* Create an instruction using a single register operand. */
#define REG1_INST(NAME, OPC) \
/* opc8 c4 r */ \
{NAME, 1, OPC, 20, NO_TYPE_INS, {{regr,16}}}
#define REGP1_INST(NAME, OPC) \
/* opc8 c4 r */ \
{NAME, 1, OPC, 20, NO_TYPE_INS, {{regp,16}}}
/* Same as REG1_INST, with additional FLAGS. */
