uint32_t ITCR; /* Integration Test Control Register */
uint32_t ITOP; /* Integration Test Output Set Register, write only */
const uint32_t Reserved2[54]; /* Reserved for future expansion, should not be modified */
const uint32_t PERIPHID[4]; /* Timer Peripheral ID, read only */
const uint32_t CELLID[4]; /* PrimeCell ID, read only */
} ARM926EJS_TIMER_REGS;
/*
* Pointers to all timer registers' base addresses:
*/
#define CAST_ADDR(ADDR) (ARM926EJS_TIMER_REGS*) (ADDR),
static volatile ARM926EJS_TIMER_REGS* const pReg[BSP_NR_TIMERS]=
{
BSP_TIMER_BASE_ADDRESSES(CAST_ADDR)
};
#undef CAST_ADDR
/**
* Initializes the specified timer's counter controller.
* The following parameters are set:
* - periodic mode (when the counter reaches 0, it is wrapped to the value of the Load Register)
* - 32-bit counter length
* - prescale = 1
*
* This function does not enable interrupt triggering and does not start the counter!
*
* Nothing is done if either 'timerNr' or 'counterNr' is invalid.
*
uint32_t ITCR; /* Integration Test Control Register */
uint32_t ITOP; /* Integration Test Output Set Register, write only */
const Reserved2[54]; /* Reserved for future expansion, should not be modified */
const uint32_t PERIPHID[4]; /* Timer Peripheral ID, read only */
const uint32_t CELLID[4]; /* PrimeCell ID, read only */
} ARM926EJS_TIMER_REGS;
/*
* Pointers to all timer registers' base addresses:
*/
#define GEN_CAST_ADDR(ADDR) (ARM926EJS_TIMER_REGS*) (ADDR),
static volatile ARM926EJS_TIMER_REGS* const pReg[BSP_NR_TIMERS]=
{
BSP_TIMER_BASE_ADDRESSES(GEN_CAST_ADDR)
};
#undef GEN_CAST_ADDR
/**
* Initializes the specified timer's counter controller.
* The following parameters are set:
* - periodic mode (when the counter reaches 0, it is wrapped to the value of the Load Register)
* - 32-bit counter length
* - prescale = 1
*
* This function does not enable interrupt triggering and does not start the counter!
*
* Nothing is done if either 'timerNr' or 'counterNr' is invalid.
*
