static void _btif_set_default_setting(void)
{
struct device_node *node = NULL;
unsigned int irq_info[3] = {0, 0, 0};
unsigned int phy_base;
node = of_find_compatible_node(NULL, NULL, "mediatek,BTIF");
if(node){
mtk_btif.p_irq->irq_id = irq_of_parse_and_map(node,0);
/*fixme, be compitable arch 64bits*/
mtk_btif.base = (unsigned long)of_iomap(node, 0);
BTIF_INFO_FUNC("get btif irq(%d),register base(0x%lx)\n",
mtk_btif.p_irq->irq_id,mtk_btif.base);
}else{
BTIF_ERR_FUNC("get btif device node fail\n");
}
/* get the interrupt line behaviour */
if (of_property_read_u32_array(node, "interrupts",
irq_info, ARRAY_SIZE(irq_info))){
BTIF_ERR_FUNC("get interrupt flag from DTS fail\n");
}else{
mtk_btif.p_irq->irq_flags = irq_info[2];
BTIF_INFO_FUNC("get interrupt flag(0x%x)\n",mtk_btif.p_irq->irq_flags);
}
if (of_property_read_u32_index(node, "reg", 0, &phy_base)){
BTIF_ERR_FUNC("get register phy base from DTS fail\n");
}else{
BTIF_INFO_FUNC("get register phy base(0x%lx)\n",(unsigned long)phy_base);
}
}
int _btif_dma_dump_dbg_reg(void)
{
#if 0
int i = 0;
char *addr1 = NULL;
char *addr2 = NULL;
int array_num = sizeof(g_dma_dbg_regs) / sizeof(g_dma_dbg_regs[0]);
addr1 = ioremap(g_dma_dbg_regs[0].reg_addr, 0x20);
if (addr1) {
for (i = 0; i < 5; i++)
g_dma_dbg_regs[i].reg_val = *(volatile unsigned int*)(addr1 + i*4);
iounmap(addr1);
}
addr2 = ioremap(g_dma_dbg_regs[5].reg_addr, 0x10);
if (addr2) {
g_dma_dbg_regs[5].reg_val = *(volatile unsigned int*)(addr2);
g_dma_dbg_regs[6].reg_val = *(volatile unsigned int*)(addr2+4);
g_dma_dbg_regs[7].reg_val = *(volatile unsigned int*)(addr2+8);
iounmap(addr2);
}
for (i = 0; i < array_num; i++)
BTIF_INFO_FUNC("<reg, val>-<0x%lx, 0x%08x>\n", g_dma_dbg_regs[i].reg_addr, g_dma_dbg_regs[i].reg_val);
#endif
return 0;
}
int hal_dma_pm_ops(P_MTK_DMA_INFO_STR p_dma_info, MTK_BTIF_PM_OPID opid)
{
int i_ret = -1;
BTIF_INFO_FUNC("op id: %d\n", opid);
switch (opid) {
case BTIF_PM_DPIDLE_EN:
i_ret = 0;
break;
case BTIF_PM_DPIDLE_DIS:
i_ret = 0;
break;
case BTIF_PM_SUSPEND:
i_ret = 0;
break;
case BTIF_PM_RESUME:
i_ret = 0;
break;
case BTIF_PM_RESTORE_NOIRQ:{
unsigned int flag = 0;
P_MTK_BTIF_IRQ_STR p_irq = p_dma_info->p_irq;
switch (p_irq->sens_type) {
case IRQ_SENS_EDGE:
if (IRQ_EDGE_FALL == p_irq->edge_type)
flag = IRQF_TRIGGER_FALLING;
else if (IRQ_EDGE_RAISE == p_irq->edge_type)
flag = IRQF_TRIGGER_RISING;
else if (IRQ_EDGE_BOTH == p_irq->edge_type)
flag = IRQF_TRIGGER_RISING |
IRQF_TRIGGER_FALLING;
else
flag = IRQF_TRIGGER_FALLING; /*make this as default type */
break;
case IRQ_SENS_LVL:
if (IRQ_LVL_LOW == p_irq->lvl_type)
flag = IRQF_TRIGGER_LOW;
else if (IRQ_LVL_HIGH == p_irq->lvl_type)
flag = IRQF_TRIGGER_HIGH;
else
flag = IRQF_TRIGGER_LOW; /*make this as default type */
break;
default:
flag = IRQF_TRIGGER_LOW; /*make this as default type */
break;
}
/* irq_set_irq_type(p_irq->irq_id, flag); */
i_ret = 0;
}
i_ret = 0;
break;
default:
i_ret = ERR_INVALID_PAR;
break;
}
return i_ret;
}
int hal_btif_rx_cb_reg(P_MTK_BTIF_INFO_STR p_btif_info, btif_rx_buf_write rx_cb)
{
if (NULL != p_btif_info->rx_cb)
{
BTIF_INFO_FUNC("rx_cb already registered, replace (0x%08x) with (0x%08x)\n", p_btif_info->rx_cb, rx_cb);
}
p_btif_info->rx_cb = rx_cb;
return 0;
}
/*****************************************************************************
* FUNCTION
* hal_dma_get_ava_room
* DESCRIPTION
* get tx available room
* PARAMETERS
* p_dma_info [IN] pointer to BTIF dma channel's information
* RETURNS
* available room size
*****************************************************************************/
int hal_dma_get_ava_room(P_MTK_DMA_INFO_STR p_dma_info)
{
int i_ret = -1;
unsigned long base = p_dma_info->base;
/*read vFIFO's left size*/
i_ret = BTIF_READ32(TX_DMA_VFF_LEFT_SIZE(base));
BTIF_DBG_FUNC("DMA tx ava room (%d).\n", i_ret);
if (0 == i_ret)
BTIF_INFO_FUNC("DMA tx vfifo is full.\n");
return i_ret;
}
/*****************************************************************************
* FUNCTION
* hal_btif_info_get
* DESCRIPTION
* get btif's information included base address , irq related information
* PARAMETERS
* RETURNS
* BTIF's informations
*****************************************************************************/
P_MTK_BTIF_INFO_STR hal_btif_info_get(void)
{
#if NEW_TX_HANDLING_SUPPORT
int i_ret = 0;
/*tx fifo and fifo lock init*/
i_ret = _btif_tx_fifo_init(&mtk_btif);
if (0 == i_ret) {
BTIF_INFO_FUNC("_btif_tx_fifo_init succeed\n");
} else {
BTIF_ERR_FUNC("_btif_tx_fifo_init failed, i_ret:%d\n", i_ret);
}
#endif
spin_lock_init(&g_clk_cg_spinlock);
return &mtk_btif;
}
/*****************************************************************************
* FUNCTION
* hal_btif_dump_reg
* DESCRIPTION
* dump BTIF module's information when needed
* PARAMETERS
* p_base [IN] BTIF module's base address
* flag [IN] register id flag
* RETURNS
* 0 means success, negative means fail
*****************************************************************************/
int hal_btif_dump_reg(P_MTK_BTIF_INFO_STR p_btif, ENUM_BTIF_REG_ID flag)
{
/*Chaozhong: To be implement*/
int i_ret = -1;
int idx = 0;
/*unsigned long irq_flag = 0;*/
unsigned int base = p_btif->base;
unsigned char reg_map[0xE0 / 4] = { 0 };
unsigned int lsr = 0x0;
unsigned int dma_en = 0;
/*spin_lock_irqsave(&(g_clk_cg_spinlock), irq_flag);*/
#if MTK_BTIF_ENABLE_CLK_CTL
if (0 == clock_is_on(MTK_BTIF_CG_BIT)) {
/*spin_unlock_irqrestore(&(g_clk_cg_spinlock), irq_flag);*/
BTIF_ERR_FUNC("%s: clock is off, this should never happen!!!\n",
__FILE__);
return i_ret;
}
#endif
lsr = BTIF_READ32(BTIF_LSR(base));
dma_en = BTIF_READ32(BTIF_DMA_EN(base));
/*here we omit 1st register which is THR/RBR register to avoid
Rx data read by this debug information accidently*/
for (idx = 1; idx < sizeof(reg_map); idx++)
reg_map[idx] = BTIF_READ8(p_btif->base + (4 * idx));
/*spin_unlock_irqrestore(&(g_clk_cg_spinlock), irq_flag);*/
BTIF_INFO_FUNC("BTIF's clock is on\n");
BTIF_INFO_FUNC("base address: 0x%x\n", base);
switch (flag) {
case REG_BTIF_ALL:
#if 0
BTIF_INFO_FUNC("BTIF_IER:0x%x\n", BTIF_READ32(BTIF_IER(base)));
BTIF_INFO_FUNC("BTIF_IIR:0x%x\n", BTIF_READ32(BTIF_IIR(base)));
BTIF_INFO_FUNC("BTIF_FAKELCR:0x%x\n",
BTIF_READ32(BTIF_FAKELCR(base)));
BTIF_INFO_FUNC("BTIF_LSR:0x%x\n", BTIF_READ32(BTIF_LSR(base)));
BTIF_INFO_FUNC("BTIF_SLEEP_EN:0x%x\n",
BTIF_READ32(BTIF_SLEEP_EN(base)));
BTIF_INFO_FUNC("BTIF_DMA_EN:0x%x\n",
BTIF_READ32(BTIF_DMA_EN(base)));
BTIF_INFO_FUNC("BTIF_RTOCNT:0x%x\n",
BTIF_READ32(BTIF_RTOCNT(base)));
BTIF_INFO_FUNC("BTIF_TRI_LVL:0x%x\n",
BTIF_READ32(BTIF_TRI_LVL(base)));
BTIF_INFO_FUNC("BTIF_WAT_TIME:0x%x\n",
BTIF_READ32(BTIF_WAT_TIME(base)));
BTIF_INFO_FUNC("BTIF_HANDSHAKE:0x%x\n",
BTIF_READ32(BTIF_HANDSHAKE(base)));
#endif
btif_dump_array("BTIF register", reg_map, sizeof(reg_map));
break;
default:
break;
}
BTIF_INFO_FUNC("Tx DMA %s\n",
(dma_en & BTIF_DMA_EN_TX) ? "enabled" : "disabled");
BTIF_INFO_FUNC("Rx DMA %s\n",
(dma_en & BTIF_DMA_EN_RX) ? "enabled" : "disabled");
BTIF_INFO_FUNC("Rx data is %s\n",
(lsr & BTIF_LSR_DR_BIT) ? "not empty" : "empty");
BTIF_INFO_FUNC("Tx data is %s\n",
(lsr & BTIF_LSR_TEMT_BIT) ? "empty" : "not empty");
return i_ret;
}
static int hal_tx_dma_dump_reg(P_MTK_DMA_INFO_STR p_dma_info,
ENUM_BTIF_REG_ID flag)
{
int i_ret = -1;
unsigned int base = p_dma_info->base;
unsigned int int_flag = 0;
unsigned int enable = 0;
unsigned int stop = 0;
unsigned int flush = 0;
unsigned int wpt = 0;
unsigned int rpt = 0;
unsigned int int_buf = 0;
unsigned int valid_size = 0;
/*unsigned long irq_flag = 0;*/
/*spin_lock_irqsave(&(g_clk_cg_spinlock), irq_flag);*/
if (0 == clock_is_on(MTK_BTIF_APDMA_CLK_CG)) {
/*spin_unlock_irqrestore(&(g_clk_cg_spinlock), irq_flag);*/
BTIF_ERR_FUNC("%s: clock is off, this should never happen!!!\n",
__FILE__);
return i_ret;
}
int_flag = BTIF_READ32(TX_DMA_INT_FLAG(base));
enable = BTIF_READ32(TX_DMA_EN(base));
stop = BTIF_READ32(TX_DMA_STOP(base));
flush = BTIF_READ32(TX_DMA_FLUSH(base));
wpt = BTIF_READ32(TX_DMA_VFF_WPT(base));
rpt = BTIF_READ32(TX_DMA_VFF_RPT(base));
int_buf = BTIF_READ32(TX_DMA_INT_BUF_SIZE(base));
valid_size = BTIF_READ32(TX_DMA_VFF_VALID_SIZE(base));
/*spin_unlock_irqrestore(&(g_clk_cg_spinlock), irq_flag);*/
BTIF_INFO_FUNC("DMA's clock is on\n");
BTIF_INFO_FUNC("Tx DMA's base address: 0x%x\n", base);
if (REG_TX_DMA_ALL == flag) {
BTIF_INFO_FUNC("TX_EN(:0x%x\n", enable);
BTIF_INFO_FUNC("INT_FLAG:0x%x\n", int_flag);
BTIF_INFO_FUNC("TX_STOP:0x%x\n", stop);
BTIF_INFO_FUNC("TX_FLUSH:0x%x\n", flush);
BTIF_INFO_FUNC("TX_WPT:0x%x\n", wpt);
BTIF_INFO_FUNC("TX_RPT:0x%x\n", rpt);
BTIF_INFO_FUNC("INT_BUF_SIZE:0x%x\n", int_buf);
BTIF_INFO_FUNC("VALID_SIZE:0x%x\n", valid_size);
BTIF_INFO_FUNC("INT_EN:0x%x\n",
BTIF_READ32(TX_DMA_INT_EN(base)));
BTIF_INFO_FUNC("TX_RST:0x%x\n", BTIF_READ32(TX_DMA_RST(base)));
BTIF_INFO_FUNC("VFF_ADDR:0x%x\n",
BTIF_READ32(TX_DMA_VFF_ADDR(base)));
BTIF_INFO_FUNC("VFF_LEN:0x%x\n",
BTIF_READ32(TX_DMA_VFF_LEN(base)));
BTIF_INFO_FUNC("TX_THRE:0x%x\n",
BTIF_READ32(TX_DMA_VFF_THRE(base)));
BTIF_INFO_FUNC("W_INT_BUF_SIZE:0x%x\n",
BTIF_READ32(TX_DMA_W_INT_BUF_SIZE(base)));
BTIF_INFO_FUNC("LEFT_SIZE:0x%x\n",
BTIF_READ32(TX_DMA_VFF_LEFT_SIZE(base)));
BTIF_INFO_FUNC("DBG_STATUS:0x%x\n",
BTIF_READ32(TX_DMA_DEBUG_STATUS(base)));
i_ret = 0;
} else {
BTIF_WARN_FUNC("unknown flag:%d\n", flag);
}
BTIF_INFO_FUNC("tx dma %s\n", (enable & DMA_EN_BIT) &&
(!(stop && DMA_STOP_BIT)) ? "enabled" : "stoped");
BTIF_INFO_FUNC("data in tx dma is %s sent by HW\n",
((wpt == rpt) &&
(int_buf == 0)) ? "completely" : "not completely");
return i_ret;
}
/*****************************************************************************
* FUNCTION
* hal_btif_clk_ctrl
* DESCRIPTION
* control clock output enable/disable of DMA module
* PARAMETERS
* p_dma_info [IN] pointer to BTIF dma channel's information
* RETURNS
* 0 means success, negative means fail
*****************************************************************************/
int hal_btif_dma_clk_ctrl(P_MTK_DMA_INFO_STR p_dma_info, ENUM_CLOCK_CTRL flag)
{
/*In MTK DMA BTIF channel, there's only one global CG on AP_DMA, no sub channel's CG bit*/
/*according to Artis's comment, clock of DMA and BTIF is default off, so we assume it to be off by default*/
int i_ret = 0;
unsigned long irq_flag = 0;
#if MTK_BTIF_ENABLE_CLK_REF_COUNTER
static atomic_t s_clk_ref = ATOMIC_INIT(0);
#else
static ENUM_CLOCK_CTRL status = CLK_OUT_DISABLE;
#endif
#if defined(CONFIG_MTK_LEGACY)
spin_lock_irqsave(&(g_clk_cg_spinlock), irq_flag);
#endif
#if MTK_BTIF_ENABLE_CLK_CTL
#if MTK_BTIF_ENABLE_CLK_REF_COUNTER
if (CLK_OUT_ENABLE == flag) {
if (1 == atomic_inc_return(&s_clk_ref)) {
#if defined(CONFIG_MTK_LEGACY)
i_ret =
enable_clock(MTK_BTIF_APDMA_CLK_CG, DMA_USER_ID);
if (i_ret) {
BTIF_WARN_FUNC
("enable_clock for MTK_BTIF_APDMA_CLK_CG failed, ret:%d",
i_ret);
}
#else
clk_prepare(clk_btif_apdma);
spin_lock_irqsave(&(g_clk_cg_spinlock), irq_flag);
clk_enable(clk_btif_apdma);
spin_unlock_irqrestore(&(g_clk_cg_spinlock), irq_flag);
BTIF_INFO_FUNC("[CCF]enable clk_btif_apdma\n");
#endif /* defined(CONFIG_MTK_LEGACY) */
}
} else if (CLK_OUT_DISABLE == flag) {
if (0 == atomic_dec_return(&s_clk_ref)) {
#if defined(CONFIG_MTK_LEGACY)
i_ret =
disable_clock(MTK_BTIF_APDMA_CLK_CG, DMA_USER_ID);
if (i_ret) {
BTIF_WARN_FUNC
("disable_clock for MTK_BTIF_APDMA_CLK_CG failed, ret:%d",
i_ret);
}
#else
spin_lock_irqsave(&(g_clk_cg_spinlock), irq_flag);
clk_disable(clk_btif_apdma);
spin_unlock_irqrestore(&(g_clk_cg_spinlock), irq_flag);
clk_unprepare(clk_btif_apdma);
BTIF_INFO_FUNC("[CCF] clk_disable_unprepare(clk_btif_apdma) calling\n");
#endif /* defined(CONFIG_MTK_LEGACY) */
}
} else {
i_ret = ERR_INVALID_PAR;
BTIF_ERR_FUNC("invalid clock ctrl flag (%d)\n", flag);
}
#else
if (status == flag) {
i_ret = 0;
BTIF_DBG_FUNC("dma clock already %s\n",
CLK_OUT_ENABLE ==
status ? "enabled" : "disabled");
} else {
if (CLK_OUT_ENABLE == flag) {
#if defined(CONFIG_MTK_LEGACY)
i_ret =
enable_clock(MTK_BTIF_APDMA_CLK_CG, DMA_USER_ID);
status = (0 == i_ret) ? flag : status;
if (i_ret) {
BTIF_WARN_FUNC
("enable_clock for MTK_BTIF_APDMA_CLK_CG failed, ret:%d",
i_ret);
}
#else
clk_prepare(clk_btif_apdma);
spin_lock_irqsave(&(g_clk_cg_spinlock), irq_flag);
clk_enable(clk_btif_apdma);
spin_unlock_irqrestore(&(g_clk_cg_spinlock), irq_flag);
BTIF_INFO_FUNC("[CCF]enable clk_btif_apdma\n");
#endif /* defined(CONFIG_MTK_LEGACY) */
} else if (CLK_OUT_DISABLE == flag) {
#if defined(CONFIG_MTK_LEGACY)
i_ret =
disable_clock(MTK_BTIF_APDMA_CLK_CG, DMA_USER_ID);
status = (0 == i_ret) ? flag : status;
if (i_ret) {
BTIF_WARN_FUNC
("disable_clock for MTK_BTIF_APDMA_CLK_CG failed, ret:%d",
i_ret);
}
#else
spin_lock_irqsave(&(g_clk_cg_spinlock), irq_flag);
clk_disable(clk_btif_apdma);
spin_unlock_irqrestore(&(g_clk_cg_spinlock), irq_flag);
clk_unprepare(clk_btif_apdma);
BTIF_INFO_FUNC("[CCF] clk_disable_unprepare(clk_btif_apdma) calling\n");
#endif /* defined(CONFIG_MTK_LEGACY) */
} else {
i_ret = ERR_INVALID_PAR;
BTIF_ERR_FUNC("invalid clock ctrl flag (%d)\n", flag);
}
}
#endif
#else
#if MTK_BTIF_ENABLE_CLK_REF_COUNTER
#else
status = flag;
#endif
i_ret = 0;
#endif
#if defined(CONFIG_MTK_LEGACY)
spin_unlock_irqrestore(&(g_clk_cg_spinlock), irq_flag);
#endif
#if MTK_BTIF_ENABLE_CLK_REF_COUNTER
if (0 == i_ret) {
BTIF_DBG_FUNC("dma clock %s\n",
CLK_OUT_ENABLE == flag ? "enabled" : "disabled");
} else {
BTIF_ERR_FUNC("%s dma clock failed, ret(%d)\n",
CLK_OUT_ENABLE == flag ? "enable" : "disable",
i_ret);
}
#else
if (0 == i_ret) {
BTIF_DBG_FUNC("dma clock %s\n",
CLK_OUT_ENABLE == flag ? "enabled" : "disabled");
} else {
BTIF_ERR_FUNC("%s dma clock failed, ret(%d)\n",
CLK_OUT_ENABLE == flag ? "enable" : "disable",
i_ret);
}
#endif
#if defined(CONFIG_MTK_LEGACY)
BTIF_DBG_FUNC("DMA's clock is %s\n",
(0 == clock_is_on(MTK_BTIF_APDMA_CLK_CG)) ? "off" : "on");
#endif
return i_ret;
}
static void hal_dma_set_default_setting(ENUM_DMA_DIR dma_dir)
{
struct device_node *node = NULL;
unsigned int irq_info[3] = {0, 0, 0};
unsigned int phy_base;
if (DMA_DIR_RX == dma_dir) {
node = of_find_compatible_node(NULL, NULL, "mediatek,AP_DMA_BTIF_RX");
if (node) {
mtk_btif_rx_dma.p_irq->irq_id = irq_of_parse_and_map(node, 0);
/*fixme, be compitable arch 64bits*/
mtk_btif_rx_dma.base = (unsigned long)of_iomap(node, 0);
BTIF_INFO_FUNC("get rx_dma irq(%d),register base(0x%lx)\n",
mtk_btif_rx_dma.p_irq->irq_id, mtk_btif_rx_dma.base);
} else {
BTIF_ERR_FUNC("get rx_dma device node fail\n");
}
/* get the interrupt line behaviour */
if (of_property_read_u32_array(node, "interrupts",
irq_info, ARRAY_SIZE(irq_info))) {
BTIF_ERR_FUNC("get interrupt flag from DTS fail\n");
} else {
mtk_btif_rx_dma.p_irq->irq_flags = irq_info[2];
BTIF_INFO_FUNC("get interrupt flag(0x%x)\n",
mtk_btif_rx_dma.p_irq->irq_flags);
}
if (of_property_read_u32_index(node, "reg", 0, &phy_base)) {
BTIF_ERR_FUNC("get register phy base from DTS fail,dma_dir(%d)\n",
dma_dir);
} else {
BTIF_INFO_FUNC("get register phy base dma_dir(%d)(0x%x)\n",
dma_dir, (unsigned int)phy_base);
}
} else if (DMA_DIR_TX == dma_dir) {
node = of_find_compatible_node(NULL, NULL, "mediatek,AP_DMA_BTIF_TX");
if (node) {
mtk_btif_tx_dma.p_irq->irq_id = irq_of_parse_and_map(node, 0);
/*fixme, be compitable arch 64bits*/
mtk_btif_tx_dma.base = (unsigned long)of_iomap(node, 0);
BTIF_INFO_FUNC("get tx_dma irq(%d),register base(0x%lx)\n",
mtk_btif_tx_dma.p_irq->irq_id, mtk_btif_tx_dma.base);
} else {
BTIF_ERR_FUNC("get tx_dma device node fail\n");
}
/* get the interrupt line behaviour */
if (of_property_read_u32_array(node, "interrupts",
irq_info, ARRAY_SIZE(irq_info))) {
BTIF_ERR_FUNC("get interrupt flag from DTS fail\n");
} else {
mtk_btif_tx_dma.p_irq->irq_flags = irq_info[2];
BTIF_INFO_FUNC("get interrupt flag(0x%x)\n",
mtk_btif_tx_dma.p_irq->irq_flags);
}
if (of_property_read_u32_index(node, "reg", 0, &phy_base)) {
BTIF_ERR_FUNC("get register phy base from DTS fail,dma_dir(%d)\n",
dma_dir);
} else {
BTIF_INFO_FUNC("get register phy base dma_dir(%d)(0x%x)\n",
dma_dir, (unsigned int)phy_base);
}
}
}
