/* Ack dmach on CSR and IRQSTATUS_L0 */
static u32 omap24xxcam_dmahw_ack_ch(void __iomem *base, int dmach)
{
u32 csr;
csr = omap24xxcam_reg_in(base, CAMDMA_CSR(dmach));
/* ack interrupt in CSR */
omap24xxcam_reg_out(base, CAMDMA_CSR(dmach), csr);
/* ack interrupt in IRQSTATUS */
omap24xxcam_reg_out(base, CAMDMA_IRQSTATUS_L0, (1 << dmach));
return csr;
}
static u32 omap24xxcam_dmahw_ack_ch(unsigned long base, int dmach)
{
u32 csr;
csr = omap24xxcam_reg_in(base, CAMDMA_CSR(dmach));
omap24xxcam_reg_out(base, CAMDMA_CSR(dmach), csr);
omap24xxcam_reg_out(base, CAMDMA_IRQSTATUS_L0, (1 << dmach));
return csr;
}
/* Ack all interrupt on CSR and IRQSTATUS_L0 */
static void omap24xxcam_dmahw_ack_all(void __iomem *base)
{
u32 csr;
int i;
for (i = 0; i < NUM_CAMDMA_CHANNELS; ++i) {
csr = omap24xxcam_reg_in(base, CAMDMA_CSR(i));
/* ack interrupt in CSR */
omap24xxcam_reg_out(base, CAMDMA_CSR(i), csr);
}
omap24xxcam_reg_out(base, CAMDMA_IRQSTATUS_L0, 0xf);
}
static void omap24xxcam_dmahw_ack_all(unsigned long base)
{
u32 csr;
int i;
for (i = 0; i < NUM_CAMDMA_CHANNELS; ++i) {
csr = omap24xxcam_reg_in(base, CAMDMA_CSR(i));
omap24xxcam_reg_out(base, CAMDMA_CSR(i), csr);
}
omap24xxcam_reg_out(base, CAMDMA_IRQSTATUS_L0, 0xf);
}
static void omap24xxcam_dmahw_transfer_setup(void __iomem *base, int dmach,
dma_addr_t start, u32 len)
{
omap24xxcam_reg_out(base, CAMDMA_CCR(dmach),
CAMDMA_CCR_SEL_SRC_DST_SYNC
| CAMDMA_CCR_BS
| CAMDMA_CCR_DST_AMODE_POST_INC
| CAMDMA_CCR_SRC_AMODE_POST_INC
| CAMDMA_CCR_FS
| CAMDMA_CCR_WR_ACTIVE
| CAMDMA_CCR_RD_ACTIVE
| CAMDMA_CCR_SYNCHRO_CAMERA);
omap24xxcam_reg_out(base, CAMDMA_CLNK_CTRL(dmach), 0);
omap24xxcam_reg_out(base, CAMDMA_CEN(dmach), len);
omap24xxcam_reg_out(base, CAMDMA_CFN(dmach), 1);
omap24xxcam_reg_out(base, CAMDMA_CSDP(dmach),
CAMDMA_CSDP_WRITE_MODE_POSTED
| CAMDMA_CSDP_DST_BURST_EN_32
| CAMDMA_CSDP_DST_PACKED
| CAMDMA_CSDP_SRC_BURST_EN_32
| CAMDMA_CSDP_SRC_PACKED
| CAMDMA_CSDP_DATA_TYPE_8BITS);
omap24xxcam_reg_out(base, CAMDMA_CSSA(dmach), 0);
omap24xxcam_reg_out(base, CAMDMA_CDSA(dmach), start);
omap24xxcam_reg_out(base, CAMDMA_CSEI(dmach), 0);
omap24xxcam_reg_out(base, CAMDMA_CSFI(dmach), DMA_THRESHOLD);
omap24xxcam_reg_out(base, CAMDMA_CDEI(dmach), 0);
omap24xxcam_reg_out(base, CAMDMA_CDFI(dmach), 0);
omap24xxcam_reg_out(base, CAMDMA_CSR(dmach),
CAMDMA_CSR_MISALIGNED_ERR
| CAMDMA_CSR_SECURE_ERR
| CAMDMA_CSR_TRANS_ERR
| CAMDMA_CSR_BLOCK
| CAMDMA_CSR_DROP);
omap24xxcam_reg_out(base, CAMDMA_CICR(dmach),
CAMDMA_CICR_MISALIGNED_ERR_IE
| CAMDMA_CICR_SECURE_ERR_IE
| CAMDMA_CICR_TRANS_ERR_IE
| CAMDMA_CICR_BLOCK_IE
| CAMDMA_CICR_DROP_IE);
}
