static int lio_get_intr_coalesce(struct net_device *netdev, struct ethtool_coalesce *intr_coal) { struct lio *lio = GET_LIO(netdev); struct octeon_device *oct = lio->oct_dev; struct octeon_instr_queue *iq; struct oct_intrmod_cfg *intrmod_cfg; intrmod_cfg = &oct->intrmod; switch (oct->chip_id) { case OCTEON_CN68XX: case OCTEON_CN66XX: { struct octeon_cn6xxx *cn6xxx = (struct octeon_cn6xxx *)oct->chip; if (!intrmod_cfg->rx_enable) { intr_coal->rx_coalesce_usecs = CFG_GET_OQ_INTR_TIME(cn6xxx->conf); intr_coal->rx_max_coalesced_frames = CFG_GET_OQ_INTR_PKT(cn6xxx->conf); } iq = oct->instr_queue[lio->linfo.txpciq[0].s.q_no]; intr_coal->tx_max_coalesced_frames = iq->fill_threshold; break; } default: netif_info(lio, drv, lio->netdev, "Unknown Chip !!\n"); return -EINVAL; } if (intrmod_cfg->rx_enable) { intr_coal->use_adaptive_rx_coalesce = intrmod_cfg->rx_enable; intr_coal->rate_sample_interval = intrmod_cfg->check_intrvl; intr_coal->pkt_rate_high = intrmod_cfg->maxpkt_ratethr; intr_coal->pkt_rate_low = intrmod_cfg->minpkt_ratethr; intr_coal->rx_max_coalesced_frames_high = intrmod_cfg->rx_maxcnt_trigger; intr_coal->rx_coalesce_usecs_high = intrmod_cfg->rx_maxtmr_trigger; intr_coal->rx_coalesce_usecs_low = intrmod_cfg->rx_mintmr_trigger; intr_coal->rx_max_coalesced_frames_low = intrmod_cfg->rx_mincnt_trigger; } return 0; }
static void cn23xx_enable_vf_interrupt(struct octeon_device *oct, u8 intr_flag) { struct octeon_cn23xx_vf *cn23xx = (struct octeon_cn23xx_vf *)oct->chip; u32 q_no, time_threshold; if (intr_flag & OCTEON_OUTPUT_INTR) { for (q_no = 0; q_no < oct->num_oqs; q_no++) { /* Set up interrupt packet and time thresholds * for all the OQs */ time_threshold = cn23xx_vf_get_oq_ticks( oct, (u32)CFG_GET_OQ_INTR_TIME(cn23xx->conf)); octeon_write_csr64( oct, CN23XX_VF_SLI_OQ_PKT_INT_LEVELS(q_no), (CFG_GET_OQ_INTR_PKT(cn23xx->conf) | ((u64)time_threshold << 32))); } } if (intr_flag & OCTEON_INPUT_INTR) { for (q_no = 0; q_no < oct->num_oqs; q_no++) { /* Set CINT_ENB to enable IQ interrupt */ octeon_write_csr64( oct, CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no), ((octeon_read_csr64( oct, CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no)) & ~CN23XX_PKT_IN_DONE_CNT_MASK) | CN23XX_INTR_CINT_ENB)); } } /* Set queue-0 MBOX_ENB to enable VF mailbox interrupt */ if (intr_flag & OCTEON_MBOX_INTR) { octeon_write_csr64( oct, CN23XX_VF_SLI_PKT_MBOX_INT(0), (octeon_read_csr64(oct, CN23XX_VF_SLI_PKT_MBOX_INT(0)) | CN23XX_INTR_MBOX_ENB)); } }