void setup_systemclock()
{
/* enable the crystal oscillator */
CGU_SetXTALOSC(XTAL_FREQ);
CGU_EnableEntity(CGU_CLKSRC_XTAL_OSC, ENABLE);
/* connect the cpu to the xtal */
CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_BASE_M4);
/* connect the PLL to the xtal */
CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL1);
/* configure the PLL to 120 MHz */
CGU_SetPLL1(10);
while((LPC_CGU->PLL1_STAT&1) == 0x0);
/* enable the PLL */
CGU_EnableEntity(CGU_CLKSRC_PLL1, ENABLE);
/* connect to the CPU core */
CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_M4);
SystemCoreClock = 120000000;
/* wait one msec */
emc_WaitUS(1000);
/* Change the clock to 204 MHz */
CGU_SetPLL1(17);
while((LPC_CGU->PLL1_STAT&1) == 0x0);
SystemCoreClock = 204000000;
CGU_ClockSourceFrequency[CGU_CLKSRC_PLL1] = SystemCoreClock;
}
/*********************************************************************//**
* @brief Initialize default clock for LPC1800 Eval board
* @param[in] None
* @return Initialize status, could be:
* - CGU_ERROR_SUCCESS: successful
* - Other: error
**********************************************************************/
uint32_t CGU_Init(void){
CGU_SetXTALOSC(12000000);
CGU_EnableEntity(CGU_CLKSRC_XTAL_OSC, ENABLE);
CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL1);
// Disable PLL1 CPU hang???
//CGU_EnableEntity(CGU_CLKSRC_PLL1, DISABLE);
CGU_SetPLL1(6);
CGU_EnableEntity(CGU_CLKSRC_PLL1, ENABLE);
CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_M3);
CGU_UpdateClock();
return 0;
}
/*********************************************************************//**
* @brief Initialize default clock for LPC4300 Eval board
* @param[in] None
* @return Initialize status, could be:
* - CGU_ERROR_SUCCESS: successful
* - Other: error
**********************************************************************/
uint32_t CGU_Init(uint32_t wantedFreq)
{
uint32_t msel = 0;
uint32_t nsel = 0;
uint32_t tmp;
// Setup PLL1 to 204MHz
// 0. Select IRC as BASE_M4_CLK source
CGU_EntityConnect(CGU_CLKSRC_IRC, CGU_BASE_M4);
SystemCoreClock = 96000000;
// 1. Enable the crystal oscillator
CGU_SetXTALOSC(12000000);
CGU_EnableEntity(CGU_CLKSRC_XTAL_OSC, ENABLE);
// 2. Wait 250us
cgu_WaitUS(250);
// 3. Reconfigure PLL1 as follows:
// - Select the M and N divider values to produce the final desired
// PLL1 output frequency (204MHz => M=17,N=1 => msel=16,nsel=0)
// - Select the crystal oscillator as clock source for PLL1
cgu_findMN(wantedFreq, &msel, &nsel);
tmp = LPC_CGU->PLL1_CTRL & ~((0xFF<<16) | (0x03<<12));
LPC_CGU->PLL1_CTRL = tmp | (msel<<16) | (nsel<<12);
CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL1);
// 4. Wait for the PLL1 to lock
while((LPC_CGU->PLL1_STAT&1) == 0x0);
// 5. Set PLL1 P-divider to divide by 2 (DIRECT=0 and PSEL=0)
LPC_CGU->PLL1_CTRL &= ~( (0x03<<8) | CGU_PLL1_DIRECT_MASK );
// 6. Select PLL1 as BASE_M4_CLK source. The BASE_M4_CLK now operates at
// the mid frequency range
CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_M4);
SystemCoreClock = (12000000 * (msel+1))/((nsel+1) * 2);
// 7. Wait 20us
cgu_WaitUS(20);
// 8. Set PLL P-divider to direct output mode (DIRECT=1)
LPC_CGU->PLL1_CTRL |= CGU_PLL1_DIRECT_MASK;
// The BASE_M4_CLK now operates in the high frequency range
CGU_UpdateClock();
SystemCoreClock = (12000000 * (msel+1))/(nsel+1);
return 0;
}
_ramfunc uint32_t CGU_Init(void)
{
__disable_irq();
MemoryPinInit(); // Make sure EMC is in high-speed pin mode
/* Set the XTAL oscillator frequency to 12MHz*/
CGU_SetXTALOSC(12000000);
CGU_EnableEntity(CGU_CLKSRC_XTAL_OSC, ENABLE);
CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_BASE_SPIFI);
CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_BASE_M3);
/* Set PL160M 12*1 = 12 MHz */
CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL1);
CGU_SetPLL1(1);
CGU_EnableEntity(CGU_CLKSRC_PLL1, ENABLE);
/* Run SPIFI from PL160M, /2 */
CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_CLKSRC_IDIVA);
CGU_EnableEntity(CGU_CLKSRC_IDIVA, ENABLE);
CGU_SetDIV(CGU_CLKSRC_IDIVA, 2); // This gets adjusted in spi_flash.c to slow the clock when writing
CGU_EntityConnect(CGU_CLKSRC_IDIVA, CGU_BASE_SPIFI);
CGU_UpdateClock();
LPC_CCU1->CLK_M3_EMCDIV_CFG |= (1<<0) | (1<<5); // Turn on clock / 2
LPC_CREG->CREG6 |= (1<<16); // EMC divided by 2
LPC_CCU1->CLK_M3_EMC_CFG |= (1<<0); // Turn on clock
/* Set PL160M @ 12*9=108 MHz */
CGU_SetPLL1(9);
/* Run base M3 clock from PL160M, no division */
CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_M3);
emc_WaitMS(30);
/* Change the clock to 180 MHz */
/* Set PL160M @ 12*15=180 MHz */
CGU_SetPLL1(15);
emc_WaitMS(30);
CGU_UpdateClock();
emc_WaitMS(10);
__enable_irq();
return 0;
}
/*********************************************************************//**
* @brief Initialize default clock for LPC4300 Eval board
* @param[in] None
* @return Initialize status, could be:
* - CGU_ERROR_SUCCESS: successful
* - Other: error
**********************************************************************/
uint32_t CGU_Init(void){
CGU_SetXTALOSC(12000000);
CGU_EnableEntity(CGU_CLKSRC_XTAL_OSC, ENABLE);
CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_BASE_M4);
CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL1);
CGU_SetPLL1(6);
CGU_EnableEntity(CGU_CLKSRC_PLL1, ENABLE);
CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_M4);
CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_BASE_UART3);
CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_BASE_UART0);
CGU_UpdateClock();
return 0;
}
void clockInit(void)
{
//uint32_t EMCClk;
__disable_irq();
/* Set the XTAL oscillator frequency to 12MHz*/
CGU_SetXTALOSC(__CRYSTAL);
CGU_EnableEntity(CGU_CLKSRC_XTAL_OSC, ENABLE);
CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_BASE_M3);
/* Set PL160M 12*1 = 12 MHz */
CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL1);
// CGU_EntityConnect(CGU_CLKSRC_IRC, CGU_CLKSRC_PLL1);
CGU_SetPLL1(1);
CGU_EnableEntity(CGU_CLKSRC_PLL1, ENABLE);
// setup CLKOUT
CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_CLKSRC_IDIVB);
CGU_EnableEntity(CGU_CLKSRC_IDIVB, ENABLE);
CGU_SetDIV(CGU_CLKSRC_IDIVB, 12); // 12 -> 6 pclks per cpu clk, 10 -> 5 pclks
// set input for CLKOUT to IDIVB
LPC_CGU->BASE_OUT_CLK &= ~0x0f000000;
LPC_CGU->BASE_OUT_CLK |= 0x0d000000;
/* Run SPIFI from PL160M, /2 */
CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_CLKSRC_IDIVA);
CGU_EnableEntity(CGU_CLKSRC_IDIVA, ENABLE);
CGU_SetDIV(CGU_CLKSRC_IDIVA, 2);
CGU_EntityConnect(CGU_CLKSRC_IDIVA, CGU_BASE_SPIFI);
CGU_UpdateClock();
LPC_CCU1->CLK_M4_EMCDIV_CFG |= (1<<0) | (1<<5); // Turn on clock / 2
LPC_CREG->CREG6 |= (1<<16); // EMC divided by 2
LPC_CCU1->CLK_M4_EMC_CFG |= (1<<0); // Turn on clock
/* Set PL160M @ 12*9=108 MHz */
CGU_SetPLL1(9);
/* Run base M3 clock from PL160M, no division */
CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_M3);
waitMS(10);
/* Change the clock to 204 MHz */
/* Set PL160M @ 12*15=180 MHz */
CGU_SetPLL1(17);
waitMS(10);
CGU_UpdateClock();
//EMCFlashInit();
//vEMC_InitSRDRAM(SDRAM_BASE_ADDR, SDRAM_WIDTH, SDRAM_SIZE_MBITS, SDRAM_DATA_BUS_BITS, SDRAM_COL_ADDR_BITS);
LPC_SCU->SFSP3_3 = 0xF3; /* high drive for SCLK */
/* IO pins */
LPC_SCU->SFSP3_4=LPC_SCU->SFSP3_5=LPC_SCU->SFSP3_6=LPC_SCU->SFSP3_7 = 0xD3;
LPC_SCU->SFSP3_8 = 0x13; /* CS doesn't need feedback */
#if 0
EMCClk = CGU_GetPCLKFrequency(CGU_PERIPHERAL_M3CORE)/2;
if (spifi_init(&sobj, 9, S_RCVCLK | S_FULLCLK, EMCClk)) {
if (spifi_init(&sobj, 9, S_RCVCLK | S_FULLCLK, EMCClk)) {
while(1);
}
}
#endif
__enable_irq();
// SPIFI_Init();
}