//******************************************************************************
//
//
// Function Name: chal_dma_force_shutdown_chan
//
// Description: Stop DMA transfer on the specified channel and lose all
// data in the FIFO
//
//******************************************************************************
void chal_dma_force_shutdown_chan(CHAL_HANDLE handle, cUInt32 channel)
{
//
// stop the DMA channel with data loss
// You can disable a DMA channel in the following ways:
// 1. Write directly to the Channel Enable bit.
// You lose any outstanding data in the FIFOs if you use this method.
// 2. Use the Active and Halt bits in conjunction with the Channel Enable bit.
// 3. Wait until the transfer completes. The channel is then automatically disabled.
//
//
cUInt32 temp;
ChalDmaDev_t *pDmaDev = (ChalDmaDev_t *)handle;
temp = CHAL_REG_READ32(pDmaDev->baseAddr+DMAC_CH0CONFIG_OFFSET
+ CHAN_REG_INCREMENT * channel);
//chal_dprintf(CDBG_ERRO, "chal_dma_force_shutdown_chan() temp: 0x%x\n", temp);
temp &= ~DMAC_CH0CONFIG_E_MASK;
CHAL_REG_WRITE32(pDmaDev->baseAddr + DMAC_CH0CONFIG_OFFSET
+ CHAN_REG_INCREMENT * channel, temp);
CHAL_REG_WRITE32(pDmaDev->baseAddr + DMAC_INTTCCLEAR_OFFSET, 0x1<<channel);
CHAL_REG_WRITE32(pDmaDev->baseAddr + DMAC_INTERRCLR_OFFSET, 0x1<<channel);
chal_dma_mark_channel_inactive(handle, channel);
}
//******************************************************************************
//
// Function Name: chal_dma_clear_int_status
//
// Description: Clear the DMA controller's interrupt status
//
//******************************************************************************
void chal_dma_clear_int_status(CHAL_HANDLE handle, cUInt32 mask)
{
ChalDmaDev_t *pDmaDev = (ChalDmaDev_t *)handle;
CHAL_REG_WRITE32(pDmaDev->baseAddr + DMAC_INTTCCLEAR_OFFSET, mask);
CHAL_REG_WRITE32(pDmaDev->baseAddr + DMAC_INTERRCLR_OFFSET, mask);
}
//******************************************************************************
//
// Function Name: chal_dma_get_int_status
//
// Description: Returns the DMA controller's interrupt status
//
//******************************************************************************
void chal_dma_get_int_status(CHAL_HANDLE handle, ChalDmaIntStatus_t *intStatus)
{
UInt32 rc;
ChalDmaDev_t *pDmaDev = (ChalDmaDev_t *)handle;
rc = CHAL_REG_READ32(pDmaDev->baseAddr + DMAC_INTTCSTAT_OFFSET);
intStatus->tcInt |= (rc & 0xfff);
CHAL_REG_WRITE32(pDmaDev->baseAddr + DMAC_INTTCCLEAR_OFFSET, rc);
rc = CHAL_REG_READ32(pDmaDev->baseAddr + DMAC_INTERRSTAT_OFFSET);
intStatus->errInt |= (rc & 0xfff);
CHAL_REG_WRITE32(pDmaDev->baseAddr + DMAC_INTERRCLR_OFFSET, rc);
}
/*
* ******************************************************************************
*
* Function Name: chal_ipc_int_clr
*
* Description: Clear ARM interrupt
*
* ******************************************************************************
*/
BCM_ERR_CODE chal_ipc_int_clr (
CHAL_IPC_HANDLE handle,
IPC_INTERRUPT_SOURCE irqNum
)
{
CHAL_IPC_DEV_T *device;
BCM_DBG_ENTER();
device = (CHAL_IPC_DEV_T*)handle;
if ( irqNum >= IPC_INTERRUPT_SOURCE_MAX )
{
BCM_DBG_EXIT();
return( BCM_ERROR );
}
/* Note: since IPCOPEN_IPCACLR_OFFSET is a write-only register it is not
* valid to read the register then OR the appropriate bit and then write the
* new value. Simply write the appropriate bit to clear the interrupt */
CHAL_REG_WRITE32(device->ipc_open_reg_base + IPCOPEN_IPCACLR_OFFSET, 1 << irqNum );
BCM_DBG_EXIT();
return( BCM_SUCCESS );
}
/*
* ******************************************************************************
*
* Function Name: chal_ipc_write_mailbox
*
* Description:
*
* ******************************************************************************
*/
BCM_ERR_CODE chal_ipc_write_mailbox (
CHAL_IPC_HANDLE handle,
IPC_MAILBOX_ID mailboxId,
uint32_t value
)
{
CHAL_IPC_DEV_T *device;
BCM_DBG_ENTER();
/* Check boundry conditions
* IPC_MAILBOX_ID is an unsigned value and does not need to check less than zero */
if ( mailboxId >= IPC_MAILBOX_ID_MAX )
{
BCM_DBG_EXIT();
return( BCM_ERROR );
}
device = (CHAL_IPC_DEV_T*)handle;
CHAL_REG_WRITE32( device->ipc_secure_reg_base + IPCSEC_IPCMAIL0_OFFSET + mailboxId*sizeof(uint32_t), value );
BCM_DBG_EXIT();
return( BCM_SUCCESS );
}
//******************************************************************************
//
// Function Name: chal_dma_soft_sig_last_request
//
// Description: Set a device to generate software single DMA request
//
//******************************************************************************
void chal_dma_soft_sig_last_request(CHAL_HANDLE handle, cUInt32 device)
{
cUInt32 temp;
ChalDmaDev_t *pDmaDev = (ChalDmaDev_t *)handle;
temp = CHAL_REG_READ32(pDmaDev->baseAddr + DMAC_SOFTLSREQ_OFFSET);
temp |= (0x1 << device);
CHAL_REG_WRITE32(pDmaDev->baseAddr + DMAC_SOFTLSREQ_OFFSET, temp);
}
void chal_audio_enable_aci_auxmic( CHAL_HANDLE handle, int enable )
{
cUInt32 regVal;
ChalAudioCtrlBlk_t *pCHALCb = (ChalAudioCtrlBlk_t*)handle;
if( enable )
{
/* Set ACI */
regVal = CHAL_REG_READ32((pCHALCb->aci_base+ACI_ADC_CTRL_OFFSET));
regVal |= ACI_ADC_CTRL_AUDIORX_VREF_PWRUP_MASK;
regVal |= ACI_ADC_CTRL_AUDIORX_BIAS_PWRUP_MASK;
CHAL_REG_WRITE32((pCHALCb->aci_base+ACI_ADC_CTRL_OFFSET), regVal);
/* enable AUXMIC */
regVal = CHAL_REG_READ32((pCHALCb->auxmic_base+AUXMIC_AUXEN_OFFSET));
regVal |= AUXMIC_AUXEN_MICAUX_EN_MASK;
CHAL_REG_WRITE32((pCHALCb->auxmic_base+AUXMIC_AUXEN_OFFSET), regVal);
/* Set probe cycle to continuous */
regVal = CHAL_REG_READ32((pCHALCb->auxmic_base+AUXMIC_CMC_OFFSET));
regVal |= AUXMIC_CMC_CONT_MSR_CTRL_MASK;
CHAL_REG_WRITE32((pCHALCb->auxmic_base+AUXMIC_CMC_OFFSET), regVal);
/* disable AUXMIC force power down CHAL_REG_WRITE32(0x3500E028, */
regVal = CHAL_REG_READ32((pCHALCb->auxmic_base+AUXMIC_F_PWRDWN_OFFSET));
regVal &= ~AUXMIC_F_PWRDWN_FORCE_PWR_DWN_MASK;
CHAL_REG_WRITE32((pCHALCb->auxmic_base+AUXMIC_F_PWRDWN_OFFSET), regVal);
}
else
{
/* Enable AUXMIC force power down */
regVal = CHAL_REG_READ32((pCHALCb->auxmic_base+AUXMIC_F_PWRDWN_OFFSET));
regVal |= AUXMIC_F_PWRDWN_FORCE_PWR_DWN_MASK;
CHAL_REG_WRITE32((pCHALCb->auxmic_base+AUXMIC_F_PWRDWN_OFFSET), regVal);
/* Set probe cycle to discontinuous */
regVal = CHAL_REG_READ32((pCHALCb->auxmic_base+AUXMIC_CMC_OFFSET));
regVal &= ~AUXMIC_CMC_CONT_MSR_CTRL_MASK;
CHAL_REG_WRITE32((pCHALCb->auxmic_base+AUXMIC_CMC_OFFSET), regVal);
/* Disable AUXMIC */
regVal = CHAL_REG_READ32((pCHALCb->auxmic_base+AUXMIC_AUXEN_OFFSET));
regVal &= ~AUXMIC_AUXEN_MICAUX_EN_MASK;
CHAL_REG_WRITE32((pCHALCb->auxmic_base+AUXMIC_AUXEN_OFFSET), regVal);
/* Analog MIC */
regVal = CHAL_REG_READ32((pCHALCb->aci_base+ACI_ADC_CTRL_OFFSET));
regVal &= ~ACI_ADC_CTRL_AUDIORX_VREF_PWRUP_MASK;
regVal &= ~ACI_ADC_CTRL_AUDIORX_BIAS_PWRUP_MASK;
CHAL_REG_WRITE32((pCHALCb->aci_base+ACI_ADC_CTRL_OFFSET), regVal);
}
}
//******************************************************************************
//
//
// Function Name: chal_dma_reset_channel
//
// Description: Reset a single channel
//
//******************************************************************************
cUInt32 chal_dma_reset_channel(CHAL_HANDLE handle, cUInt16 channel)
{
ChalDmaDev_t *pDmaDev = (ChalDmaDev_t *)handle;
if (channel >= TOTAL_DMA_CHANNELS)
return 0;
//chal_dprintf(CDBG_ERRO, "chal_dma_reset_channel() channel: 0x%x\n", channel);
//
// clear any pending DMA interrupts, wirte zeros to other
// bits does not clear interrupt for these bits
//
CHAL_REG_WRITE32(pDmaDev->baseAddr + DMAC_INTTCCLEAR_OFFSET, 0x1 << channel);
CHAL_REG_WRITE32(pDmaDev->baseAddr + DMAC_INTERRCLR_OFFSET, 0x1 << channel);
CHAL_REG_WRITE32(pDmaDev->baseAddr + DMAC_CH0CONFIG_OFFSET
+ CHAN_REG_INCREMENT * channel, 0);
CHAL_REG_WRITE32(pDmaDev->baseAddr + DMAC_CH0SRCADDR_OFFSET
+ CHAN_REG_INCREMENT * channel, 0);
CHAL_REG_WRITE32(pDmaDev->baseAddr + DMAC_CH0DESTADDR_OFFSET
+ CHAN_REG_INCREMENT * channel, 0);
CHAL_REG_WRITE32(pDmaDev->baseAddr + DMAC_CH0LLI_OFFSET
+ CHAN_REG_INCREMENT * channel, 0);
return 1;
}
void chal_audio_set_aci_auxmic_datab(CHAL_HANDLE handle,
_Bool micOutEnable)
{
cUInt32 regVal;
ChalAudioCtrlBlk_t *pCHALCb = (ChalAudioCtrlBlk_t *)handle;
regVal = CHAL_REG_READ32((pCHALCb->aci_base+ACI_ACI_CTRL_OFFSET));
if (micOutEnable)
regVal |= ACI_ACI_CTRL_SW_MIC_DATAB_MASK;
else
regVal &= ~ACI_ACI_CTRL_SW_MIC_DATAB_MASK;
CHAL_REG_WRITE32((pCHALCb->aci_base+ACI_ACI_CTRL_OFFSET),
regVal);
}
//******************************************************************************
//
// Function Name: chal_dma_shutdown_chan
//
// Description: Terminate a DMA transfer gracefully without data lose
//
//******************************************************************************
void chal_dma_shutdown_chan(CHAL_HANDLE handle, cUInt32 channel)
{
cUInt32 temp;
ChalDmaDev_t *pDmaDev = (ChalDmaDev_t *)handle;
//
// To disable a DMA channel without losing data in the FIFO:
// 1. Set the Halt bit in the relevant channel Configuration Register.
// This causes any subsequent DMA requests to be ignored.
// 2. Poll the Active bit in the relevant channel Configuration Register until
// it reaches 0. This bit indicates whether there is any data in the
// channel that has to be transferred.
// 3. Clear the Channel Enable bit in the relevant channel Configuration Register.
//
//
CHAL_REG_WRITE32(pDmaDev->baseAddr + DMAC_INTTCCLEAR_OFFSET, 0x1<<channel);
CHAL_REG_WRITE32(pDmaDev->baseAddr + DMAC_INTERRCLR_OFFSET, 0x1<<channel);
temp = CHAL_REG_READ32(pDmaDev->baseAddr+DMAC_CH0CONFIG_OFFSET
+ CHAN_REG_INCREMENT * channel);
temp |= DMAC_CH0CONFIG_H_MASK;
CHAL_REG_WRITE32(pDmaDev->baseAddr + DMAC_CH0CONFIG_OFFSET
+ CHAN_REG_INCREMENT * channel, temp);
while (temp & DMAC_CH0CONFIG_A_MASK)
{
temp = CHAL_REG_READ32(pDmaDev->baseAddr+DMAC_CH0CONFIG_OFFSET
+ CHAN_REG_INCREMENT * channel);
}
temp &= ~DMAC_CH0CONFIG_E_MASK;
CHAL_REG_WRITE32(pDmaDev->baseAddr + DMAC_CH0CONFIG_OFFSET
+ CHAN_REG_INCREMENT * channel, temp);
chal_dma_mark_channel_inactive(handle, channel);
}
//******************************************************************************
//
// Function Name: chal_dma_enable_dmac
//
// Description: enable dma
//
//******************************************************************************
void chal_dma_enable_dmac(CHAL_HANDLE handle)
{
cUInt32 temp;
ChalDmaDev_t *pDmaDev = (ChalDmaDev_t *)handle;
temp = CHAL_REG_READ32(pDmaDev->baseAddr + DMAC_CONFIG_OFFSET);
if (temp & DMAC_CONFIG_E_MASK)
{
//TRACE_Printf_Sio("Already Ensabled");
}
else {
temp |= DMAC_CONFIG_E_MASK;
CHAL_REG_WRITE32(pDmaDev->baseAddr + DMAC_CONFIG_OFFSET, temp);
}
}
//******************************************************************************
//
// Function Name: chal_dma_disable_dmac
//
// Description: disable dma
//
//******************************************************************************
void chal_dma_disable_dmac(CHAL_HANDLE handle)
{
cUInt32 temp;
ChalDmaDev_t *pDmaDev = (ChalDmaDev_t *)handle;
temp = CHAL_REG_READ32(pDmaDev->baseAddr + DMAC_CONFIG_OFFSET);
if (!(temp & DMAC_CONFIG_E_MASK))
{
}
else {
temp &= ~DMAC_CONFIG_E_MASK;
CHAL_REG_WRITE32(pDmaDev->baseAddr + DMAC_CONFIG_OFFSET, temp);
}
}
//******************************************************************************
//
// Function Name: chal_dma_set_sync
//
// Description: Enables or disables synchronization logic for the DMA
// request signals. A bit set to 0 enables the synchronization
// logic for a particular group of DMA requests. A bit set to
// 1 disables the synchronization logic for a particular group
// of DMA requests. By default it is reset to 0, and synchronization
// logic enabled
//
//******************************************************************************
void chal_dma_set_sync(CHAL_HANDLE handle, cUInt16 mask)
{
ChalDmaDev_t *pDmaDev = (ChalDmaDev_t *)handle;
//
// You must use synchronization logic when the peripheral generating
// the DMA request runs on a different clock to the DMAC.
// For peripherals running on the same clock as the DMAC, disabling
// the synchronization logic improves the DMA request response
// time. If necessary, synchronize the DMA response signals, DMACCLR and
// DMACTC, in the peripheral.
//
//
CHAL_REG_WRITE32(pDmaDev->baseAddr + DMAC_SYNC_OFFSET, mask);
}
/*
* ******************************************************************************
*
* Function Name: chal_ipc_sleep_vc
*
* Description: VideoCore sleep
*
* ******************************************************************************
*/
BCM_ERR_CODE chal_ipc_sleep_vc (
CHAL_IPC_HANDLE handle
)
{
CHAL_IPC_DEV_T *device;
BCM_DBG_ENTER();
device = (CHAL_IPC_DEV_T*)handle;
CHAL_REG_WRITE32( device->ipc_secure_reg_base + IPCSEC_IPCAWAKE_OFFSET,
CHAL_REG_READ32( device->ipc_secure_reg_base + IPCSEC_IPCAWAKE_OFFSET ) &
~IPCSEC_IPCAWAKE_WAKEUP_MASK );
return BCM_SUCCESS;
}
/*
* ******************************************************************************
*
* Function Name: chal_ipc_wakeup_vc
*
* Description: Videocore wakeup
*
* ******************************************************************************
*/
BCM_ERR_CODE chal_ipc_wakeup_vc (
CHAL_IPC_HANDLE handle,
uint32_t address
)
{
CHAL_IPC_DEV_T *device;
BCM_DBG_ENTER();
device = (CHAL_IPC_DEV_T*)handle;
CHAL_REG_WRITE32(device->ipc_secure_reg_base + IPCSEC_IPCAWAKE_OFFSET,
address | IPCSEC_IPCAWAKE_WAKEUP_MASK );
BCM_DBG_EXIT();
return( BCM_SUCCESS );
}
//******************************************************************************
//
// Function Name: chal_dma_init
//
// Description: Initialize DMA hardware and software interface
//
//******************************************************************************
CHAL_HANDLE chal_dma_init(cUInt32 baseAddress)
{
int i;
ChalDmaDev_t *pDmaDev;
pDmaDev = &DmaDev;
pDmaDev->baseAddr = baseAddress;
CHAL_REG_WRITE32(pDmaDev->baseAddr + DMAC_INTTCCLEAR_OFFSET, 0xFF);
CHAL_REG_WRITE32(pDmaDev->baseAddr + DMAC_INTERRCLR_OFFSET, 0xFF);
//
// clear any m_DMAC_ENBLDCHNS before using dma
//
CHAL_REG_WRITE32(pDmaDev->baseAddr + DMAC_ENBLDCHNS_OFFSET, 0);
for (i=0; i<TOTAL_DMA_CHANNELS; i++)
CHAL_REG_WRITE32(pDmaDev->baseAddr + DMAC_CH0CONFIG_OFFSET
+ CHAN_REG_INCREMENT * i, 0);
//
// clear any PENDING interrupt
//
CHAL_REG_WRITE32(pDmaDev->baseAddr + DMAC_INTTCCLEAR_OFFSET, 0xFF);
CHAL_REG_WRITE32(pDmaDev->baseAddr + DMAC_INTERRCLR_OFFSET, 0xFF);
// disable DMA controller for now to save power
chal_dma_disable_dmac((CHAL_HANDLE)pDmaDev);
//populate capability info
pDmaDev->capabilities.numOfChannel = TOTAL_DMA_CHANNELS;
pDmaDev->capabilities.chanLLISize = DMA_LLI_NODE_SIZE;
pDmaDev->capabilities.maxBurstSize = DMA_MAX_BURST_SIZE;
pDmaDev->capabilities.maxXferSize = DMA_MAX_XFER_SIZE;
pDmaDev->capabilities.maxLLINodeNum = 0; //unlimited
pDmaDev->capabilities.fixedWordWidth = 0;
return (CHAL_HANDLE) pDmaDev;
}
//******************************************************************************
//
// Function Name: chal_dma_config_channel
//
// Description: Config a dma channel, i.e, in this case channel config reg
//
//******************************************************************************
cUInt32 chal_dma_config_channel(
CHAL_HANDLE handle,
cUInt32 chan,
cUInt32 assocChan,
ChalDmaChanConfig_t *pConfig
)
{
DmaChanConfig_t chanConfig;
cUInt32 bandRequested;
cUInt32 i, j, k, configChan;
ChalDmaDev_t *pDmaDev = (ChalDmaDev_t *)handle;
chal_dma_enable_dmac(handle);
chal_dma_reset_channel(handle, chan);
chanConfig.DWord = CHAL_REG_READ32(pDmaDev->baseAddr+DMAC_CH0CONFIG_OFFSET
+ CHAN_REG_INCREMENT * chan);
chanConfig.ChanConfigBitField.locked = pConfig->locked;
chanConfig.ChanConfigBitField.tcIntMask = pConfig->tcIntMask;
chanConfig.ChanConfigBitField.errIntMask = pConfig->errIntMask;
chanConfig.ChanConfigBitField.flowCtrl = pConfig->flowCtrl;
chanConfig.ChanConfigBitField.dstPeripheral = pConfig->dstPeripheral;
chanConfig.ChanConfigBitField.srcPeripheral = pConfig->srcPeripheral;
CHAL_REG_WRITE32(pDmaDev->baseAddr + DMAC_CH0CONFIG_OFFSET
+ CHAN_REG_INCREMENT * chan, chanConfig.DWord);
// chal_dma_disable_dmac(handle);
if(assocChan == ASSOC_CHAN_NONE)
{
configChan = chan;
}
else
{
configChan = TOTAL_DMA_CHANNELS + assocChan;
}
//allocate pre-allocated node
if(pDmaDev->chanInfo[configChan].bUsed == TRUE)
{
pDmaDev->chanInfo[configChan].bandNum = 0;
bandRequested = pConfig->nodeNumRequested/pDmaDev->nodeNumPerBand + 1; //always allocate at least a band
for(i=0;i<bandRequested;i++)
{
for(j=0;j<LLI_NODE_BAND_NUM; j++)
{
if(pDmaDev->LLIBand[j].bUsed == FALSE) //free band
{
pDmaDev->chanInfo[configChan].chanNodeBand[i] = &pDmaDev->LLIBand[j]; //reserve the band
pDmaDev->chanInfo[configChan].bandNum ++;
pDmaDev->LLIBand[j].bUsed = TRUE; //mark it
break;
}
}
if(j==LLI_NODE_BAND_NUM) //no more LLI node available
{
for(k=0;k<pDmaDev->chanInfo[configChan].bandNum;k++)
{
pDmaDev->chanInfo[configChan].chanNodeBand[k]->bUsed = FALSE;
}
pDmaDev->chanInfo[configChan].bandNum = 0; //reset count
pr_err("%s - exceeded available LLI's\n", __func__);
return 0;
}
}
}
return 1;
}
/*
* ===========================================================================
*
* Function Name: chal_memc_ddr3_init
*
* Description:
* Initialize MEMC controller for DDR3
*
* ===========================================================================
*/
MEMC_EXPORT BCM_ERR_CODE chal_memc_ddr3_init (
void* generic_hdl
)
{
uint32_t wrvalue = 0x0;
uint32_t base_addr = 0x0;
CHAL_MEMC_HANDLE handle = (CHAL_MEMC_HANDLE)generic_hdl;
if (!handle) {
BCM_DBG_ERR (("invalid argument: handle==0\n"));
return BCM_ERROR;
}
base_addr = handle->memc_open_reg_base;
if ( ddr3_clock_configuration( handle ) == BCM_ERROR )
{
BCM_DBG_ERR (("DDR3 Clock configuration failed\n"));
return BCM_ERROR;
}
/* Configure the strap settings */
if ( ddr3_strap_config( handle ) == BCM_ERROR )
{
BCM_DBG_ERR (("DDR3 Strap configuration failed\n"));
return BCM_ERROR;
}
/* Timing 0 : Based on 400MHz */
wrvalue = ( 0xe << CSR_DRAM_TIMING0_TRAS_SHIFT |
0x5 << CSR_DRAM_TIMING0_TWR_SHIFT |
0x3 << CSR_DRAM_TIMING0_TRTP_SHIFT |
0x5 << CSR_DRAM_TIMING0_TRP_PB_SHIFT |
0x5 << CSR_DRAM_TIMING0_TRP_AB_SHIFT |
0x3 << CSR_DRAM_TIMING0_TRRD_SHIFT |
0x5 << CSR_DRAM_TIMING0_TRCD_SHIFT );
CHAL_REG_WRITE32( base_addr + CSR_DRAM_TIMING0_OFFSET, wrvalue);
/* Timing 1 : Based on 400MHz */
wrvalue = ( 0x1 << CSR_DRAM_TIMING1_TDQSCK_SHIFT |
0x1C<< CSR_DRAM_TIMING1_TXSR_SHIFT |
0x4 << CSR_DRAM_TIMING1_TCKESR_SHIFT |
0x3 << CSR_DRAM_TIMING1_TXP_SHIFT |
0xF << CSR_DRAM_TIMING1_TFAW_SHIFT |
0x3 << CSR_DRAM_TIMING1_TWTR_SHIFT );
CHAL_REG_WRITE32( base_addr + CSR_DRAM_TIMING1_OFFSET, wrvalue);
if ( ddr3_auto_calibrate( handle ) == BCM_ERROR )
{
/* Auto-init failed */
BCM_DBG_ERR (("Auto-init failed\n"));
return BCM_ERROR;
}
if (handle->operation_mode == MEMC_OP_MODE_ASIC)
{
ddr3_auto_power_down_enable( handle, CHAL_MEMC_DDR3_POWER_DOWN_MODE_PRECHARGE );
}
/* software reset*/
CHAL_REG_WRITE32( base_addr + CSR_SOFT_RESET_OFFSET, 0);
/* configure the cl, cwl and wr in the DDR3 mode registers */
if ( ddr3_config_mode_registers( handle ) == BCM_ERROR )
{
BCM_DBG_ERR (("DDR3 Mode Register configuration failed\n"));
return BCM_ERROR;
}
/* Configure the DRAM start and end address, dram density, auto calculates memory size */
if ( ddr3_config_dram( handle ) == BCM_ERROR )
{
BCM_DBG_ERR (("DDR3 DRAM configuration failed\n"));
return BCM_ERROR;
}
/** @todo The tRFC and tREFI really need to be set based on the clock speed. */
if (handle->operation_mode == MEMC_OP_MODE_ASIC)
{
/* Values obtained from simulation test program */
handle->refresh_ctrl = (0x04<<CSR_REFRESH_CNTRL_PENDING_REFRESH_PRIORITY_COUNT_SHIFT |
0x1d<<CSR_REFRESH_CNTRL_TRFC_SHIFT |
0xcd<<CSR_REFRESH_CNTRL_REFRESH_PERIOD_SHIFT ) ; /* ru_div(7800/38.46)) */
}
else
{
/* Values obtained from simulation test program */
handle->refresh_ctrl = (0x2b<<CSR_REFRESH_CNTRL_TRFC_SHIFT |
0x65<<CSR_REFRESH_CNTRL_REFRESH_PERIOD_SHIFT ) ; /* ru_div(7800/76.92)) */
}
wrvalue = handle->refresh_ctrl;
CHAL_REG_WRITE32( base_addr + CSR_REFRESH_CNTRL_OFFSET, wrvalue);
/* ZQ Calibration timing */
wrvalue = ( 0xff<<CSR_DRAM_ZQ_CALIBRATION_TIMING_TZQCL_SHIFT |
0x40<<CSR_DRAM_ZQ_CALIBRATION_TIMING_TZQCS_SHIFT );
CHAL_REG_WRITE32( base_addr + CSR_DRAM_ZQ_CALIBRATION_TIMING_OFFSET, wrvalue);
CHAL_DELAY_MICROS (1); /* wait 1 us*/
/* init done */
wrvalue = CSR_SW_INIT_DONE_DONE_MASK;
CHAL_REG_WRITE32( base_addr + CSR_SW_INIT_DONE_OFFSET, wrvalue); /* 0x1*/
return(BCM_SUCCESS);
}
int chal_keypad_init(CHAL_KEYPAD_HANDLE_t * handle,
const CHAL_KEYPAD_CONFIG_t * config)
{
uint32_t temp;
int i;
if (!handle || !handle->regBaseAddr) {
return (-1);
}
if (!config ||
(config->columns > CHAL_KEYPAD_SCAN_COL_CNT) ||
(config->rows > CHAL_KEYPAD_SCAN_ROW_CNT) ||
(config->interruptEdge > CHAL_KEYPAD_INTERRUPT_EDGE_MAX) ||
(config->debounceTime > CHAL_KEYPAD_DEBOUNCE_MAX)
) {
return (-2);
}
/* Ensure things are inactive and in a known default state. */
chal_keypad_term(handle);
/* Use rows as output for scan. Need to set a bit for each row. */
temp = (1 << config->rows) - 1;
temp = temp << KEYPAD_KPIOR_ROWOCONTRL_SHIFT;
CHAL_REG_WRITE32(handle->regBaseAddr + KEYPAD_KPIOR_OFFSET, temp);
/* Configure the individual key interrupt controls. There's 2-bits for each key
* for this, spread over 4 32-bit registers. We will set all keys to the desired
* value, even though all keys might not be used. Create a 32-bit value with
* all the 2-bit fields set the same, and then write to the 4 registers.
*/
temp = 0;
for (i = 0; i < 32; i += 2) {
temp |= (config->interruptEdge << i);
}
CHAL_REG_WRITE32(handle->regBaseAddr + KEYPAD_KPEMR0_OFFSET, temp);
CHAL_REG_WRITE32(handle->regBaseAddr + KEYPAD_KPEMR1_OFFSET, temp);
CHAL_REG_WRITE32(handle->regBaseAddr + KEYPAD_KPEMR2_OFFSET, temp);
CHAL_REG_WRITE32(handle->regBaseAddr + KEYPAD_KPEMR3_OFFSET, temp);
/* Setup the hardware configuration register, including enable of keypad operations */
temp = KEYPAD_KPCR_ENABLE_MASK |
KEYPAD_KPCR_COLFILTERENABLE_MASK |
(config->debounceTime << KEYPAD_KPCR_COLUMNFILTERTYPE_SHIFT) |
KEYPAD_KPCR_STATUSFILTERENABLE_MASK |
(config->debounceTime << KEYPAD_KPCR_STATUSFILTERTYPE_SHIFT) |
((config->columns - 1) << KEYPAD_KPCR_COLUMNWIDTH_SHIFT) |
((config->rows - 1) << KEYPAD_KPCR_ROWWIDTH_SHIFT);
if (config->activeLowMode) {
temp |= KEYPAD_KPCR_MODE_MASK;
}
if (config->swapRowColumn) {
temp |= KEYPAD_KPCR_SWAPROWCOLUMN_MASK;
}
CHAL_REG_WRITE32(handle->regBaseAddr + KEYPAD_KPCR_OFFSET, temp);
return (0);
}
//******************************************************************************
//
// Function Name: chal_dma_start_transfer
//
// Description: Start a DMA transfer by reloading DMA registers
//
//******************************************************************************
void chal_dma_start_transfer(
CHAL_HANDLE handle,
cUInt32 channel,
cUInt32 assocChan
)
{
cUInt32 temp;
ChalDmaLinkNode_t *head;
DmaChanConfig_t config;
ChalDmaDev_t *pDmaDev = (ChalDmaDev_t *)handle;
//chal_dprintf(1, "chal_dma_start_transfer, channel = %d, assocChan = %d\n", channel, assocChan);
//
// wait the channel to be free
// You must fully initialize the channel before you enable it. Additionally, you must set the
// Enable bit of the DMAC before you enable any channels.
//
CHAL_REG_WRITE32(pDmaDev->baseAddr + DMAC_INTTCCLEAR_OFFSET, 0x1<<channel);
CHAL_REG_WRITE32(pDmaDev->baseAddr + DMAC_INTERRCLR_OFFSET, 0x1<<channel);
do
{
temp = CHAL_REG_READ32(pDmaDev->baseAddr + DMAC_ENBLDCHNS_OFFSET);
}while (temp & (0x1 << channel));
if(assocChan == ASSOC_CHAN_NONE)
{
//
// Mark channel active and enable DMA core
//
chal_dma_mark_channel_active(handle, channel);
//
// 1. Clear any pending interrupts on the channel you want to use.
// The privious channel operation might have left interrupts active.
// 2. Write the source address into the SRC Register.
// 3. Write the destination address into the DEST Register.
// 4. Write the address of the next SRC into the NEXT Register. If the transfer
// consists of a single packet of data, you must write 0 into this register.
// 5. Write the control information into the CONTROL Register.
// 6. Write the channel configuration information into the CONFIG register.
// 7. Set channel enable bit, then the DMA channel is automatically enabled.
//
head = pDmaDev->chanInfo[channel].headNode;
}
else
{
chal_dma_mark_channel_active(handle, TOTAL_DMA_CHANNELS + assocChan);
head = pDmaDev->chanInfo[TOTAL_DMA_CHANNELS + assocChan].headNode;
}
#if 0
chal_dprintf(1, "chal_dma_start_transfer, head->src = 0x%x\n", head->src);
chal_dprintf(1, "chal_dma_start_transfer, head->dst = 0x%x\n", head->dst);
chal_dprintf(1, "chal_dma_start_transfer, head->control.DWord = 0x%x\n", head->control.DWord);
chal_dprintf(1, "chal_dma_start_transfer, head->next = 0x%x\n", head->next);
#endif
//
// set up DMA for transfer
//
CHAL_REG_WRITE32(pDmaDev->baseAddr + DMAC_CH0CONTROL_OFFSET
+ CHAN_REG_INCREMENT * channel, head->control.DWord);
CHAL_REG_WRITE32(pDmaDev->baseAddr + DMAC_CH0SRCADDR_OFFSET
+ CHAN_REG_INCREMENT * channel, head->src);
CHAL_REG_WRITE32(pDmaDev->baseAddr + DMAC_CH0DESTADDR_OFFSET
+ CHAN_REG_INCREMENT * channel, head->dst);
CHAL_REG_WRITE32(pDmaDev->baseAddr + DMAC_CH0LLI_OFFSET
+ CHAN_REG_INCREMENT * channel, head->next);
config.DWord = CHAL_REG_READ32(pDmaDev->baseAddr+DMAC_CH0CONFIG_OFFSET
+ CHAN_REG_INCREMENT * channel);
config.ChanConfigBitField.chanEnabled = 1;
//chal_dprintf(1, "chal_dma_start_transfer, config.DWord = 0x%x\n", config.DWord);
CHAL_REG_WRITE32(pDmaDev->baseAddr + DMAC_CH0CONFIG_OFFSET
+ CHAN_REG_INCREMENT * channel, config.DWord);
}