static int stx7111_suspend_prepare(suspend_state_t state)
{
#ifdef CONFIG_PM_DEBUG
if (state == PM_SUSPEND_STANDBY) {
stx7111_wrt_table[0] = /* swith config */
ioread32(CLOCKGENA_BASE_ADDR + CKGA_CLKOPSRC_SWITCH_CFG(0));
stx7111_wrt_table[1] = /* clk_STNoc_ic */
ioread32(CLOCKGENA_BASE_ADDR + CKGA_OSC_DIV_CFG(0));
stx7111_wrt_table[2] = /* clk_ic_if_100 */
ioread32(CLOCKGENA_BASE_ADDR + CKGA_OSC_DIV_CFG(5));
} else
#endif
{
stx7111_wrt_table[0] = /* swith config */
ioread32(CLOCKGENA_BASE_ADDR + CKGA_CLKOPSRC_SWITCH_CFG(0));
stx7111_wrt_table[1] = /* swith config 1 */
ioread32(CLOCKGENA_BASE_ADDR + CKGA_CLKOPSRC_SWITCH_CFG(1));
stx7111_wrt_table[2] = /* clk_STNoc_ic */
ioread32(CLOCKGENA_BASE_ADDR + CKGA_OSC_DIV_CFG(0));
stx7111_wrt_table[3] = /* clk_ic_if_100 */
ioread32(CLOCKGENA_BASE_ADDR + CKGA_OSC_DIV_CFG(5));
stx7111_wrt_table[4] = /* clk_ic_if_200 */
ioread32(CLOCKGENA_BASE_ADDR + CKGA_OSC_DIV_CFG(17));
}
return 0;
}
#define _SYS_STA3_VALUE (13)
#define _SYS_CFG11 (7)
#define _SYS_CFG11_MASK (8)
#define _SYS_CFG38 (9)
#define _SYS_CFG38_MASK (10)
/* *************************
* STANDBY INSTRUCTION TABLE
* *************************
*/
#ifdef CONFIG_PM_DEBUG
static unsigned long stx7111_standby_table[] __cacheline_aligned = {
/* 1. Move all the clock on OSC */
CLK_POKE(CKGA_CLKOPSRC_SWITCH_CFG(0x0), 0x0),
CLK_POKE(CKGA_OSC_DIV_CFG(5), 29), /* clk_ic_if_100 @ 1 MHz to be safe for lirc */
IMMEDIATE_DEST(0x1f),
/* reduces the st40 frequency */
CLK_STORE(CKGA_OSC_DIV_CFG(4)),
/* reduces the clk_STNoc_ic */
CLK_STORE(CKGA_OSC_DIV_CFG(0x0)),
/* END. */
_END(),
IMMEDIATE_DEST(0x10000),
CLK_STORE(CKGA_PLL0LS_DIV_CFG(4)),
DATA_LOAD(0x0),
CLK_STORE(CKGA_CLKOPSRC_SWITCH_CFG(0x0)),
static int stx7111_suspend_core(suspend_state_t state, int suspending)
{
static unsigned char *clka_pll0_div;
static unsigned char *clka_pll1_div;
static unsigned long *clka_switch_cfg;
int i;
long pwr = 0x3; /* PLL_0/PLL_1 both OFF */
long cfg_0, cfg_1;
if (suspending)
goto on_suspending;
if (!clka_pll0_div) /* there was an error on suspending */
return 0;
/* Resuming... */
iowrite32(0, cga + CKGA_POWER_CFG);
while (!(ioread32(cga + CKGA_PLL(0)) & CKGA_PLL_LOCK))
;
while (!(ioread32(cga + CKGA_PLL(1)) & CKGA_PLL_LOCK))
;
/* applay the original parents */
iowrite32(clka_switch_cfg[0], cga + CKGA_CLKOPSRC_SWITCH_CFG(0));
iowrite32(clka_switch_cfg[1], cga + CKGA_CLKOPSRC_SWITCH_CFG(1));
/* restore all the clocks settings */
for (i = 0; i < 18; ++i) {
iowrite32(clka_pll0_div[i], cga +
((i < 4) ? CKGA_PLL0HS_DIV_CFG(i) :
CKGA_PLL0LS_DIV_CFG(i)));
iowrite32(clka_pll1_div[i], cga + CKGA_PLL1_DIV_CFG(i));
}
mdelay(10);
pr_devel("[STM][PM] ClockGen A: restored\n");
kfree(clka_pll0_div);
kfree(clka_pll1_div);
kfree(clka_switch_cfg);
clka_switch_cfg = NULL;
clka_pll0_div = clka_pll1_div = NULL;
stx7111_suspend_wake();
return 0;
on_suspending:
clka_pll0_div = kmalloc(sizeof(char) * 18, GFP_ATOMIC);
clka_pll1_div = kmalloc(sizeof(char) * 18, GFP_ATOMIC);
clka_switch_cfg = kmalloc(sizeof(long) * 2, GFP_ATOMIC);
if (!clka_pll0_div || !clka_pll1_div || !clka_switch_cfg)
goto error;
/* save the original settings */
clka_switch_cfg[0] = ioread32(cga + CKGA_CLKOPSRC_SWITCH_CFG(0));
clka_switch_cfg[1] = ioread32(cga + CKGA_CLKOPSRC_SWITCH_CFG(1));
for (i = 0; i < 18; ++i) {
clka_pll0_div[i] = ioread32(cga +
((i < 4) ? CKGA_PLL0HS_DIV_CFG(i) :
CKGA_PLL0LS_DIV_CFG(i)));
clka_pll1_div[i] = ioread32(cga + CKGA_PLL1_DIV_CFG(i));
}
pr_devel("[STM][PM] ClockGen A: saved\n");
mdelay(10);
/* to avoid the system is to much slow all
* the clocks are scaled @ 30 MHz
* the final setting is done in the tables
*/
for (i = 0; i < 18; ++i)
iowrite32(0, cga + CKGA_OSC_DIV_CFG(i));
/* almost all the clocks off, except some critical ones */
cfg_0 = 0xffffffff;
cfg_0 &= ~(0x3 << (2 * CLKA_ST40_ICK_ID));
cfg_0 &= ~(0x3 << (2 * CLKA_IC_IF_100_ID));
cfg_1 = 0xf;
cfg_1 &= ~(0x3 << (2 * (CLKA_IC_IF_200_ID - 16)));
if (wkd.stm_mac0_can_wakeup) {
unsigned long pll_id;
/* identify the eth_phy_clk */
pll_id = (clk_get_parent(ca_eth_phy_clk) == ca_pll1_clk) ?
2 : 1;
pwr &= ~pll_id;
cfg_0 &= ~(0x3 << (2 * CLKA_ETH_PHY_ID));
cfg_0 |= (pll_id << (2 * CLKA_ETH_PHY_ID));
}
if (wkd.hdmi_can_wakeup) {
/* Pll_1 on */
pwr &= ~2;
/* ic_if_100 under pll1 */
cfg_0 &= ~(0x3 << (2 * CLKA_IC_IF_100_ID));
cfg_0 |= (0x2 << (2 * CLKA_IC_IF_100_ID));
} else {
if (!wkd.lirc_can_wakeup)
clk_set_rate(ca_ic_if_100_clk,
clk_get_rate(ca_ref_clk)/32);
}
iowrite32(cfg_0, cga + CKGA_CLKOPSRC_SWITCH_CFG(0));
iowrite32(cfg_1, cga + CKGA_CLKOPSRC_SWITCH_CFG(1));
iowrite32(pwr, cga + CKGA_POWER_CFG);
return 0;
error:
kfree(clka_pll1_div);
kfree(clka_pll0_div);
kfree(clka_switch_cfg);
clka_switch_cfg = NULL;
clka_pll0_div = clka_pll1_div = NULL;
return -ENOMEM;
}
static int fli7510_suspend_core(suspend_state_t state, int suspending)
{
static unsigned char *clka_pll0_div;
static unsigned char *clka_pll1_div;
static unsigned long *clka_switch_cfg;
int i;
long pwr = 0x3; /* PLL_0/PLL_1 both OFF */
long cfg_0, cfg_1;
if (state == PM_SUSPEND_STANDBY)
return 0;
if (suspending)
goto on_suspending;
if (!clka_pll0_div) /* there was an error on suspending */
return 0;
/* Resuming... */
iowrite32(0, cga + CKGA_POWER_CFG);
while (!(ioread32(cga + CKGA_PLL(0)) & CKGA_PLL_LOCK))
;
while (!(ioread32(cga + CKGA_PLL(1)) & CKGA_PLL_LOCK))
;
/* applay the original parents */
iowrite32(clka_switch_cfg[0], cga + CKGA_CLKOPSRC_SWITCH_CFG(0));
iowrite32(clka_switch_cfg[1], cga + CKGA_CLKOPSRC_SWITCH_CFG(1));
/* restore all the clocks settings */
for (i = 0; i < 18; ++i) {
iowrite32(clka_pll0_div[i], cga +
((i < 4) ? CKGA_PLL0HS_DIV_CFG(i) :
CKGA_PLL0LS_DIV_CFG(i)));
iowrite32(clka_pll1_div[i], cga + CKGA_PLL1_DIV_CFG(i));
}
mdelay(10);
pr_devel("[STM][PM] ClockGen A: restored\n");
kfree(clka_pll0_div);
kfree(clka_pll1_div);
kfree(clka_switch_cfg);
clka_switch_cfg = NULL;
clka_pll0_div = clka_pll1_div = NULL;
/* Restore ic_if_100 to previous rate */
clk_set_parent(ca_ic_100_clk, ca_pll_clk);
clk_set_rate(ca_ic_100_clk, ca_ic_100_clk_rate);
return 0;
on_suspending:
clka_pll0_div = kmalloc(sizeof(char) * 18, GFP_ATOMIC);
clka_pll1_div = kmalloc(sizeof(char) * 18, GFP_ATOMIC);
clka_switch_cfg = kmalloc(sizeof(long) * 2, GFP_ATOMIC);
if (!clka_pll0_div || !clka_pll1_div || !clka_switch_cfg)
goto error;
/* save the original settings */
clka_switch_cfg[0] = ioread32(cga + CKGA_CLKOPSRC_SWITCH_CFG(0));
clka_switch_cfg[1] = ioread32(cga + CKGA_CLKOPSRC_SWITCH_CFG(1));
for (i = 0; i < 18; ++i) {
clka_pll0_div[i] = ioread32(cga +
((i < 4) ? CKGA_PLL0HS_DIV_CFG(i) :
CKGA_PLL0LS_DIV_CFG(i)));
clka_pll1_div[i] = ioread32(cga + CKGA_PLL1_DIV_CFG(i));
}
pr_devel("[STM][PM] ClockGen A: saved\n");
mdelay(10);
/* to avoid the system is to much slow all
* the clocks are scaled @ 30 MHz
* the final setting is done in the tables
*/
for (i = 0; i < 18; ++i)
iowrite32(0, cga + CKGA_OSC_DIV_CFG(i));
/* almost all the clocks off, except some critical ones */
cfg_0 = 0xffffff3f; /*
* Not clear why:
* - the Audio Dec. Clock can not disabled
*/
cfg_0 &= ~(0x3 << (2 * CLKA_ST40_HOST_ID));
cfg_0 &= ~(0x3 << (2 * CLKA_IC_100_ID));
cfg_0 &= ~(0x3 << (2 * CLKA_IC_150_ID));
cfg_1 = 0xff;
cfg_1 &= ~(0x3 << (2 * CLKA_IC_200_ID));
#if 0
if (wkd.eth_phy_can_wakeup) {
/* Pll_0 on */
pwr &= ~1;
/* eth_phy_clk under pll0 */
cfg_0 &= ~(0x3 << (2 * CLKA_ETH_PHY_ID));
cfg_0 |= (0x1 << (2 * CLKA_ETH_PHY_ID));
}
if (wkd.hdmi_can_wakeup) {
/* Pll_1 on */
pwr &= ~2;
/* ic_if_100 under pll1 */
cfg_0 &= ~(0x3 << (2 * CLKA_IC_IF_100_ID));
cfg_0 |= (0x2 << (2 * CLKA_IC_IF_100_ID));
} else {
if (!wkd.lirc_can_wakeup)
clk_set_rate(ca_ic_100_clk,
clk_get_rate(ca_ref_clk)/32);
}
#endif
iowrite32(cfg_0, cga + CKGA_CLKOPSRC_SWITCH_CFG(0));
iowrite32(cfg_1, cga + CKGA_CLKOPSRC_SWITCH_CFG(1));
iowrite32(pwr, cga + CKGA_POWER_CFG);
return 0;
error:
kfree(clka_pll1_div);
kfree(clka_pll0_div);
kfree(clka_switch_cfg);
clka_switch_cfg = NULL;
clka_pll0_div = clka_pll1_div = NULL;
return -ENOMEM;
}
static int stx7105_suspend_core(suspend_state_t state, int suspending)
{
static unsigned char *clka_pll0_div;
static unsigned char *clka_pll1_div;
static unsigned long *clka_switch_cfg;
static unsigned long saved_gplmi_appd;
int i;
if (suspending)
goto on_suspending;
if (!clka_pll0_div) /* there was an error on suspending */
return 0;
/* Resuming... */
iowrite32(0, cga + CKGA_POWER_CFG);
while (!(ioread32(cga + CKGA_PLL(0)) & CKGA_PLL_LOCK))
;
while (!(ioread32(cga + CKGA_PLL(1)) & CKGA_PLL_LOCK))
;
/* applay the original parents */
iowrite32(clka_switch_cfg[0], cga + CKGA_CLKOPSRC_SWITCH_CFG(0));
iowrite32(clka_switch_cfg[1], cga + CKGA_CLKOPSRC_SWITCH_CFG(1));
/* restore all the clocks settings */
for (i = 0; i < 18; ++i) {
iowrite32(clka_pll0_div[i], ((i < 4) ?
cga + CKGA_PLL0HS_DIV_CFG(i) :
cga + CKGA_PLL0LS_DIV_CFG(i)));
iowrite32(clka_pll1_div[i], cga + CKGA_PLL1_DIV_CFG(i));
}
mdelay(10);
pr_devel("[STM][PM] ClockGen A: restored\n");
/* restore the APPD */
iowrite32(saved_gplmi_appd, LMI_APPD(0));
kfree(clka_pll0_div);
kfree(clka_pll1_div);
kfree(clka_switch_cfg);
clka_switch_cfg = NULL;
clka_pll0_div = clka_pll1_div = NULL;
stx7105_suspend_wake();
return 0;
on_suspending:
clka_pll0_div = kmalloc(sizeof(char) * 18, GFP_ATOMIC);
clka_pll1_div = kmalloc(sizeof(char) * 18, GFP_ATOMIC);
clka_switch_cfg = kmalloc(sizeof(long) * 2, GFP_ATOMIC);
if (!clka_pll0_div || !clka_pll1_div || !clka_switch_cfg)
goto error;
/* save the current APPD setting*/
saved_gplmi_appd = ioread32(LMI_APPD(0));
/* disable the APPD */
iowrite32(0x0, LMI_APPD(0));
/* save the original settings */
clka_switch_cfg[0] = ioread32(cga + CKGA_CLKOPSRC_SWITCH_CFG(0));
clka_switch_cfg[1] = ioread32(cga + CKGA_CLKOPSRC_SWITCH_CFG(1));
for (i = 0; i < 18; ++i) {
clka_pll0_div[i] = ioread32(((i < 4) ?
cga + CKGA_PLL0HS_DIV_CFG(i) :
cga + CKGA_PLL0LS_DIV_CFG(i)));
clka_pll1_div[i] = ioread32(cga + CKGA_PLL1_DIV_CFG(i));
}
pr_devel("[STM][PM] ClockGen A: saved\n");
mdelay(10);
/* to avoid the system is to much slow all
* the clocks are scaled @ 30 MHz
* the final setting is done in the tables
*/
for (i = 0; i < 18; ++i)
iowrite32(0, cga + CKGA_OSC_DIV_CFG(i));
/* almost all the clocks off */
iowrite32(0xfffff0ff, cga + CKGA_CLKOPSRC_SWITCH_CFG(0));
iowrite32(0x3, cga + CKGA_CLKOPSRC_SWITCH_CFG(1));
if (wkd.hdmi_can_wakeup || wkd.eth_phy_can_wakeup) {
unsigned long pwr = 0x3; /* Plls Off */
unsigned long cfg = 0xfffff0ff;
#define CLKA_IC_IF_100_ID 5
#define CLKA_ETH0_PHY_ID 13
if (wkd.hdmi_can_wakeup) {
/* needs PLL1 on */
pwr &= ~2;
cfg &= ~(0x3 << (2 * CLKA_IC_IF_100_ID));
cfg |= (0x2 << (2 * CLKA_IC_IF_100_ID));
}
if (wkd.eth_phy_can_wakeup) {
/* needs PLL1 on */
pwr &= ~2;
cfg &= ~(0x3 << (2 * CLKA_ETH0_PHY_ID));
cfg |= (0x2 << (2 * CLKA_ETH0_PHY_ID));
}
iowrite32(cfg, cga + CKGA_CLKOPSRC_SWITCH_CFG(0));
iowrite32(pwr, cga + CKGA_POWER_CFG);
} else {
iowrite32(3, cga + CKGA_POWER_CFG);
if (!wkd.lirc_can_wakeup)
clk_set_rate(ca_ic_if_100_clk,
clk_get_rate(ca_ref_clk)/32);
}
return 0;
error:
kfree(clka_pll1_div);
kfree(clka_pll0_div);
kfree(clka_switch_cfg);
clka_switch_cfg = NULL;
clka_pll0_div = clka_pll1_div = NULL;
return -ENOMEM;
}