CLK(id, NORATE, NULL, glbl, NULL, NULL, 0, h_r, h_c, \
h_b, br, 0, 0, 0, NULL, NULL, NULL, NONE, NULL, tv)
#define CLK_BRIDGE(id, glbl, br, par, h_r, h_c, h_b, tv) \
CLK(id, NORATE, NULL, glbl, NULL, NULL, 0, h_r, h_c, \
h_b, br, 0, 0, 0, NULL, NULL, NULL, par, NULL, tv)
/*
* Clock table
*/
static struct clk_local soc_clk_local_tbl_7x30[] = {
CLK_NORATE(MDC, MDC_NS_REG, B(9), B(11),
CLK_HALT_STATEA_REG, HALT, 10, 0x4D56),
CLK_NORATE(LPA_CORE, LPA_NS_REG, B(5), 0,
CLK_HALT_STATEC_REG, HALT, 5, 0x0E),
CLK_1RATE(I2C, I2C_NS_REG, B(9), B(11), clk_tbl_tcxo,
CLK_HALT_STATEA_REG, HALT, 15, 0x4D4D),
CLK_1RATE(I2C_2, I2C_2_NS_REG, B(0), B(2), clk_tbl_tcxo,
CLK_HALT_STATEC_REG, HALT, 2, 0x0B),
CLK_1RATE(QUP_I2C, QUP_I2C_NS_REG, B(0), B(2), clk_tbl_tcxo,
CLK_HALT_STATEB_REG, HALT, 31, 0x1C),
CLK_1RATE(UART1, UART_NS_REG, B(5), B(4), clk_tbl_tcxo,
CLK_HALT_STATEB_REG, HALT, 7, 0x4D6F),
CLK_1RATE(UART2, UART2_NS_REG, B(5), B(4), clk_tbl_tcxo,
CLK_HALT_STATEB_REG, HALT, 5, 0x4D71),
CLK_BASIC(EMDH, EMDH_NS_REG, 0, B(11), clk_tbl_mdh, AXI_LI_ADSP_A,
NULL, DELAY, 0, 0x4F00),
CLK_BASIC(PMDH, PMDH_NS_REG, 0, B(11), clk_tbl_mdh, AXI_LI_ADSP_A,
NULL, DELAY, 0, 0x5500),
CLK_BASIC(MDP, MDP_NS_REG, B(9), B(11), clk_tbl_mdp_core, AXI_MDP,
CLK_HALT_STATEB_REG, HALT, 16, 0x5400),
.br_en_mask = br, \
.test_vector = tv, \
.parent = L_##par##_CLK, \
.current_freq = &local_dummy_freq, \
}
/*
* Clock table
*/
struct clk_local soc_clk_local_tbl[] = {
CLK_NORATE(MDC, MDC_NS_REG, BIT(9), BIT(11),
CLK_HALT_STATEA_REG, HALT, 10, 0x4D56),
CLK_NORATE(LPA_CORE, LPA_NS_REG, BIT(5), 0,
CLK_HALT_STATEC_REG, HALT, 5, 0x0E),
CLK_1RATE(I2C, I2C_NS_REG, BIT(9), BIT(11), clk_tbl_tcxo,
CLK_HALT_STATEA_REG, HALT, 15, 0x4D4D),
CLK_1RATE(I2C_2, I2C_2_NS_REG, BIT(0), BIT(2), clk_tbl_tcxo,
CLK_HALT_STATEC_REG, HALT, 2, 0x0B),
CLK_1RATE(QUP_I2C, QUP_I2C_NS_REG, BIT(0), BIT(2), clk_tbl_tcxo,
CLK_HALT_STATEB_REG, HALT, 31, 0x1C),
CLK_1RATE(UART1, UART_NS_REG, BIT(5), BIT(4), clk_tbl_tcxo,
CLK_HALT_STATEB_REG, HALT, 7, 0x4D6F),
CLK_1RATE(UART2, UART2_NS_REG, BIT(5), BIT(4), clk_tbl_tcxo,
CLK_HALT_STATEB_REG, HALT, 5, 0x4D71),
CLK_BASIC(EMDH, EMDH_NS_REG, 0, BIT(11), clk_tbl_mdh, AXI_LI_ADSP_A,
NULL, DELAY, 0, 0x4F00),
CLK_BASIC(PMDH, PMDH_NS_REG, 0, BIT(11), clk_tbl_mdh, AXI_LI_ADSP_A,
NULL, DELAY, 0, 0x5500),
CLK_BASIC(MDP, MDP_NS_REG, BIT(9), BIT(11), clk_tbl_mdp_core, AXI_MDP,
CLK_HALT_STATEB_REG, HALT, 16, 0x5400),
