/*!
* @brief Main function
*/
int main(void)
{
volatile uint32_t i;
uint32_t sysFreq;
/* Structure for OSC configuration */
osc_config_t oscConfig;
oscConfig.freq = BOARD_XTAL0_CLK_HZ;
oscConfig.capLoad = 0U;
oscConfig.workMode = kOSC_ModeOscLowPower;
oscConfig.oscerConfig.enableMode = kOSC_ErClkEnable;
BOARD_InitPins();
CLOCK_InitOsc0(&oscConfig);
CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);
/* Set clock divider to safe value to switch mode */
CLOCK_SetSimSafeDivs();
#if (defined(FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE) && FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE)
/* Calculate frdiv */
if (!APP_GetAvailableFrdiv())
{
while (1)
{
}
}
#endif /* FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE || FSL_FEATURE_MCG_USE_PLLREFSEL */
/* Configure pll */
if (!APP_GetAvailablePllConfig(&g_pllConfig))
{
while (1)
{
}
}
APP_BootToPeeExample();
/* Change clock PEE -> PBE -> BLPE */
APP_ChangePeeToBlpeExample();
/* Change clock BLPE -> PBE -> PEE */
APP_ChangeBlpeToPeeExample();
/* Get System clock to blink a LED */
sysFreq = CLOCK_GetFreq(kCLOCK_CoreSysClk) / 20U;
/* Enable a LED */
LED_INIT();
/* Blink a LED */
while (1)
{
for (i = 0; i < sysFreq; i++)
{
__NOP();
}
LED_TOGGLE();
}
}
/*FUNCTION**********************************************************************
*
* Function Name : BOARD_InitOsc0
* Description : This function is used to setup MCG OSC with Ref oscillator for KW40_512.
*
*END**************************************************************************/
void BOARD_InitOsc0(void)
{
const osc_config_t oscConfig = {
.freq = BOARD_XTAL0_CLK_HZ, .workMode = kOSC_ModeExt,
};
/* Initializes OSC0 according to previous configuration to meet Ref OSC needs. */
CLOCK_InitOsc0(&oscConfig);
/* Passing the XTAL0 frequency to clock driver. */
CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);
}
/*!
* @brief Main function
*/
int main(void)
{
volatile uint32_t i;
uint32_t sysFreq;
/* Structure for OSC configuration */
osc_config_t oscConfig;
oscConfig.freq = BOARD_XTAL0_CLK_HZ;
oscConfig.capLoad = 0U;
oscConfig.workMode = kOSC_ModeOscLowPower;
oscConfig.oscerConfig.enableMode = kOSC_ErClkEnable;
BOARD_InitPins();
CLOCK_InitOsc0(&oscConfig);
CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);
/* Set clock divider to safe value to switch mode */
CLOCK_SetSimSafeDivs();
/* Calculate frdiv */
if (!APP_GetAvailableFrdiv())
{
while (1)
{
}
}
/* Boot to Fee mode */
APP_BootToFeeExample();
/* Change clock FEE -> FBE -> BLPE */
APP_ChangeFeeToBlpeExample();
/* Change clock BLPE -> FBE -> FEE */
APP_ChangeBlpeToFeeExample();
/* Get System clock to blink a LED */
sysFreq = CLOCK_GetFreq(kCLOCK_CoreSysClk) / 20U;
/* Enable a LED */
LED_INIT();
/* Blink a LED */
while (1)
{
for (i = 0; i < sysFreq; i++)
{
__NOP();
}
LED_TOGGLE();
}
}
void BOARD_BootClockRUN(void)
{
CLOCK_SetSimSafeDivs();
CLOCK_InitOsc0(&g_defaultClockConfigRun.oscConfig);
CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);
CLOCK_BootToPeeMode(g_defaultClockConfigRun.mcgConfig.oscsel, kMCG_PllClkSelPll0,
&g_defaultClockConfigRun.mcgConfig.pll0Config);
CLOCK_SetInternalRefClkConfig(g_defaultClockConfigRun.mcgConfig.irclkEnableMode,
g_defaultClockConfigRun.mcgConfig.ircs, g_defaultClockConfigRun.mcgConfig.fcrdiv);
CLOCK_SetSimConfig(&g_defaultClockConfigRun.simConfig);
SystemCoreClock = g_defaultClockConfigRun.coreClock;
}
/**
*
* @brief Initialize the system clock
*
* This routine will configure the multipurpose clock generator (MCG) to
* set up the system clock.
* The MCG has nine possible modes, including Stop mode. This routine assumes
* that the current MCG mode is FLL Engaged Internal (FEI), as from reset.
* It transitions through the FLL Bypassed External (FBE) and
* PLL Bypassed External (PBE) modes to get to the desired
* PLL Engaged External (PEE) mode and generate the maximum 120 MHz system
* clock.
*
* @return N/A
*
*/
static ALWAYS_INLINE void clkInit(void)
{
CLOCK_SetSimSafeDivs();
CLOCK_InitOsc0(&oscConfig);
CLOCK_SetXtal0Freq(CONFIG_OSC_XTAL0_FREQ);
CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0Config);
CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow,
CONFIG_MCG_FCRDIV);
CLOCK_SetSimConfig(&simConfig);
#if CONFIG_ETH_MCUX
CLOCK_SetEnetTime0Clock(TIMESRC_OSCERCLK);
#endif
#if CONFIG_USB_KINETIS
CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcPll0,
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
#endif
}
void BOARD_BootClockHSRUN(void)
{
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
SMC_SetPowerModeHsrun(SMC);
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
{
}
CLOCK_SetSimSafeDivs();
CLOCK_InitOsc0(&g_defaultClockConfigHsrun.oscConfig);
CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);
CLOCK_BootToPeeMode(g_defaultClockConfigHsrun.mcgConfig.oscsel, kMCG_PllClkSelPll0,
&g_defaultClockConfigHsrun.mcgConfig.pll0Config);
CLOCK_SetInternalRefClkConfig(g_defaultClockConfigHsrun.mcgConfig.irclkEnableMode,
g_defaultClockConfigHsrun.mcgConfig.ircs, g_defaultClockConfigHsrun.mcgConfig.fcrdiv);
CLOCK_SetSimConfig(&g_defaultClockConfigHsrun.simConfig);
SystemCoreClock = g_defaultClockConfigHsrun.coreClock;
}
void BOARD_BootClockVLPR(void)
{
/*
* Core clock: 4MHz
* Bus clock: 4MHz
*/
const sim_clock_config_t simConfig = {
.pllFllSel = 0U, /* PLLFLLSEL select MCG FLL. */
.er32kSrc = 2U, /* ERCLK32K selection, use RTC. */
.clkdiv1 = 0x00040000U, /* SIM_CLKDIV1. */
};
CLOCK_SetSimSafeDivs();
CLOCK_BootToBlpiMode(0U, kMCG_IrcFast, kMCG_IrclkEnable);
CLOCK_SetSimConfig(&simConfig);
SystemCoreClock = 4000000U;
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
SMC_SetPowerModeVlpr(SMC);
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
{
}
}
void BOARD_BootClockRUN(void)
{
/*
* Core clock: 72MHz
* Bus clock: 36MHz
* Flash clock: 26MHz
*/
const mcg_pll_config_t pll0Config = {
.enableMode = 0U, .prdiv = 0x07U, .vdiv = 0x0CU,
};
const sim_clock_config_t simConfig = {
.pllFllSel = 1U, /* PLLFLLSEL select MCG PLL. */
.er32kSrc = 3U, /* ERCLK32K selection, use LPO 1 kHz. */
.clkdiv1 = 0x01020000U, /* SIM_CLKDIV1. */
};
CLOCK_SetSimSafeDivs();
BOARD_InitOsc0();
CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0Config);
CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow, 0);
CLOCK_SetSimConfig(&simConfig);
SystemCoreClock = 72000000U;
}
void BOARD_InitOsc0(void)
{
const osc_config_t oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
.capLoad = 10,
.workMode = kOSC_ModeExt,
.oscerConfig = {
.enableMode = kOSC_ErClkEnable,
#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
.erclkDiv = 0U,
#endif
}};
CLOCK_InitOsc0(&oscConfig);
/* Passing the XTAL0 frequency to clock driver. */
CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);
/* Use RTC_CLKIN input clock directly. */
CLOCK_SetXtal32Freq(BOARD_XTAL32K_CLK_HZ);
}
void BOARD_BootClockVLPR(void)
{
/*
* Core clock: 4MHz
*/
const sim_clock_config_t simConfig = {
.pllFllSel = 3U, /* PLLFLLSEL select IRC48MCLK. */
.pllFllDiv = 0U, /* PLLFLLSEL clock divider divisor. */
.pllFllFrac = 0U, /* PLLFLLSEL clock divider fraction. */
.er32kSrc = 2U, /* ERCLK32K selection, use RTC. */
.clkdiv1 = 0x03040000U, /* SIM_CLKDIV1. */
};
CLOCK_SetSimSafeDivs();
CLOCK_BootToBlpiMode(0U, kMCG_IrcFast, kMCG_IrclkEnable);
CLOCK_SetSimConfig(&simConfig);
SystemCoreClock = 4000000U;
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
SMC_SetPowerModeVlpr(SMC);
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
{
}
}
void BOARD_BootClockRUN(void)
{
/*
* Core clock: 72MHz
*/
const mcg_pll_config_t pll0Config = {
.enableMode = 0U, .prdiv = 0x00U, .vdiv = 0x08U,
};
const sim_clock_config_t simConfig = {
.pllFllSel = 1U, /* PLLFLLSEL select PLL. */
.pllFllDiv = 0U, /* PLLFLLSEL clock divider divisor. */
.pllFllFrac = 0U, /* PLLFLLSEL clock divider fraction. */
.er32kSrc = 2U, /* ERCLK32K selection, use RTC. */
.clkdiv1 = 0x15051000U, /* SIM_CLKDIV1. */
};
CLOCK_SetSimSafeDivs();
BOARD_InitOsc0();
CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0Config);
CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow, 0);
CLOCK_SetSimConfig(&simConfig);
SystemCoreClock = 72000000U;
}
void BOARD_BootClockHSRUN(void)
{
/*
* Core clock: 96MHz
*/
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
SMC_SetPowerModeHsrun(SMC);
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
{
}
CLOCK_SetSimSafeDivs();
BOARD_InitOsc0();
const sim_clock_config_t simConfig = {
.pllFllSel = 1U, /* PLLFLLSEL select PLL. */
.pllFllDiv = 0U, /* PLLFLLSEL clock divider divisor. */
.pllFllFrac = 0U, /* PLLFLLSEL clock divider fraction. */
.er32kSrc = 2U, /* ERCLK32K selection, use RTC. */
.clkdiv1 = 0x03030000U, /* SIM_CLKDIV1. */
};
const mcg_pll_config_t pll0Config = {
.enableMode = 0U, .prdiv = 0x00U, .vdiv = 0x00U,
};
CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0Config);
CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow, 0);
CLOCK_SetSimConfig(&simConfig);
SystemCoreClock = 96000000U;
}
void BOARD_InitOsc0(void)
{
const osc_config_t oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
.capLoad = 0,
.workMode = kOSC_ModeOscLowPower,
.oscerConfig = {
.enableMode = kOSC_ErClkEnable,
#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
.erclkDiv = 0U,
#endif
}};
CLOCK_InitOsc0(&oscConfig);
/* Passing the XTAL0 frequency to clock driver. */
CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);
CLOCK_SetXtal32Freq(BOARD_XTAL32K_CLK_HZ);
}
static ALWAYS_INLINE void clkInit(void)
{
/*
* Core clock: 48MHz
* Bus clock: 24MHz
*/
const mcg_pll_config_t pll0Config = {
.enableMode = 0U, .prdiv = CONFIG_MCG_PRDIV0, .vdiv = CONFIG_MCG_VDIV0,
};
const sim_clock_config_t simConfig = {
.pllFllSel = 1U, /* PLLFLLSEL select PLL. */
.er32kSrc = 3U, /* ERCLK32K selection, use LPO. */
.clkdiv1 = 0x10010000U, /* SIM_CLKDIV1. */
};
const osc_config_t oscConfig = {.freq = CONFIG_OSC_XTAL0_FREQ,
.capLoad = 0,
#if defined(CONFIG_OSC_EXTERNAL)
.workMode = kOSC_ModeExt,
#elif defined(CONFIG_OSC_LOW_POWER)
.workMode = kOSC_ModeOscLowPower,
#elif defined(CONFIG_OSC_HIGH_GAIN)
.workMode = kOSC_ModeOscHighGain,
#else
#error "An oscillator mode must be defined"
#endif
.oscerConfig = {
.enableMode = kOSC_ErClkEnable,
#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && \
FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
.erclkDiv = 0U,
#endif
} };
CLOCK_SetSimSafeDivs();
CLOCK_InitOsc0(&oscConfig);
/* Passing the XTAL0 frequency to clock driver. */
CLOCK_SetXtal0Freq(CONFIG_OSC_XTAL0_FREQ);
CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0Config);
CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow, 0);
CLOCK_SetSimConfig(&simConfig);
#ifdef CONFIG_UART_MCUX_LPSCI_0
CLOCK_SetLpsci0Clock(LPSCI0SRC_MCGFLLCLK);
#endif
}
static int kl2x_init(struct device *arg)
{
ARG_UNUSED(arg);
int oldLevel; /* old interrupt lock level */
/* disable interrupts */
oldLevel = irq_lock();
/* Disable the watchdog */
SIM->COPC = 0;
/* Initialize system clock to 48 MHz */
clkInit();
/*
* install default handler that simply resets the CPU
* if configured in the kernel, NOP otherwise
*/
NMI_INIT();
/* restore interrupt state */
irq_unlock(oldLevel);
return 0;
}
SYS_INIT(kl2x_init, PRE_KERNEL_1, 0);
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockVLPR
outputs:
- {id: Bus_clock.outFreq, value: 800 kHz}
- {id: Core_clock.outFreq, value: 4 MHz}
- {id: Flash_clock.outFreq, value: 800 kHz}
- {id: LPO_clock.outFreq, value: 1 kHz}
- {id: MCGIRCLK.outFreq, value: 4 MHz}
- {id: System_clock.outFreq, value: 4 MHz}
settings:
- {id: MCGMode, value: BLPI}
- {id: powerMode, value: VLPR}
- {id: MCG.CLKS.sel, value: MCG.IRCS}
- {id: MCG.FCRDIV.scale, value: '1'}
- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
- {id: SIM.OUTDIV4.scale, value: '5'}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
void BOARD_BootClockVLPR(void)
{
const sim_clock_config_t simConfig = {
.er32kSrc = 0U, .clkdiv1 = 0x00040000U,
};
/* ERR010224 */
RSIM->RF_OSC_CTRL |= RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK; /* Prevent XTAL_OUT_EN from generating XTAL_OUT request */
CLOCK_SetSimSafeDivs();
CLOCK_BootToBlpiMode(0U, kMCG_IrcFast, kMCG_IrclkEnable);
CLOCK_SetSimConfig(&simConfig);
SystemCoreClock = 4000000U;
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
SMC_SetPowerModeVlpr(SMC);
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
{
}
}
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockRUN
called_from_default_init: true
outputs:
- {id: Bus_clock.outFreq, value: 20 MHz}
- {id: Core_clock.outFreq, value: 40 MHz}
- {id: Flash_clock.outFreq, value: 20 MHz}
- {id: LPO_clock.outFreq, value: 1 kHz}
- {id: MCGFLLCLK.outFreq, value: 40 MHz}
- {id: MCGIRCLK.outFreq, value: 32.768 kHz}
- {id: OSCERCLK.outFreq, value: 32 MHz}
- {id: System_clock.outFreq, value: 40 MHz}
settings:
- {id: MCGMode, value: FEE}
- {id: MCG.FCRDIV.scale, value: '1'}
- {id: MCG.FLL_mul.scale, value: '1280'}
- {id: MCG.FRDIV.scale, value: '1024'}
- {id: MCG.IREFS.sel, value: MCG.FRDIV}
- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
- {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
- {id: MCG_C2_RANGE_CFG, value: Very_high}
- {id: RTC_CR_OSCE_CFG, value: Oscillator_enabled}
sources:
- {id: REFOSC.OSC.outFreq, value: 32 MHz, enabled: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
void BOARD_BootClockRUN(void)
{
const sim_clock_config_t simConfig = {
.er32kSrc = 0U, .clkdiv1 = 0x00010000U,
};
BOARD_RfOscInit();
CLOCK_SetSimSafeDivs();
BOARD_InitOsc0();
CLOCK_BootToFeeMode(kMCG_OscselOsc, 5U, kMCG_Dmx32Default, kMCG_DrsMid, CLOCK_SYS_FllStableDelay);
CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow, 0U);
CLOCK_SetSimConfig(&simConfig);
SystemCoreClock = 40000000U;
}
void BOARD_RfOscInit(void)
{
uint32_t temp, tempTrim;
uint8_t revId;
/* Obtain REV ID from SIM */
temp = SIM->SDID;
revId = (uint8_t)((temp & SIM_SDID_REVID_MASK) >> SIM_SDID_REVID_SHIFT);
if(0 == revId)
{
tempTrim = RSIM->ANA_TRIM;
RSIM->ANA_TRIM |= RSIM_ANA_TRIM_BB_LDO_XO_TRIM_MASK; /* Set max trim for BB LDO for XO */
}/* Workaround for Rev 1.0 XTAL startup and ADC analog diagnostics circuitry */
/* Turn on clocks for the XCVR */
/* Enable RF OSC in RSIM and wait for ready */
temp = RSIM->CONTROL;
temp &= ~RSIM_CONTROL_RF_OSC_EN_MASK;
RSIM->CONTROL = temp | RSIM_CONTROL_RF_OSC_EN(1);
/* ERR010224 */
RSIM->RF_OSC_CTRL |= RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK; /* Prevent XTAL_OUT_EN from generating XTAL_OUT request */
while((RSIM->CONTROL & RSIM_CONTROL_RF_OSC_READY_MASK) == 0); /* Wait for RF_OSC_READY */
if(0 == revId)
{
SIM->SCGC5 |= SIM_SCGC5_PHYDIG_MASK;
XCVR_TSM->OVRD0 |= XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_EN_MASK | XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_MASK; /* Force ADC DAC LDO on to prevent BGAP failure */
RSIM->ANA_TRIM = tempTrim; /* Reset LDO trim settings */
}/* Workaround for Rev 1.0 XTAL startup and ADC analog diagnostics circuitry */
}
void BOARD_InitOsc0(void)
{
const osc_config_t oscConfig = {
.freq = BOARD_XTAL0_CLK_HZ, .workMode = kOSC_ModeExt,
};
CLOCK_InitOsc0(&oscConfig);
/* Passing the XTAL0 frequency to clock driver. */
CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);
}
void BOARD_BootClockVLPR(void)
{
/*
* Core clock: 4MHz
*/
const sim_clock_config_t simConfig = {
.pllFllSel = 0U, /* PLLFLLSEL select FLL. */
.er32kSrc = 2U, /* ERCLK32K selection, use RTC. */
.clkdiv1 = 0x00030000U, /* SIM_CLKDIV1. */
};
CLOCK_SetSimSafeDivs();
CLOCK_BootToBlpiMode(0U, kMCG_IrcFast, kMCG_IrclkEnable);
CLOCK_SetSimConfig(&simConfig);
SystemCoreClock = 4000000U;
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
SMC_SetPowerModeVlpr(SMC, false);
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
{
}
}
void BOARD_BootClockRUN(void)
{
/*
* Core clock: 48MHz
* Bus clock: 24MHz
*/
const mcg_pll_config_t pll0Config = {
.enableMode = 0U,
.prdiv = 0x1U,
.vdiv = 0x0U,
};
const sim_clock_config_t simConfig = {
.pllFllSel = 1U, /* PLLFLLSEL select PLL. */
.er32kSrc = 2U, /* ERCLK32K selection, use RTC. */
.clkdiv1 = 0x00010000U, /* SIM_CLKDIV1. */
};
/* Perform initialization of the wireless modem clock output */
if (BOARD_ExtClk_Setup_HookUp(BOARD_XTAL0_CLK_HZ) != 1U)
{
/* If the initialization was not successfully, do not continue with clock setup */
return;
}
CLOCK_SetSimSafeDivs();
BOARD_InitOsc0();
CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0Config);
CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow, 0);
CLOCK_SetSimConfig(&simConfig);
SystemCoreClock = 48000000U;
}
void BOARD_InitOsc0(void)
{
const osc_config_t oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
.capLoad = 0,
.workMode = kOSC_ModeOscLowPower,
.oscerConfig = {
.enableMode = kOSC_ErClkEnable | kOSC_ErClkEnableInStop,
#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
.erclkDiv = 0U,
#endif
}};
CLOCK_InitOsc0(&oscConfig);
/* Passing the XTAL0 frequency to clock driver. */
CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);
}