/*! * @brief LLWU ISR function */ void llwu_isr(void) { uint8_t pinEn; NVIC_ClearPendingIRQ(LLW_IRQn); /* Print LLWU acknowledgement only if UART is enabled */ for(pinEn = 0; pinEn < FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN; pinEn++) { if (LLWU_HAL_GetExternalPinWakeupFlag(LLWU_BASE, (llwu_wakeup_pin_t)pinEn)) { LLWU_HAL_ClearExternalPinWakeupFlag(LLWU_BASE, (llwu_wakeup_pin_t)pinEn); /* write one to clear the flag */ } } /* * Note: This ISR does not write to the LLWU_F3 register because these * are peripheral module wakeups. The flags contained in the LLWU_F3 * register should be cleared through the associated module interrupt * and not through the LLWU_F3 per the Kinetis L Family Reference * Manual (LLWU Chapter) */ if (LLWU_HAL_GetInternalModuleWakeupFlag(LLWU_BASE, kLlwuWakeupModule0)) { CLOCK_SYS_EnableLptimerClock(0); LPTMR_HAL_ClearIntFlag(LPTMR0_BASE); /* write 1 to TCF to clear the LPT timer compare flag */ LPTMR_HAL_IsEnabled(LPTMR0_BASE); LPTMR_HAL_SetIntCmd(LPTMR0_BASE, 1); LPTMR_HAL_IsIntPending(LPTMR0_BASE); } if(LLWU_HAL_GetFilterDetectFlag(LLWU_BASE, 0)){ LLWU_HAL_ClearFilterDetectFlag(LLWU_BASE, 0); } if(LLWU_HAL_GetFilterDetectFlag(LLWU_BASE, 1)){ LLWU_HAL_ClearFilterDetectFlag(LLWU_BASE, 1); } }
/*! * @brief ISR Routine for Low Power Timer */ void demo_lptmr_isr(void) { volatile uint32_t lptmrCsrTemp; CLOCK_SYS_EnableLptimerClock(0); LPTMR_HAL_ClearIntFlag(LPTMR0_BASE); /* write 1 to TCF to clear the LPT timer compare flag */ LPTMR_HAL_Enable(LPTMR0_BASE); /* enable timer */ LPTMR_HAL_SetIntCmd(LPTMR0_BASE, true); /* enable interrupts */ LPTMR_HAL_ClearIntFlag(LPTMR0_BASE); /* clear the flag */ /*wait for write to complete to before returning */ while(!(LPTMR_HAL_IsEnabled(LPTMR0_BASE) && LPTMR_HAL_GetIntCmd(LPTMR0_BASE))); }
void lp_ticker_init(void) { if (lp_ticker_inited) { return; } lp_ticker_inited = 1; // RTC might be configured already, don't reset it RTC_HAL_SetSupervisorAccessCmd(RTC_BASE, true); if (!RTC_HAL_IsCounterEnabled(RTC_BASE)) { // select RTC for OSC32KSEL CLOCK_HAL_SetSource(SIM_BASE, kClockOsc32kSel, 2); // configure RTC SIM_HAL_EnableRtcClock(SIM_BASE, 0U); RTC_HAL_Init(RTC_BASE); RTC_HAL_Enable(RTC_BASE); for (volatile uint32_t wait_count = 0; wait_count < 1000000; wait_count++); RTC_HAL_SetAlarmIntCmd(RTC_BASE, false); RTC_HAL_SetSecsIntCmd(RTC_BASE, false); RTC_HAL_SetAlarmReg(RTC_BASE, 0); RTC_HAL_EnableCounter(RTC_BASE, true); } vIRQ_ClearPendingIRQ(RTC_IRQn); vIRQ_SetVector(RTC_IRQn, (uint32_t)rct_isr); vIRQ_EnableIRQ(RTC_IRQn); // configure LPTMR CLOCK_SYS_EnableLptimerClock(0); LPTMR0_CSR = 0x00; LPTMR0_PSR = 0x00; LPTMR0_CMR = 0x00; LPTMR_HAL_SetTimerModeMode(LPTMR0_BASE, kLptmrTimerModeTimeCounter); LPTMR0_PSR |= LPTMR_PSR_PCS(0x2) | LPTMR_PSR_PBYP_MASK; LPTMR_HAL_SetIntCmd(LPTMR0_BASE, 1); LPTMR_HAL_SetFreeRunningCmd(LPTMR0_BASE, 0); IRQn_Type timer_irq[] = LPTMR_IRQS; vIRQ_SetVector(timer_irq[0], (uint32_t)lptmr_isr); vIRQ_EnableIRQ(timer_irq[0]); }