/*FUNCTION********************************************************************** * * Function Name : CLOCK_SYS_GetCopFreq * Description : Gets the clock frequency for COP module. * This function gets the clock frequency for COP moudle. * *END**************************************************************************/ uint32_t CLOCK_SYS_GetCopFreq(void) { clock_cop_src_t src; uint32_t freq; src = CLOCK_HAL_GetCopSrc(SIM); switch (src) { case kClockCopSrcLpoClk: freq = CLOCK_SYS_GetLpoClockFreq(); break; case kClockCopSrcMcgIrClk: freq = CLOCK_HAL_GetInternalRefClk(MCG); break; case kClockCopSrcOsc0erClk: freq = CLOCK_SYS_GetOsc0ExternalRefClockFreq(); break; case kClockCopSrcBusClk: freq = CLOCK_SYS_GetBusClockFreq(); break; default: freq = 0U; break; } return freq; }
clock_manager_error_code_t CLOCK_SYS_GetFreq(clock_names_t clockName, uint32_t *frequency) { clock_manager_error_code_t returnCode = kClockManagerSuccess; switch (clockName) { case kCoreClock: case kSystemClock: *frequency = CLOCK_SYS_GetCoreClockFreq(); break; case kPlatformClock: *frequency = CLOCK_SYS_GetSystemClockFreq(); break; case kBusClock: *frequency = CLOCK_SYS_GetBusClockFreq(); break; case kFlexBusClock: *frequency = CLOCK_SYS_GetFlexbusFreq(); break; case kFlashClock: *frequency = CLOCK_SYS_GetFlashClockFreq(); break; case kOsc32kClock: *frequency = CLOCK_SYS_GetExternalRefClock32kFreq(); break; case kOsc0ErClock: *frequency = CLOCK_SYS_GetOsc0ExternalRefClockFreq(); break; case kRtcoutClock: *frequency = CLOCK_SYS_GetRtcOutFreq(); break; case kMcgFfClock: *frequency = CLOCK_SYS_GetFixedFreqClockFreq(); break; case kMcgFllClock: *frequency = CLOCK_HAL_GetFllClk(MCG_BASE); break; case kMcgPll0Clock: *frequency = CLOCK_HAL_GetPll0Clk(MCG_BASE); break; case kMcgOutClock: *frequency = CLOCK_HAL_GetOutClk(MCG_BASE); break; case kMcgIrClock: *frequency = CLOCK_HAL_GetInternalRefClk(MCG_BASE); break; case kLpoClock: *frequency = CLOCK_SYS_GetLpoClockFreq(); break; default: *frequency = 0U; returnCode = kClockManagerNoSuchClockName; break; } return returnCode; }
/*FUNCTION********************************************************************** * * Function Name : CLOCK_SYS_GetPortFilterFreq * Description : Gets PORTx digital input filter clock frequency. * This function gets the PORTx digital input filter clock frequency. * *END**************************************************************************/ uint32_t CLOCK_SYS_GetPortFilterFreq(uint32_t instance, clock_port_filter_src_t src) { if (kClockPortFilterSrcBusClk == src) { return CLOCK_SYS_GetBusClockFreq(); } else { return CLOCK_SYS_GetLpoClockFreq(); } }
/*FUNCTION********************************************************************** * * Function Name : CLOCK_SYS_GetWdogFreq * Description : Gets watch dog clock frequency. * This function gets the watch dog clock frequency. * *END**************************************************************************/ uint32_t CLOCK_SYS_GetWdogFreq(uint32_t instance, clock_wdog_src_t wdogSrc) { if (kClockWdogSrcLpoClk == wdogSrc) { return CLOCK_SYS_GetLpoClockFreq(); } else { return CLOCK_SYS_GetBusClockFreq(); } }
/*FUNCTION********************************************************************** * * Function Name : CLOCK_SYS_GetSpiFreq * Description : Gets the clock frequency for SPI. * *END**************************************************************************/ uint32_t CLOCK_SYS_GetSpiFreq(uint32_t instance) { assert(instance < SPI_INSTANCE_COUNT); if (0U == instance) { return CLOCK_SYS_GetBusClockFreq(); } else { return CLOCK_SYS_GetSystemClockFreq(); } }
/*FUNCTION********************************************************************** * * Function Name : QUADTMR_DRV_SetupFlexPwm * Description : Provides a PWM signal * The user provides the input clock source which is derived from the IP Bus clock. The user also * provides the desired PWM signal's period in microseconds and the pulse width in microseconds. * This function enables the pre-load function for each comapare register to allow updating * the PWM signal characteristics at a later time. * *END**************************************************************************/ void QUADTMR_DRV_SetupFlexPwm(uint32_t instance, quadtmr_ip_bus_clock_source_t clockSrc, uint32_t pwmPulsePeriod, uint32_t pulseWidthPeriod) { TMR_Type *tmrBase = g_quadtmrBase[instance]; uint16_t pulseCnt, highPulse, lowPulse; /* Update source clock frequency.*/ g_quadtmrIpSourceClock = CLOCK_SYS_GetBusClockFreq() / (1 << clockSrc); pulseCnt = ((uint64_t)g_quadtmrIpSourceClock * pwmPulsePeriod) / 1000000; highPulse = ((uint64_t)g_quadtmrIpSourceClock * pulseWidthPeriod) / 1000000; lowPulse = pulseCnt - highPulse; QUADTMR_HAL_SetupComparePreload(tmrBase, 2, highPulse, kQuadTmrLoadOnComp2); QUADTMR_HAL_SetupComparePreload(tmrBase, 1, lowPulse, kQuadTmrLoadOnComp1); QUADTMR_HAL_OutPwmSignal(tmrBase, (quadtmr_pri_count_source_t)(clockSrc + 8), highPulse, lowPulse); }
/*FUNCTION********************************************************************** * * Function Name : CLOCK_SYS_GetUartFreq * Description : Gets the clock frequency for UART module. * This function gets the clock frequency for UART module. * *END**************************************************************************/ uint32_t CLOCK_SYS_GetUartFreq(uint32_t instance) { uint32_t freq; switch (instance) { case 0: freq = CLOCK_SYS_GetSystemClockFreq(); break; case 1: freq = CLOCK_SYS_GetBusClockFreq(); break; default: freq = 0U; break; } return freq; }
/////////////////////////////////////////////////////////////////////////////// //Function to configure UART2 /////////////////////////////////////////////////////////////////////////////// void UART2_config(unsigned int BAUD_RATE) { long int uart_clock, BR; unsigned int SBR, OSR; unsigned char temp; //enable Port A and UART 0 clocks SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK; SIM_SCGC4 |= SIM_SCGC4_UART2_MASK; //configure UART 0 pins configure_uart_pins(1); //configure baud rate uart_clock = CLOCK_SYS_GetBusClockFreq(); SBR = uart_clock/(16 * BAUD_RATE); UART2_BDL = SBR & 0xFF; UART2_BDH |= ((SBR & 0xFF00)>>8); UART2_C1 = 0; UART2_C2 |= 0x0C; //enable transmitter and receiver UART2_C3 = 0; //Function to configure UART2 }
/*FUNCTION********************************************************************** * Function Name : POWER_SYS_CheckClocks * Description :Internal function used by POWER_SYS_SetMode function *END**************************************************************************/ static power_manager_error_code_t POWER_SYS_CheckClocks(power_manager_modes_t mode) { #if POWER_VLPR_MCG_LITE mcglite_mode_t mcgMode = CLOCK_HAL_GetMode(MCG); #else mcg_modes_t mcgMode = CLOCK_HAL_GetMcgMode(MCG); /* Check clock monitors */ switch(mode) { #if FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE case kPowerManagerHsrun: #endif case kPowerManagerRun: case kPowerManagerWait: /* Clock monitors can be enabled */ break; default: /* For other modes clock monitors should be disabled */ #if FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR if( CLOCK_HAL_IsOsc0MonitorEnabled(MCG) ) { return kPowerManagerErrorClock; } #endif #if FSL_FEATURE_MCG_HAS_RTC_32K if( CLOCK_HAL_IsRtcOscMonitorEnabled(MCG) ) { return kPowerManagerErrorClock; } #endif #if FSL_FEATURE_MCG_USE_PLLREFSEL if( CLOCK_HAL_IsOsc1MonitorEnabled(MCG) ) { return kPowerManagerErrorClock; } #endif break; } #endif /* We need check clocks if goes into VLPR or VLPW over VLPR */ if( (mode!=kPowerManagerVlpr) && (mode!=kPowerManagerVlpw) ) { return kPowerManagerSuccess; } #if POWER_VLPR_MCG_LITE switch(mcgMode) { case kMcgliteModeLirc8M: case kMcgliteModeLirc2M: case kMcgliteModeExt: /* allowed modes */ break; default: return kPowerManagerErrorClock; } if(CLOCK_SYS_GetFlashClockFreq() > POWER_VLPR_MAX_FLASH_BLPE_CLK) { return kPowerManagerErrorClock; } #else switch(mcgMode) { case kMcgModeBLPI: /* fast IRC must be selected */ if(CLOCK_HAL_GetInternalRefClkMode(MCG) != kMcgIrcFast) { return kPowerManagerErrorClock; } if(CLOCK_SYS_GetFlashClockFreq() > POWER_VLPR_MAX_FLASH_BLPI_CLK) { return kPowerManagerErrorClock; } break; case kMcgModeBLPE: if(CLOCK_SYS_GetFlashClockFreq() > POWER_VLPR_MAX_FLASH_BLPE_CLK) { return kPowerManagerErrorClock; } break; default: return kPowerManagerErrorClock; } #endif if(CLOCK_SYS_GetCoreClockFreq() > POWER_VLPR_MAX_CLK) { return kPowerManagerErrorClock; } if(CLOCK_SYS_GetBusClockFreq() > POWER_VLPR_MAX_CLK) { return kPowerManagerErrorClock; } if(CLOCK_SYS_GetSystemClockFreq() > POWER_VLPR_MAX_CLK) { return kPowerManagerErrorClock; } return kPowerManagerSuccess; }
/*FUNCTION********************************************************************** * * Function Name : SMARTCARD_DRV_InterfaceClockInit * Description : This function initializes clock module used for card clock generation * *END**************************************************************************/ static uint16_t SMARTCARD_DRV_InterfaceClockInit(uint8_t clockModuleInstance, uint8_t clockModuleChannel, uint32_t cardClk) { #if defined(EMVSIM_INSTANCE_COUNT) assert(clockModuleInstance < EMVSIM_INSTANCE_COUNT); EMVSIM_Type * base = g_emvsimBase[clockModuleInstance]; uint32_t emvsimClkMhz = 0; uint8_t emvsimPRSCValue; /* Retrieve EMV SIM clock */ emvsimClkMhz = CLOCK_SYS_GetEmvsimFreq(clockModuleInstance)/1000000; /* Calculate MOD value */ emvsimPRSCValue = (emvsimClkMhz*1000)/(cardClk/1000); /* Set clock prescaler */ EMVSIM_HAL_SetClockPrescaler(base, emvsimPRSCValue); /* Enable smart card clock */ EMVSIM_HAL_EnableCardClock(base); return cardClk; #elif defined(FTM_INSTANCE_COUNT) assert(clockModuleInstance < FTM_INSTANCE_COUNT); ftm_user_config_t ftmInfo; uint32_t periph_clk_mhz = 0; uint16_t ftmModValue; FTM_Type * ftmBase = g_ftmBase[clockModuleInstance]; uint32_t chnlPairnum = FTM_HAL_GetChnPairIndex(clockModuleChannel); /* Retrieve FTM system clock */ periph_clk_mhz = CLOCK_SYS_GetBusClockFreq()/1000000; /* Calculate MOD value */ ftmModValue = ((periph_clk_mhz*1000/2)/(cardClk/1000)) -1; /* Clear FTM driver user configuration */ memset(&ftmInfo, 0, sizeof(ftmInfo)); ftmInfo.BDMMode = kFtmBdmMode_11; ftmInfo.syncMethod = kFtmUseSoftwareTrig; /* Initialize FTM driver */ FTM_DRV_Init(clockModuleInstance, &ftmInfo); /* Reset FTM prescaler to 'Divide by 1', i.e., to be same clock as peripheral clock */ FTM_HAL_SetClockPs(ftmBase, kFtmDividedBy1); /* Disable FTM counter firstly */ FTM_HAL_SetClockSource(ftmBase, kClock_source_FTM_None); /* Set initial counter value */ FTM_HAL_SetCounterInitVal(ftmBase, 0); /* Set MOD value */ FTM_HAL_SetMod(ftmBase, ftmModValue); /* Other initializations to defaults */ FTM_HAL_SetCpwms(ftmBase, 0); FTM_HAL_SetDualChnCombineCmd(ftmBase, chnlPairnum, false); FTM_HAL_SetDualEdgeCaptureCmd(ftmBase, chnlPairnum, false); /* Configure mode to output compare, tougle output on match */ FTM_HAL_SetChnEdgeLevel(ftmBase, clockModuleChannel, kFtmToggleOnMatch); FTM_HAL_SetChnMSnBAMode(ftmBase, clockModuleChannel, 1); /* Configure a match value to toggle output at */ FTM_HAL_SetChnCountVal(ftmBase, clockModuleChannel, 1); /* Set clock source to start the counter */ FTM_HAL_SetClockSource(ftmBase, kClock_source_FTM_SystemClk); /* Re-calculate the actually configured smartcard clock and return to caller */ return (uint32_t)(((periph_clk_mhz*1000/2)/(FTM_HAL_GetMod(ftmBase)+1))*1000); #elif defined(TPM_INSTANCE_COUNT) assert(clockModuleInstance < TPM_INSTANCE_COUNT); assert(clockModuleChannel < FSL_FEATURE_TPM_CHANNEL_COUNTn(clockModuleInstance)); /* Initialize TPM driver parameter */ tpm_pwm_param_t param = { kTpmCenterAlignedPWM, /* mode */ kTpmHighTrue, /* edgeMode */ cardClk, /* uFrequencyHZ */ 50 /* uDutyCyclePercent */ }; /* Initialize TPM driver */ tpm_general_config_t driverInfo; memset(&driverInfo, 0, sizeof(driverInfo)); driverInfo.isDBGMode = true; TPM_DRV_Init(clockModuleInstance, &driverInfo); /* Set TPM clock source, the user will have to call the Clocking API's to set the * TPM module clock before calling this function */ TPM_DRV_SetClock(clockModuleInstance, kTpmClockSourceModuleClk, kTpmDividedBy1); /* Start TPM in PWM mode to generate smart card clock */ TPM_DRV_PwmStart(clockModuleInstance, ¶m, clockModuleChannel); return cardClk; #else return 0; #endif }