/* ===================================================================*/
LDD_TDeviceData* ACompLdd1_Init(LDD_TUserData *UserDataPtr)
{
ACompLdd1_TDeviceData *DeviceDataPtr; /* LDD device structure */
/* Allocate HAL device structure */
/* {FreeRTOS RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPtr = &DeviceDataPtr__DEFAULT_RTOS_ALLOC;
DeviceDataPtr->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
DeviceDataPtr->EventMask = 0x00U; /* Store mask of enabled event */
/* SIM_SCGC4: CMP=1 */
SIM_SCGC4 |= SIM_SCGC4_CMP_MASK;
/* PORTC_PCR2: ISF=0,MUX=0 */
PORTC_PCR2 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
/* CMP1_CR1: SE=0,WE=0,??=0,PMODE=0,INV=0,COS=0,OPE=0,EN=0 */
CMP1_CR1 = 0x00U; /* Disable comparator and sampling */
/* CMP1_MUXCR: ??=0,??=0,PSEL=2,MSEL=0 */
CMP1_MUXCR = (CMP_MUXCR_PSEL(0x02) | CMP_MUXCR_MSEL(0x00)); /* Initialize inputs */
/* CMP1_FPR: FILT_PER=0 */
CMP1_FPR = CMP_FPR_FILT_PER(0x00); /* Disable filter */
/* CMP1_CR0: ??=0,FILTER_CNT=0,??=0,??=0,HYSTCTR=0 */
CMP1_CR0 = (CMP_CR0_FILTER_CNT(0x00) | CMP_CR0_HYSTCTR(0x00)); /* Reset filter */
/* CMP1_FPR: FILT_PER=0 */
CMP1_FPR = CMP_FPR_FILT_PER(0x00); /* Set filter period */
/* CMP1_SCR: ??=0,DMAEN=0,??=0,IER=0,IEF=0,CFR=1,CFF=1,COUT=0 */
CMP1_SCR = (CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* Set SC register and clear flags */
/* CMP1_CR1: SE=0,WE=0,??=0,PMODE=0,INV=0,COS=0,OPE=0,EN=1 */
CMP1_CR1 = CMP_CR1_EN_MASK;
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_ACompLdd1_ID,DeviceDataPtr);
return ((LDD_TDeviceData*)DeviceDataPtr); /* Return pointer to the data data structure */
}
void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config)
{
assert(NULL != config);
uint8_t tmp8;
#if defined(FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT) && FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT
/* Choose the clock source for sampling. */
if (config->enableSample)
{
base->CR1 |= CMP_CR1_SE_MASK; /* Choose the external SAMPLE clock. */
}
else
{
base->CR1 &= ~CMP_CR1_SE_MASK; /* Choose the internal divided bus clock. */
}
#endif /* FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT */
/* Set the filter count. */
tmp8 = base->CR0 & ~CMP_CR0_FILTER_CNT_MASK;
tmp8 |= CMP_CR0_FILTER_CNT(config->filterCount);
base->CR0 = tmp8;
/* Set the filter period. It is used as the divider to bus clock. */
base->FPR = CMP_FPR_FILT_PER(config->filterPeriod);
}
