static void cn23xx_vf_setup_global_output_regs(struct octeon_device *oct) { u32 reg_val; u32 q_no; for (q_no = 0; q_no < (oct->sriov_info.rings_per_vf); q_no++) { octeon_write_csr(oct, CN23XX_VF_SLI_OQ_PKTS_CREDIT(q_no), 0xFFFFFFFF); reg_val = octeon_read_csr(oct, CN23XX_VF_SLI_OQ_PKTS_SENT(q_no)); reg_val &= 0xEFFFFFFFFFFFFFFFL; reg_val = octeon_read_csr(oct, CN23XX_VF_SLI_OQ_PKT_CONTROL(q_no)); /* clear IPTR */ reg_val &= ~CN23XX_PKT_OUTPUT_CTL_IPTR; /* set DPTR */ reg_val |= CN23XX_PKT_OUTPUT_CTL_DPTR; /* reset BMODE */ reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_BMODE); /* No Relaxed Ordering, No Snoop, 64-bit Byte swap * for Output Queue ScatterList reset ROR_P, NSR_P */ reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR_P); reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR_P); #ifdef __LITTLE_ENDIAN_BITFIELD reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ES_P); #else reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES_P); #endif /* No Relaxed Ordering, No Snoop, 64-bit Byte swap * for Output Queue Data reset ROR, NSR */ reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR); reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR); /* set the ES bit */ reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES); /* write all the selected settings */ octeon_write_csr(oct, CN23XX_VF_SLI_OQ_PKT_CONTROL(q_no), reg_val); } }
static int cn23xx_enable_vf_io_queues(struct octeon_device *oct) { u32 q_no; for (q_no = 0; q_no < oct->num_iqs; q_no++) { u64 reg_val; /* set the corresponding IQ IS_64B bit */ if (oct->io_qmask.iq64B & BIT_ULL(q_no)) { reg_val = octeon_read_csr64( oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no)); reg_val |= CN23XX_PKT_INPUT_CTL_IS_64B; octeon_write_csr64( oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no), reg_val); } /* set the corresponding IQ ENB bit */ if (oct->io_qmask.iq & BIT_ULL(q_no)) { reg_val = octeon_read_csr64( oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no)); reg_val |= CN23XX_PKT_INPUT_CTL_RING_ENB; octeon_write_csr64( oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no), reg_val); } } for (q_no = 0; q_no < oct->num_oqs; q_no++) { u32 reg_val; /* set the corresponding OQ ENB bit */ if (oct->io_qmask.oq & BIT_ULL(q_no)) { reg_val = octeon_read_csr( oct, CN23XX_VF_SLI_OQ_PKT_CONTROL(q_no)); reg_val |= CN23XX_PKT_OUTPUT_CTL_RING_ENB; octeon_write_csr( oct, CN23XX_VF_SLI_OQ_PKT_CONTROL(q_no), reg_val); } } return 0; }