static void __init cns3xxx_init(void)
{
struct device_node *dn;
cns3xxx_l2x0_init();
dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-ahci");
if (of_device_is_available(dn)) {
u32 tmp;
tmp = __raw_readl(MISC_SATA_POWER_MODE);
tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */
tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */
__raw_writel(tmp, MISC_SATA_POWER_MODE);
/* Enable SATA PHY */
cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0);
cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1);
/* Enable SATA Clock */
cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA);
/* De-Asscer SATA Reset */
cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA));
}
dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-sdhci");
if (of_device_is_available(dn)) {
u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014);
u32 gpioa_pins = __raw_readl(gpioa);
/* MMC/SD pins share with GPIOA */
gpioa_pins |= 0x1fff0004;
__raw_writel(gpioa_pins, gpioa);
cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));
cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO));
}
pm_power_off = cns3xxx_power_off;
of_platform_populate(NULL, of_default_bus_match_table,
cns3xxx_auxdata, NULL);
}
static void __init cns3xxx_spi_initial(void)
{
u32 __iomem *gpiob = (void __iomem *) (CNS3XXX_MISC_BASE_VIRT + 0x0018);
u32 gpiob_pins = __raw_readl(gpiob);
/* MMC/SD pins share with GPIOA */
gpiob_pins |= 0xf80;
__raw_writel(gpiob_pins, gpiob);
/* share pin config. */
//PM_PLL_HM_PD_CTRL_REG &= ~(0x1 << 5);
//HAL_MISC_ENABLE_SPI_PINS();
cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SPI_PCM_I2C));
cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SPI_PCM_I2C));
SPI_CONFIGURATION_REG = (((0x0 & 0x3) << 0) | /* 8bits shift length */
(0x0 << 9) | /* SPI mode */
(0x0 << 10) | /* disable FIFO */
(0x1 << 11) | /* SPI master mode */
(0x0 << 12) | /* disable SPI loopback mode */
(0x1 << 13) | /* clock phase */
(0x1 << 14) | /* clock polarity */
(0x0 << 24) | /* disable - SPI data swap */
(0x1 << 29) | /* enable - 2IO Read mode */
(0x0 << 30) | /* disable - SPI high speed read for system boot up */
(0x0 << 31)); /* disable - SPI */
/* Set SPI bit rate PCLK/2 */
SPI_BIT_RATE_CONTROL_REG = 0x1;
/* Set SPI Tx channel 0 */
SPI_TRANSMIT_CONTROL_REG = 0x0;
/* Set Tx FIFO Threshold, Tx FIFO has 2 words */
SPI_FIFO_TRANSMIT_CONFIG_REG &= ~(0x03 << 4);
SPI_FIFO_TRANSMIT_CONFIG_REG |= ((0x0 & 0x03) << 4);
/* Set Rx FIFO Threshold, Rx FIFO has 2 words */
SPI_FIFO_RECEIVE_CONFIG_REG &= ~(0x03 << 4);
SPI_FIFO_RECEIVE_CONFIG_REG |= ((0x0 & 0x03) << 4);
/* Disable all interrupt */
SPI_INTERRUPT_ENABLE_REG = 0x0;
/* Clear spurious interrupt sources */
SPI_INTERRUPT_STATUS_REG = (0x0F << 4);
/* Enable SPI */
SPI_CONFIGURATION_REG |= (0x1 << 31);
return;
}
static void __init ts43xx_map_io(void)
{
cns3xxx_map_io();
#ifdef CONFIG_SERIAL_8250_CONSOLE
HAL_MISC_ENABLE_UART1_PINS();
cns3xxx_pwr_power_up(CNS3XXX_PWR_PLL(PLL_USB));
cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(UART1));
early_serial_setup(&cns3xxx_serial_ports[0]);
#if (1 < CONFIG_SERIAL_8250_NR_UARTS)
HAL_MISC_ENABLE_UART1_PINS();
cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(UART1));
cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(UART1));
early_serial_setup(&cns3xxx_serial_ports[1]);
#endif
#if (2 < CONFIG_SERIAL_8250_NR_UARTS)
HAL_MISC_ENABLE_UART2_PINS();
cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(UART2));
cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(UART2));
early_serial_setup(&cns3xxx_serial_ports[2]);
#endif
#endif
}
static void __init ts43xx_ahci_init(void)
{
u32 tmp;
tmp = MISC_SATA_POWER_MODE;
//tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */
tmp &= ~(0x1 << 16); /* Force SATA PHY 0 into SLUMBER Mode */
tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */
MISC_SATA_POWER_MODE = tmp;
/* Enable SATA PHY */
// ts43xx only uses port 1
//cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0);
cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1);
/* Enable SATA Clock */
cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA);
/* De-Asscer SATA Reset */
cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA));
}
static void __init cns3xxx_init(void)
{
int i;
#ifdef CONFIG_CACHE_L2X0
/* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled
* Bits: .... ...0 0111 1001 0000 .... .... .... */
cns3xxx_l2x0_init();
#endif
#ifdef CONFIG_CACHE_L2CC
l2cc_init((void __iomem *) CNS3XXX_L2C_BASE_VIRT);
#endif
#ifdef CONFIG_CNS3XXX_DMAC
dmac_init();
#endif
#ifdef CONFIG_CNS3XXX_RAID
cns_rdma_init();
#endif
show_board_version();
{
volatile unsigned long *pciecfg0;
pciecfg0 = (volatile unsigned long *)CNS3XXX_PCIE0_CFG0_BASE_VIRT;
pciecfg0[1] |= 7;
printk("usec at kernel start: 0x%08lX\n", *(volatile unsigned long *)(CNS3XXX_PCIE0_MEM_BASE_VIRT+0x14));
}
ts43xx_ahci_init();
for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
struct amba_device *d = amba_devs[i];
int ret;
cns3xxx_pwr_power_up(CNS3XXX_PWR_PLL(PLL_LCD));
cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(LCDC));
cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(LCDC));
ret = amba_device_register(d, &iomem_resource);
if(ret)
printk("%s=>%d: %d\n", __FUNCTION__, __LINE__, ret);
}
platform_add_devices(cns3xxx_devs, ARRAY_SIZE(cns3xxx_devs));
lm_device_register(&cns3xxx_usb_otg_device);
i2c_register_board_info(0, cns3xxx_i2c_devices, ARRAY_SIZE(cns3xxx_i2c_devices));
i2c_register_board_info(1, cns3xxx_i2c_gpio_devices, ARRAY_SIZE(cns3xxx_i2c_gpio_devices));
spi_register_board_info(cns3xxx_spi_devices, ARRAY_SIZE(cns3xxx_spi_devices));
cns3xxx_proc_dir = proc_mkdir("cns3xxx", NULL);
#ifdef CONFIG_DEBUG_FS
cns3xxx_debugfs_dir = debugfs_create_dir("cns3xxx", NULL);
#endif
#ifdef CONFIG_CACHE_L2CC
l2cc_proc_init();
#endif
pm_power_off = cns3xxx_power_off;
}
