* Clock-Architecture Diagram 5
*/
FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0,
RK1108_CLKSEL_CON(5), 8, 1, MFLAGS, 0, 7, DFLAGS,
RK1108_CLKGATE_CON(2), 0, GFLAGS),
COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
RK1108_CLKSEL_CON(8), 0,
RK1108_CLKGATE_CON(2), 1, GFLAGS,
&rk1108_i2s0_fracmux),
GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
RK1108_CLKGATE_CON(2), 2, GFLAGS),
COMPOSITE_NODIV(0, "i2s_out", mux_i2s_out_p, 0,
RK1108_CLKSEL_CON(5), 15, 1, MFLAGS,
RK1108_CLKGATE_CON(2), 3, GFLAGS),
COMPOSITE(0, "i2s1_src", mux_pll_src_2plls_p, 0,
RK1108_CLKSEL_CON(6), 8, 1, MFLAGS, 0, 7, DFLAGS,
RK1108_CLKGATE_CON(2), 4, GFLAGS),
COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(9), 0,
RK2928_CLKGATE_CON(2), 5, GFLAGS,
&rk1108_i2s1_fracmux),
GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
RK1108_CLKGATE_CON(2), 6, GFLAGS),
COMPOSITE(0, "i2s2_src", mux_pll_src_2plls_p, 0,
RK1108_CLKSEL_CON(7), 8, 1, MFLAGS, 0, 7, DFLAGS,
RK1108_CLKGATE_CON(3), 8, GFLAGS),
COMPOSITE_NOMUX(0, "crypto", "aclk_cpu_pre", 0, RK3288_CLKSEL_CON(26), 6, 2, DFLAGS, RK3288_CLKGATE_CON(5), 4, GFLAGS), GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(0), 7, GFLAGS), COMPOSITE(0, "i2s_src", mux_pll_src_cpll_gpll_p, 0, RK3288_CLKSEL_CON(4), 15, 1, MFLAGS, 0, 7, DFLAGS, RK3288_CLKGATE_CON(4), 1, GFLAGS), COMPOSITE_FRAC(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(8), 0, RK3288_CLKGATE_CON(4), 2, GFLAGS), MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(4), 8, 2, MFLAGS), COMPOSITE_NODIV(SCLK_I2S0_OUT, "i2s0_clkout", mux_i2s_clkout_p, 0, RK3288_CLKSEL_CON(4), 12, 1, MFLAGS, RK3288_CLKGATE_CON(4), 0, GFLAGS), GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", CLK_SET_RATE_PARENT, RK3288_CLKGATE_CON(4), 3, GFLAGS), MUX(0, "spdif_src", mux_pll_src_cpll_gpll_p, 0, RK3288_CLKSEL_CON(5), 15, 1, MFLAGS), COMPOSITE_NOMUX(0, "spdif_pre", "spdif_src", 0, RK3288_CLKSEL_CON(5), 0, 7, DFLAGS, RK3288_CLKGATE_CON(4), 4, GFLAGS), COMPOSITE_FRAC(0, "spdif_frac", "spdif_src", 0, RK3288_CLKSEL_CON(9), 0, RK3288_CLKGATE_CON(4), 5, GFLAGS), COMPOSITE_NODIV(SCLK_SPDIF, "sclk_spdif", mux_spdif_p, 0, RK3288_CLKSEL_CON(5), 8, 2, MFLAGS, RK3288_CLKGATE_CON(4), 6, GFLAGS),
* stclk_mcu is listed as child of fclk_mcu_src in diagram 5, * but stclk_mcu has an additional own divider in diagram 2 */ COMPOSITE_NOMUX(0, "stclk_mcu", "fclk_mcu_src", 0, RK3368_CLKSEL_CON(12), 8, 3, DFLAGS, RK3368_CLKGATE_CON(13), 13, GFLAGS), COMPOSITE(0, "i2s_8ch_src", mux_pll_src_cpll_gpll_p, 0, RK3368_CLKSEL_CON(27), 12, 1, MFLAGS, 0, 7, DFLAGS, RK3368_CLKGATE_CON(6), 1, GFLAGS), COMPOSITE_FRACMUX(0, "i2s_8ch_frac", "i2s_8ch_src", CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(28), 0, RK3368_CLKGATE_CON(6), 2, GFLAGS, &rk3368_i2s_8ch_fracmux), COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "i2s_8ch_clkout", mux_i2s_8ch_clkout_p, 0, RK3368_CLKSEL_CON(27), 15, 1, MFLAGS, RK3368_CLKGATE_CON(6), 0, GFLAGS), GATE(SCLK_I2S_8CH, "sclk_i2s_8ch", "i2s_8ch_pre", CLK_SET_RATE_PARENT, RK3368_CLKGATE_CON(6), 3, GFLAGS), COMPOSITE(0, "spdif_8ch_src", mux_pll_src_cpll_gpll_p, 0, RK3368_CLKSEL_CON(31), 12, 1, MFLAGS, 0, 7, DFLAGS, RK3368_CLKGATE_CON(6), 4, GFLAGS), COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_src", CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(32), 0, RK3368_CLKGATE_CON(6), 5, GFLAGS, &rk3368_spdif_8ch_fracmux), GATE(SCLK_SPDIF_8CH, "sclk_spdif_8ch", "spdif_8ch_pre", CLK_SET_RATE_PARENT, RK3368_CLKGATE_CON(6), 6, GFLAGS), COMPOSITE(0, "i2s_2ch_src", mux_pll_src_cpll_gpll_p, 0, RK3368_CLKSEL_CON(53), 12, 1, MFLAGS, 0, 7, DFLAGS, RK3368_CLKGATE_CON(5), 13, GFLAGS),
RK2928_CLKGATE_CON(3), 2, GFLAGS), COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0, RK2928_CLKSEL_CON(34), 7, 1, MFLAGS, 0, 5, DFLAGS, RK2928_CLKGATE_CON(3), 15, GFLAGS), GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_src", 0, RK2928_CLKGATE_CON(9), 7, GFLAGS), GATE(SCLK_TIMER2, "timer2", "xin24m", 0, RK2928_CLKGATE_CON(3), 4, GFLAGS), GATE(SCLK_TIMER3, "timer3", "xin24m", 0, RK2928_CLKGATE_CON(1), 2, GFLAGS), GATE(SCLK_TIMER4, "timer4", "xin24m", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS), GATE(SCLK_TIMER5, "timer5", "xin24m", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS), GATE(SCLK_TIMER6, "timer6", "xin24m", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS), COMPOSITE_NODIV(0, "sclk_hsicphy_480m", mux_hsicphy_p, 0, RK2928_CLKSEL_CON(30), 0, 2, DFLAGS, RK2928_CLKGATE_CON(3), 6, GFLAGS), DIV(0, "sclk_hsicphy_12m", "sclk_hsicphy_480m", 0, RK2928_CLKGATE_CON(11), 8, 6, DFLAGS), MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0, RK2928_CLKSEL_CON(2), 15, 1, MFLAGS), COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0, RK2928_CLKSEL_CON(3), 0, 7, DFLAGS, RK2928_CLKGATE_CON(0), 9, GFLAGS), COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_pre", 0, RK2928_CLKSEL_CON(7), 0, RK2928_CLKGATE_CON(0), 10, GFLAGS), MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0, RK2928_CLKSEL_CON(3), 8, 2, MFLAGS), COMPOSITE_NOMUX(0, "spdif_pre", "i2s_src", 0,
RK3328_CLKGATE_CON(1), 2, GFLAGS, &rk3328_i2s0_fracmux), GATE(SCLK_I2S0, "clk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT, RK3328_CLKGATE_CON(1), 3, GFLAGS), COMPOSITE(0, "clk_i2s1_div", mux_2plls_p, 0, RK3328_CLKSEL_CON(8), 15, 1, MFLAGS, 0, 7, DFLAGS, RK3328_CLKGATE_CON(1), 4, GFLAGS), COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT, RK3328_CLKSEL_CON(9), 0, RK3328_CLKGATE_CON(1), 5, GFLAGS, &rk3328_i2s1_fracmux), GATE(SCLK_I2S1, "clk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT, RK3328_CLKGATE_CON(0), 6, GFLAGS), COMPOSITE_NODIV(SCLK_I2S1_OUT, "i2s1_out", mux_i2s1out_p, 0, RK3328_CLKSEL_CON(8), 12, 1, MFLAGS, RK3328_CLKGATE_CON(1), 7, GFLAGS), COMPOSITE(0, "clk_i2s2_div", mux_2plls_p, 0, RK3328_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 7, DFLAGS, RK3328_CLKGATE_CON(1), 8, GFLAGS), COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT, RK3328_CLKSEL_CON(11), 0, RK3328_CLKGATE_CON(1), 9, GFLAGS, &rk3328_i2s2_fracmux), GATE(SCLK_I2S2, "clk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT, RK3328_CLKGATE_CON(1), 10, GFLAGS), COMPOSITE_NODIV(SCLK_I2S2_OUT, "i2s2_out", mux_i2s2out_p, 0, RK3328_CLKSEL_CON(10), 12, 1, MFLAGS, RK3328_CLKGATE_CON(1), 11, GFLAGS),
RK2928_CLKSEL_CON(22), 15, 1, MFLAGS, 8, 5, DFLAGS, RK2928_CLKGATE_CON(2), 6, GFLAGS), GATE(0, "sclk_hsadc", "ext_hsadc", 0, RK2928_CLKGATE_CON(10), 12, GFLAGS), COMPOSITE(0, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0, RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS, RK2928_CLKGATE_CON(2), 15, GFLAGS), COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0, RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 8, DFLAGS, RK2928_CLKGATE_CON(2), 11, GFLAGS), COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0, RK2928_CLKSEL_CON(11), 10, 2, MFLAGS, RK2928_CLKGATE_CON(2), 13, GFLAGS), DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0, RK2928_CLKSEL_CON(12), 0, 8, DFLAGS), COMPOSITE_NODIV(0, "sclk_emmc_src", mux_mmc_src_p, 0, RK2928_CLKSEL_CON(11), 12, 2, MFLAGS, RK2928_CLKGATE_CON(2), 14, GFLAGS), DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0, RK2928_CLKSEL_CON(12), 8, 8, DFLAGS), /* * Clock-Architecture Diagram 2 */ GATE(0, "gpll_vop", "gpll", 0,
RK2928_CLKSEL_CON(10), 14, 2, MFLAGS, 0, 5, DFLAGS, RK2928_CLKGATE_CON(2), 0, GFLAGS), GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0, RK2928_CLKGATE_CON(2), 1, GFLAGS), DIV(0, "pclk_peri_src", "aclk_peri_src", CLK_IGNORE_UNUSED, RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO), GATE(PCLK_PERI, "pclk_peri", "pclk_peri_src", 0, RK2928_CLKGATE_CON(2), 3, GFLAGS), DIV(0, "hclk_peri_src", "aclk_peri_src", CLK_IGNORE_UNUSED, RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO), GATE(HCLK_PERI, "hclk_peri", "hclk_peri_src", 0, RK2928_CLKGATE_CON(2), 2, GFLAGS), COMPOSITE_NODIV(SCLK_TIMER0, "sclk_timer0", mux_timer_p, CLK_IGNORE_UNUSED, RK2928_CLKSEL_CON(2), 4, 1, MFLAGS, RK2928_CLKGATE_CON(1), 0, GFLAGS), COMPOSITE_NODIV(SCLK_TIMER1, "sclk_timer1", mux_timer_p, CLK_IGNORE_UNUSED, RK2928_CLKSEL_CON(2), 5, 1, MFLAGS, RK2928_CLKGATE_CON(1), 1, GFLAGS), COMPOSITE_NODIV(SCLK_TIMER2, "sclk_timer2", mux_timer_p, CLK_IGNORE_UNUSED, RK2928_CLKSEL_CON(2), 6, 1, MFLAGS, RK2928_CLKGATE_CON(2), 4, GFLAGS), COMPOSITE_NODIV(SCLK_TIMER3, "sclk_timer3", mux_timer_p, CLK_IGNORE_UNUSED, RK2928_CLKSEL_CON(2), 7, 1, MFLAGS, RK2928_CLKGATE_CON(2), 5, GFLAGS), MUX(0, "uart_pll_clk", mux_pll_src_apll_dpll_gpll_usb480m_p, 0, RK2928_CLKSEL_CON(13), 10, 2, MFLAGS), COMPOSITE_NOMUX(0, "uart0_src", "uart_pll_clk", 0, RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
RV1108_CLKSEL_CON(12), 7, 1, MFLAGS, 0, 7, DFLAGS, RV1108_CLKGATE_CON(8), 15, GFLAGS), COMPOSITE(SCLK_I2C0_PMU, "sclk_i2c0_pmu", mux_pll_src_2plls_p, 0, RV1108_CLKSEL_CON(19), 7, 1, MFLAGS, 0, 7, DFLAGS, RV1108_CLKGATE_CON(8), 14, GFLAGS), GATE(0, "pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(8), 13, GFLAGS), /* * Clock-Architecture Diagram 3 */ COMPOSITE(SCLK_WIFI, "sclk_wifi", mux_wifi_src_p, 0, RV1108_CLKSEL_CON(28), 15, 1, MFLAGS, 8, 6, DFLAGS, RV1108_CLKGATE_CON(9), 8, GFLAGS), COMPOSITE_NODIV(0, "sclk_cifout_src", mux_cifout_src_p, 0, RV1108_CLKSEL_CON(40), 8, 1, MFLAGS, RV1108_CLKGATE_CON(9), 11, GFLAGS), COMPOSITE_NOGATE(SCLK_CIFOUT, "sclk_cifout", mux_cifout_p, 0, RV1108_CLKSEL_CON(40), 12, 1, MFLAGS, 0, 5, DFLAGS), COMPOSITE_NOMUX(SCLK_MIPI_CSI_OUT, "sclk_mipi_csi_out", "xin24m", 0, RV1108_CLKSEL_CON(41), 0, 5, DFLAGS, RV1108_CLKGATE_CON(9), 12, GFLAGS), GATE(0, "pclk_acodecphy", "pclk_top_pre", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(14), 6, GFLAGS), GATE(0, "pclk_usbgrf", "pclk_top_pre", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(14), 14, GFLAGS), GATE(ACLK_CIF0, "aclk_cif0", "aclk_vio1_pre", 0, RV1108_CLKGATE_CON(18), 10, GFLAGS), GATE(HCLK_CIF0, "hclk_cif0", "hclk_vio_pre", 0,
