static void print_fpga_info(void) { struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0); u16 versions = in_le16(&fpga->versions); u16 fpga_version = in_le16(&fpga->fpga_version); u16 fpga_features = in_le16(&fpga->fpga_features); unsigned unit_type; unsigned hardware_version; unsigned feature_channels; unsigned feature_expansion; unit_type = (versions & 0xf000) >> 12; hardware_version = versions & 0x000f; feature_channels = fpga_features & 0x007f; feature_expansion = fpga_features & (1<<15); puts("FPGA: "); switch (unit_type) { case UNITTYPE_CCD_SWITCH: printf("CCD-Switch"); break; default: printf("UnitType %d(not supported)", unit_type); break; } switch (hardware_version) { case HWVER_100: printf(" HW-Ver 1.00\n"); break; case HWVER_110: printf(" HW-Ver 1.10\n"); break; case HWVER_121: printf(" HW-Ver 1.21\n"); break; case HWVER_122: printf(" HW-Ver 1.22\n"); break; default: printf(" HW-Ver %d(not supported)\n", hardware_version); break; } printf(" FPGA V %d.%02d, features:", fpga_version / 100, fpga_version % 100); printf(" %d channel(s)", feature_channels); printf(", expansion %ssupported\n", feature_expansion ? "" : "un"); }
static void print_fpga_info(void) { struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0); u16 versions = in_le16(&fpga->versions); u16 fpga_version = in_le16(&fpga->fpga_version); u16 fpga_features = in_le16(&fpga->fpga_features); int fpga_state = get_fpga_state(0); unsigned unit_type; unsigned hardware_version; unsigned feature_channels; puts("FPGA: "); if (fpga_state & FPGA_STATE_DONE_FAILED) { printf(" done timed out\n"); return; } if (fpga_state & FPGA_STATE_REFLECTION_FAILED) { printf(" refelectione test failed\n"); return; } unit_type = (versions & 0xf000) >> 12; hardware_version = versions & 0x000f; feature_channels = fpga_features & 0x007f; switch (unit_type) { case UNITTYPE_CCX16: printf("CCX-Switch"); break; default: printf("UnitType %d(not supported)", unit_type); break; } switch (hardware_version) { case HWVER_300: printf(" HW-Ver 3.00-3.12\n"); break; default: printf(" HW-Ver %d(not supported)\n", hardware_version); break; } printf(" FPGA V %d.%02d, features:", fpga_version / 100, fpga_version % 100); printf(" %d channel(s)\n", feature_channels); }
/* * setup Gbit PHYs */ int last_stage_init(void) { ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0); unsigned int k; miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME, bb_miiphy_read, bb_miiphy_write); for (k = 0; k < 32; ++k) configure_gbit_phy(k); /* take fpga serdes blocks out of reset */ out_le16(&fpga->quad_serdes_reset, 0); return 0; }
int board_early_init_r(void) { unsigned k; unsigned ctr; for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) gd->arch.fpga_state[k] = 0; /* * reset FPGA */ gd405ex_init(); gd405ex_set_fpga_reset(1); gd405ex_setup_hw(); for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { ctr = 0; while (!gd405ex_get_fpga_done(k)) { udelay(100000); if (ctr++ > 5) { gd->arch.fpga_state[k] |= FPGA_STATE_DONE_FAILED; break; } } } udelay(10); gd405ex_set_fpga_reset(0); for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(k); #ifdef CONFIG_SYS_FPGA_NO_RFL_HI u16 *reflection_target = &fpga->reflection_low; #else u16 *reflection_target = &fpga->reflection_high; #endif /* * wait for fpga out of reset */ ctr = 0; while (1) { out_le16(&fpga->reflection_low, REFLECTION_TESTPATTERN); if (in_le16(reflection_target) == REFLECTION_TESTPATTERN_INV) break; udelay(100000); if (ctr++ > 5) { gd->arch.fpga_state[k] |= FPGA_STATE_REFLECTION_FAILED; break; } } } return 0; }
/* * Check Board Identity: */ int checkboard(void) { ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0); char *s = getenv("serial#"); u16 versions = in_le16(&fpga->versions); u16 fpga_version = in_le16(&fpga->fpga_version); u16 fpga_features = in_le16(&fpga->fpga_features); unsigned unit_type; unsigned hardware_version; unsigned feature_channels; unsigned feature_expansion; unit_type = (versions & 0xf000) >> 12; hardware_version = versions & 0x000f; feature_channels = fpga_features & 0x007f; feature_expansion = fpga_features & (1<<15); printf("Board: "); printf("CATCenter Io"); if (s != NULL) { puts(", serial# "); puts(s); } puts("\n "); switch (unit_type) { case UNITTYPE_CCD_SWITCH: printf("CCD-Switch"); break; default: printf("UnitType %d(not supported)", unit_type); break; } switch (hardware_version) { case HWVER_100: printf(" HW-Ver 1.00\n"); break; case HWVER_110: printf(" HW-Ver 1.10\n"); break; case HWVER_121: printf(" HW-Ver 1.21\n"); break; case HWVER_122: printf(" HW-Ver 1.22\n"); break; default: printf(" HW-Ver %d(not supported)\n", hardware_version); break; } printf(" FPGA V %d.%02d, features:", fpga_version / 100, fpga_version % 100); printf(" %d channel(s)", feature_channels); printf(", expansion %ssupported\n", feature_expansion ? "" : "un"); return 0; }
static void print_fpga_info(void) { struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0); u16 versions = in_le16(&fpga->versions); u16 fpga_version = in_le16(&fpga->fpga_version); u16 fpga_features = in_le16(&fpga->fpga_features); unsigned unit_type; unsigned hardware_version; unsigned feature_compression; unsigned feature_osd; unsigned feature_audio; unsigned feature_sysclock; unsigned feature_ramconfig; unsigned feature_carriers; unsigned feature_video_channels; unit_type = (versions & 0xf000) >> 12; hardware_version = versions & 0x000f; feature_compression = (fpga_features & 0xe000) >> 13; feature_osd = fpga_features & (1<<11); feature_audio = (fpga_features & 0x0600) >> 9; feature_sysclock = (fpga_features & 0x0180) >> 7; feature_ramconfig = (fpga_features & 0x0060) >> 5; feature_carriers = (fpga_features & 0x000c) >> 2; feature_video_channels = fpga_features & 0x0003; switch (unit_type) { case UNITTYPE_MAIN_USER: printf("Mainchannel"); break; case UNITTYPE_VIDEO_USER: printf("Videochannel"); break; default: printf("UnitType %d(not supported)", unit_type); break; } switch (hardware_version) { case HWVER_100: printf(" HW-Ver 1.00\n"); break; case HWVER_104: printf(" HW-Ver 1.04\n"); break; case HWVER_110: printf(" HW-Ver 1.10\n"); break; default: printf(" HW-Ver %d(not supported)\n", hardware_version); break; } printf(" FPGA V %d.%02d, features:", fpga_version / 100, fpga_version % 100); switch (feature_compression) { case COMPRESSION_NONE: printf(" no compression"); break; case COMPRESSION_TYPE1_DELTA: printf(" type1-deltacompression"); break; default: printf(" compression %d(not supported)", feature_compression); break; } printf(", %sosd", feature_osd ? "" : "no "); switch (feature_audio) { case AUDIO_NONE: printf(", no audio"); break; case AUDIO_TX: printf(", audio tx"); break; case AUDIO_RX: printf(", audio rx"); break; case AUDIO_RXTX: printf(", audio rx+tx"); break; default: printf(", audio %d(not supported)", feature_audio); break; } puts(",\n "); switch (feature_sysclock) { case SYSCLK_147456: printf("clock 147.456 MHz"); break; default: printf("clock %d(not supported)", feature_sysclock); break; } switch (feature_ramconfig) { case RAM_DDR2_32: printf(", RAM 32 bit DDR2"); break; default: printf(", RAM %d(not supported)", feature_ramconfig); break; } printf(", %d carrier(s)", feature_carriers); printf(", %d video channel(s)\n", feature_video_channels); }
int last_stage_init(void) { unsigned int k; unsigned int fpga; struct ihs_fpga *fpga0 = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0); struct ihs_fpga *fpga1 = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(1); int failed = 0; char str_phys[] = "Setup PHYs -"; char str_serdes[] = "Start SERDES blocks"; char str_channels[] = "Start FPGA channels"; char str_locks[] = "Verify SERDES locks"; char str_hicb[] = "Verify HICB status"; char str_status[] = "Verify PHY status -"; char slash[] = "\\|/-\\|/-"; print_fpga_info(0); print_fpga_info(1); /* setup Gbit PHYs */ puts("TRANS: "); puts(str_phys); miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME, bb_miiphy_read, bb_miiphy_write); for (k = 0; k < 32; ++k) { configure_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k); putc('\b'); putc(slash[k % 8]); } miiphy_register(CONFIG_SYS_GBIT_MII1_BUSNAME, bb_miiphy_read, bb_miiphy_write); for (k = 0; k < 32; ++k) { configure_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k); putc('\b'); putc(slash[k % 8]); } blank_string(strlen(str_phys)); /* take fpga serdes blocks out of reset */ puts(str_serdes); udelay(500000); out_le16(&fpga0->quad_serdes_reset, 0); out_le16(&fpga1->quad_serdes_reset, 0); blank_string(strlen(str_serdes)); /* take channels out of reset */ puts(str_channels); udelay(500000); for (fpga = 0; fpga < 2; ++fpga) { u16 *ch0_config_int = &(fpga ? fpga1 : fpga0)->ch0_config_int; for (k = 0; k < 32; ++k) out_le16(ch0_config_int + 4 * k, 0); } blank_string(strlen(str_channels)); /* verify channels serdes lock */ puts(str_locks); udelay(500000); for (fpga = 0; fpga < 2; ++fpga) { u16 *ch0_status_int = &(fpga ? fpga1 : fpga0)->ch0_status_int; for (k = 0; k < 32; ++k) { u16 status = in_le16(ch0_status_int + 4*k); if (!(status & (1 << 4))) { failed = 1; printf("fpga %d channel %d: no serdes lock\n", fpga, k); } /* reset events */ out_le16(ch0_status_int + 4*k, status); } } blank_string(strlen(str_locks)); /* verify hicb_status */ puts(str_hicb); for (fpga = 0; fpga < 2; ++fpga) { u16 *ch0_hicb_status_int = &(fpga ? fpga1 : fpga0)->ch0_hicb_status_int; for (k = 0; k < 32; ++k) { u16 status = in_le16(ch0_hicb_status_int + 4*k); if (status) printf("fpga %d hicb %d: hicb status %04x\n", fpga, k, status); /* reset events */ out_le16(ch0_hicb_status_int + 4*k, status); } } blank_string(strlen(str_hicb)); /* verify phy status */ puts(str_status); for (k = 0; k < 32; ++k) { if (verify_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k)) { printf("verify baseboard phy %d failed\n", k); failed = 1; } putc('\b'); putc(slash[k % 8]); } for (k = 0; k < 32; ++k) { if (verify_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k)) { printf("verify extensionboard phy %d failed\n", k); failed = 1; } putc('\b'); putc(slash[k % 8]); } blank_string(strlen(str_status)); printf("Starting 64 channels %s\n", failed ? "failed" : "ok"); return 0; }
static void print_fpga_info(unsigned dev) { struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(dev); u16 versions = in_le16(&fpga->versions); u16 fpga_version = in_le16(&fpga->fpga_version); u16 fpga_features = in_le16(&fpga->fpga_features); int fpga_state = get_fpga_state(dev); unsigned unit_type; unsigned hardware_version; unsigned feature_channels; unsigned feature_expansion; printf("FPGA%d: ", dev); if (fpga_state & FPGA_STATE_PLATFORM) printf("(legacy) "); if (fpga_state & FPGA_STATE_DONE_FAILED) { printf(" done timed out\n"); return; } if (fpga_state & FPGA_STATE_REFLECTION_FAILED) { printf(" refelectione test failed\n"); return; } unit_type = (versions & 0xf000) >> 12; hardware_version = versions & 0x000f; feature_channels = fpga_features & 0x007f; feature_expansion = fpga_features & (1<<15); switch (unit_type) { case UNITTYPE_CCD_SWITCH: printf("CCD-Switch"); break; default: printf("UnitType %d(not supported)", unit_type); break; } switch (hardware_version) { case HWVER_100: printf(" HW-Ver 1.00\n"); break; case HWVER_110: printf(" HW-Ver 1.10\n"); break; default: printf(" HW-Ver %d(not supported)\n", hardware_version); break; } printf(" FPGA V %d.%02d, features:", fpga_version / 100, fpga_version % 100); printf(" %d channel(s)", feature_channels); printf(", expansion %ssupported\n", feature_expansion ? "" : "un"); }