unsigned int pin_mux_spi1_cs1(unsigned int PinNr) { switch(PinNr) { case Spi1_CS1_PinMux_E16: HWREG(SOC_CONTROL_REGS + CONTROL_CONF_UART_TXD(0)) = (CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_PUTYPESEL | CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_RXACTIVE | CONTROL_CONF_MUXMODE(1)); break; case Spi1_CS1_PinMux_D17: HWREG(SOC_CONTROL_REGS + CONTROL_CONF_UART_RTSN(1)) = (CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_PUTYPESEL | CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_RXACTIVE | CONTROL_CONF_MUXMODE(4)); break; case Spi1_CS1_PinMux_C18: HWREG(SOC_CONTROL_REGS + CONTROL_CONF_ECAP0_IN_PWM0_OUT) = (CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_PUTYPESEL | CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_RXACTIVE | CONTROL_CONF_MUXMODE(2)); break; case Spi1_CS1_PinMux_A15: HWREG(SOC_CONTROL_REGS + CONTROL_CONF_XDMA_EVENT_INTR(0)) = (CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_PUTYPESEL | CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_RXACTIVE | CONTROL_CONF_MUXMODE(3)); break; default: return 0; } return 0; }
unsigned int GPIO0Pin19PinMuxSetup(void) { unsigned int profile = 7; unsigned int status = FALSE; profile = EVMProfileGet(); switch(profile) { /* Fall through for cases 0, 1, 2, 4, 5 and 6. */ case 0: case 1: case 2: case 3: case 4: case 5: case 6: default: break; case 7: HWREG(SOC_CONTROL_REGS + CONTROL_CONF_XDMA_EVENT_INTR(0)) = CONTROL_CONF_MUXMODE(7); status = TRUE; break; } return status; }
/** * \brief This function selects the McASP instance 1 pins * * \param None * * \return TRUE/FALSE. * * \note This muxing depends on the profile in which the EVM is configured. */ void McASP1PinMuxSetup(void) { HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_COL) = CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_RXACTIVE | MCASP_SEL_MODE; HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_CRS) = CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_RXACTIVE | MCASP_SEL_MODE; HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXERR) = CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_RXACTIVE | MCASP_SEL_MODE; HWREG(SOC_CONTROL_REGS + CONTROL_CONF_RMII1_REFCLK) = CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_RXACTIVE | MCASP_SEL_MODE; HWREG(SOC_CONTROL_REGS + CONTROL_CONF_XDMA_EVENT_INTR(0)) = CLKOUT1_SEL_MODE; }