mad_status MADIMPENTRY( RegistersTarget )( mad_registers *mr ) { #if !defined( __BIG_ENDIAN__ ) int i; // Convert GPRs for( i = 0; i < 32; i++ ) { PPC_SWAP_REG_64( *(&mr->ppc.r0 + i) ); } // Convert FPRs for( i = 0; i < 32; i++ ) { PPC_SWAP_REG_64( (*(&mr->ppc.f0 + i)).u64 ); } // Convert special registers PPC_SWAP_REG_64( mr->ppc.iar ); PPC_SWAP_REG_64( mr->ppc.msr ); PPC_SWAP_REG_64( mr->ppc.ctr ); PPC_SWAP_REG_64( mr->ppc.lr ); CONV_BE_32( mr->ppc.xer ); CONV_BE_32( mr->ppc.cr ); CONV_BE_32( mr->ppc.fpscr ); #endif return( MS_OK ); }
mad_status MADIMPENTRY( RegistersHost )( mad_registers *mr ) { #if !defined( __BIG_ENDIAN__ ) int i; // Currently harcoded for big endian targets - should be dynamic // And we really ought to have a 64-bit byte swap routine... // Convert GPRs for( i = 0; i < 32; i++ ) { PPC_SWAP_REG_64( *(&mr->ppc.r0 + i) ); } // Convert FPRs for( i = 0; i < 32; i++ ) { PPC_SWAP_REG_64( (*(&mr->ppc.f0 + i)).u64 ); } // Convert special registers PPC_SWAP_REG_64( mr->ppc.iar ); PPC_SWAP_REG_64( mr->ppc.msr ); PPC_SWAP_REG_64( mr->ppc.ctr ); PPC_SWAP_REG_64( mr->ppc.lr ); CONV_BE_32( mr->ppc.xer ); CONV_BE_32( mr->ppc.cr ); CONV_BE_32( mr->ppc.fpscr ); #endif return( MS_OK ); }
static void fix_rel_byte_order( elf_file_handle elf_file_hnd, Elf32_Rel *e_rel ) { // note that one of the branches will always get compiled out, // depending on host endianness if( elf_file_hnd->flags & ORL_FILE_FLAG_BIG_ENDIAN ) { CONV_BE_32( e_rel->r_offset ); CONV_BE_32( e_rel->r_info ); } else { CONV_LE_32( e_rel->r_offset ); CONV_LE_32( e_rel->r_info ); } }
static void fix_sym_byte_order( elf_file_handle elf_file_hnd, Elf32_Sym *e_sym ) { // note that one of the branches will always get compiled out, // depending on host endianness if( elf_file_hnd->flags & ORL_FILE_FLAG_BIG_ENDIAN ) { CONV_BE_32( e_sym->st_name ); CONV_BE_32( e_sym->st_value ); CONV_BE_32( e_sym->st_size ); CONV_BE_16( e_sym->st_shndx ); } else { CONV_LE_32( e_sym->st_name ); CONV_LE_32( e_sym->st_value ); CONV_LE_32( e_sym->st_size ); CONV_LE_16( e_sym->st_shndx ); } }
static int GetAnOffset( addr_off in, addr_off *off ) { address a; int rc; memset( &a, 0, sizeof( a ) ); a.mach.offset = in; rc = MCReadMem( a, sizeof( *off ), off ) == sizeof( *off ); if( rc ) { CONV_BE_32( *off ); // NYI: dynamic endian switching } return( rc ); }
void WriteBigEndian32( unsigned_32 num ) { CONV_BE_32( num ); WriteNew( &num, sizeof( num ) ); }
mad_status DIGENTRY MIRegistersTarget( mad_registers *mr ) { #if !defined( __BIG_ENDIAN__ ) unsigned_32 temp; int i; // Convert GPRs for( i = 0; i < 32; i++ ) { CONV_BE_32( TRANS_GPREG_LO( mr->ppc, i ) ); CONV_BE_32( TRANS_GPREG_HI( mr->ppc, i ) ); temp = TRANS_GPREG_LO( mr->ppc, i ); TRANS_GPREG_LO( mr->ppc, i ) = TRANS_GPREG_HI( mr->ppc, i ); TRANS_GPREG_HI( mr->ppc, i ) = temp; } // Convert FPRs for( i = 0; i < 32; i++ ) { CONV_BE_32( TRANS_FPREG_LO( mr->ppc, i ) ); CONV_BE_32( TRANS_FPREG_HI( mr->ppc, i ) ); temp = TRANS_FPREG_LO( mr->ppc, i ); TRANS_FPREG_LO( mr->ppc, i ) = TRANS_FPREG_HI( mr->ppc, i ); TRANS_FPREG_HI( mr->ppc, i ) = temp; } // Convert special registers CONV_BE_32( mr->ppc.iar.u._32[I64LO32] ); CONV_BE_32( mr->ppc.iar.u._32[I64HI32] ); temp = mr->ppc.iar.u._32[I64LO32]; mr->ppc.iar.u._32[I64LO32] = mr->ppc.iar.u._32[I64HI32]; mr->ppc.iar.u._32[I64HI32] = temp; CONV_BE_32( mr->ppc.msr.u._32[I64LO32] ); CONV_BE_32( mr->ppc.msr.u._32[I64HI32] ); temp = mr->ppc.msr.u._32[I64LO32]; mr->ppc.msr.u._32[I64LO32] = mr->ppc.msr.u._32[I64HI32]; mr->ppc.msr.u._32[I64HI32] = temp; CONV_BE_32( mr->ppc.ctr.u._32[I64LO32] ); CONV_BE_32( mr->ppc.ctr.u._32[I64HI32] ); temp = mr->ppc.ctr.u._32[I64LO32]; mr->ppc.ctr.u._32[I64LO32] = mr->ppc.ctr.u._32[I64HI32]; mr->ppc.ctr.u._32[I64HI32] = temp; CONV_BE_32( mr->ppc.lr.u._32[I64LO32] ); CONV_BE_32( mr->ppc.lr.u._32[I64HI32] ); temp = mr->ppc.lr.u._32[I64LO32]; mr->ppc.lr.u._32[I64LO32] = mr->ppc.lr.u._32[I64HI32]; mr->ppc.lr.u._32[I64HI32] = temp; CONV_BE_32( mr->ppc.xer ); CONV_BE_32( mr->ppc.cr ); CONV_BE_32( mr->ppc.fpscr ); #endif return( MS_OK ); }
mad_status DIGENTRY MIRegistersHost( mad_registers *mr ) { #if !defined( __BIG_ENDIAN__ ) unsigned_32 temp; int i; // Currently harcoded for big endian targets - should be dynamic // And we really ought to have a 64-bit byte swap routine... // Convert GPRs for( i = 0; i < 32; i++ ) { CONV_BE_32( TRANS_GPREG_LO( mr->ppc, i ) ); CONV_BE_32( TRANS_GPREG_HI( mr->ppc, i ) ); temp = TRANS_GPREG_LO( mr->ppc, i ); TRANS_GPREG_LO( mr->ppc, i ) = TRANS_GPREG_HI( mr->ppc, i ); TRANS_GPREG_HI( mr->ppc, i ) = temp; } // Convert FPRs for( i = 0; i < 32; i++ ) { CONV_BE_32( TRANS_FPREG_LO( mr->ppc, i ) ); CONV_BE_32( TRANS_FPREG_HI( mr->ppc, i ) ); temp = TRANS_FPREG_LO( mr->ppc, i ); TRANS_FPREG_LO( mr->ppc, i ) = TRANS_FPREG_HI( mr->ppc, i ); TRANS_FPREG_HI( mr->ppc, i ) = temp; } // Convert special registers CONV_BE_32( mr->ppc.iar.u._32[I64LO32] ); CONV_BE_32( mr->ppc.iar.u._32[I64HI32] ); temp = mr->ppc.iar.u._32[I64LO32]; mr->ppc.iar.u._32[I64LO32] = mr->ppc.iar.u._32[I64HI32]; mr->ppc.iar.u._32[I64HI32] = temp; CONV_BE_32( mr->ppc.msr.u._32[I64LO32] ); CONV_BE_32( mr->ppc.msr.u._32[I64HI32] ); temp = mr->ppc.msr.u._32[I64LO32]; mr->ppc.msr.u._32[I64LO32] = mr->ppc.msr.u._32[I64HI32]; mr->ppc.msr.u._32[I64HI32] = temp; CONV_BE_32( mr->ppc.ctr.u._32[I64LO32] ); CONV_BE_32( mr->ppc.ctr.u._32[I64HI32] ); temp = mr->ppc.ctr.u._32[I64LO32]; mr->ppc.ctr.u._32[I64LO32] = mr->ppc.ctr.u._32[I64HI32]; mr->ppc.ctr.u._32[I64HI32] = temp; CONV_BE_32( mr->ppc.lr.u._32[I64LO32] ); CONV_BE_32( mr->ppc.lr.u._32[I64HI32] ); temp = mr->ppc.lr.u._32[I64LO32]; mr->ppc.lr.u._32[I64LO32] = mr->ppc.lr.u._32[I64HI32]; mr->ppc.lr.u._32[I64HI32] = temp; CONV_BE_32( mr->ppc.xer ); CONV_BE_32( mr->ppc.cr ); CONV_BE_32( mr->ppc.fpscr ); #endif return( MS_OK ); }