// sdio CORE_SDIO_INIT(__TARGET_CHIP__), CORE_SDIO_FINI(__TARGET_CHIP__), CORE_SDIO_CONFIG(__TARGET_CHIP__), CORE_SDIO_START(__TARGET_CHIP__), CORE_SDIO_STOP(__TARGET_CHIP__), CORE_SDIO_SEND_CMD(__TARGET_CHIP__), CORE_SDIO_SEND_CMD_ISREADY(__TARGET_CHIP__), CORE_SDIO_GET_RESP(__TARGET_CHIP__), CORE_SDIO_DATA_TX(__TARGET_CHIP__), CORE_SDIO_DATA_TX_ISREADY(__TARGET_CHIP__), CORE_SDIO_DATA_RX(__TARGET_CHIP__), CORE_SDIO_DATA_RX_ISREADY(__TARGET_CHIP__), } #endif ,{ // tickclk CORE_TICKCLK_INIT(__TARGET_CHIP__), CORE_TICKCLK_FINI(__TARGET_CHIP__), CORE_TICKCLK_START(__TARGET_CHIP__), CORE_TICKCLK_STOP(__TARGET_CHIP__), CORE_TICKCLK_GET_COUNT(__TARGET_CHIP__), } ,{ // delay CORE_DELAY_INIT(__TARGET_CHIP__), CORE_DELAY_DELAYMS(__TARGET_CHIP__), CORE_DELAY_DELAYUS(__TARGET_CHIP__) } ,peripheral_commit };
.ebi.config = CORE_EBI_CONFIG(__TARGET_CHIP__), .ebi.config_sram = CORE_EBI_CONFIG_SRAM(__TARGET_CHIP__), .ebi.config_psram = CORE_EBI_CONFIG_PSRAM(__TARGET_CHIP__), .ebi.config_nor = CORE_EBI_CONFIG_NOR(__TARGET_CHIP__), .ebi.config_nand = CORE_EBI_CONFIG_NAND(__TARGET_CHIP__), .ebi.config_sdram = CORE_EBI_CONFIG_SDRAM(__TARGET_CHIP__), .ebi.config_ddram = CORE_EBI_CONFIG_DDRAM(__TARGET_CHIP__), .ebi.config_pccard = CORE_EBI_CONFIG_PCCARD(__TARGET_CHIP__), .ebi.get_base_addr = CORE_EBI_GET_BASE_ADDR(__TARGET_CHIP__), #endif #if IFS_SDIO_EN .sdio.init = CORE_SDIO_INIT(__TARGET_CHIP__), .sdio.fini = CORE_SDIO_FINI(__TARGET_CHIP__), #endif #if IFS_HCD_EN .hcd.init = CORE_HCD_INIT(__TARGET_CHIP__), .hcd.fini = CORE_HCD_FINI(__TARGET_CHIP__), .hcd.regbase = CORE_HCD_REGBASE(__TARGET_CHIP__), #endif .tickclk.init = CORE_TICKCLK_INIT(__TARGET_CHIP__), .tickclk.fini = CORE_TICKCLK_FINI(__TARGET_CHIP__), .tickclk.start = CORE_TICKCLK_START(__TARGET_CHIP__), .tickclk.stop = CORE_TICKCLK_STOP(__TARGET_CHIP__), .tickclk.get_count = CORE_TICKCLK_GET_COUNT(__TARGET_CHIP__), .tickclk.config_cb = CORE_TICKCLK_CONFIG_CB(__TARGET_CHIP__), }; const struct interfaces_info_t *interfaces = &core_interfaces;