//*****************************************************************************
//
// The main code for the application. It sets up the peripherals, displays the
// splash screens, and then manages the interaction between the game and the
// screen saver.
//
//*****************************************************************************
int
main(void)
{
tRectangle sRect;
#ifndef _TMS320C6X
unsigned int index;
#endif
SetupIntc();
/* Configuring UART2 instance for serial communication. */
UARTStdioInit();
#ifdef _TMS320C6X
CacheEnableMAR((unsigned int)0xC0000000, (unsigned int)0x20000000);
CacheEnable(L1PCFG_L1PMODE_32K | L1DCFG_L1DMODE_32K | L2CFG_L2MODE_256K);
#else
/* Sets up 'Level 1" page table entries.
* The page table entry consists of the base address of the page
* and the attributes for the page. The following operation is to
* setup one-to-one mapping page table for DDR memeory range and set
* the atributes for the same. The DDR memory range is from 0xC0000000
* to 0xDFFFFFFF. Thus the base of the page table ranges from 0xC00 to
* 0xDFF. Cache(C bit) and Write Buffer(B bit) are enabled only for
* those page table entries which maps to DDR RAM and internal RAM.
* All the pages in the DDR range are provided with R/W permissions
*/
for(index = 0; index < (4*1024); index++)
{
if((index >= 0xC00 && index < 0xE00)|| (index == 0x800))
{
pageTable[index] = (index << 20) | 0x00000C1E;
}
else
{
pageTable[index] = (index << 20) | 0x00000C12;
}
}
/* Configures translation table base register
* with pagetable base address.
*/
CP15TtbSet((unsigned int )pageTable);
/* Enables MMU */
CP15MMUEnable();
/* Enable Instruction Cache */
CP15ICacheEnable();
/* Enable Data Cache */
CP15DCacheEnable();
#endif
SetUpLCD();
ConfigureFrameBuffer();
GrOffScreen16BPPInit(&g_sSHARP480x272x16Display0, (unsigned char *)g_pucBuffer0, LCD_WIDTH, LCD_HEIGHT);
GrOffScreen16BPPInit(&g_sSHARP480x272x16Display1, (unsigned char *)g_pucBuffer1, LCD_WIDTH, LCD_HEIGHT);
// Initialize a drawing context.
GrContextInit(&sContext0, &g_sSHARP480x272x16Display0);
GrContextInit(&sContext1, &g_sSHARP480x272x16Display1);
/* enable End of frame interrupt */
RasterEndOfFrameIntEnable(SOC_LCDC_0_REGS);
/* enable raster */
RasterEnable(SOC_LCDC_0_REGS);
PeripheralsSetup();
I2C0IntRegister(4);
AIC31Init();
ToneLoopInit();
/* Start playing the tone */
ToneLoopStart();
// TS init
TouchInit();
GrContextForegroundSet(&sContext0, ClrBlack);
GrContextForegroundSet(&sContext1, ClrBlack);
sRect.sXMin = GAME_X - 1;
sRect.sYMin = GAME_Y - 1;
sRect.sXMax = GAME_X + GAME_W;
sRect.sYMax = GAME_Y + GAME_H;
GrRectFill(&sContext0, &sRect);
GrRectFill(&sContext1, &sRect);
GrImageDraw(&sContext0, g_pucTILogo128x96, GAME_X, GAME_Y);
GrImageDraw(&sContext1, g_pucTILogo128x96, GAME_X, GAME_Y);
Delay(0x5FFFFF);
// Confiure and start timer2
Timer2Config();
Timer2Start();
// Loop forever.
while(1)
{
// Display the main screen.
if(MainScreen())
{
// The button was pressed, so start the game.
PlayGame();
}
else
{
// The button was not pressed during the timeout period, so start
// the screen saver.
ScreenSaver();
}
}
}
/******************************************************************************
** INTERNAL FUNCTION DEFINITIONS
*******************************************************************************/
int main(void)
{
#ifndef _TMS320C6X
unsigned int index;
#endif
/* Setting the Master priority for the VPIF and LCD DMA controllers to highest level */
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_MSTPRI1) &= 0x00FFFFFF;
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_MSTPRI2) &= 0x0FFFFFFF;
#ifdef _TMS320C6X
/* Set MAR bits and configure L1 cache */
CacheEnableMAR((unsigned int)0xC0000000, (unsigned int)0x10000000);
CacheEnable(L1PCFG_L1PMODE_32K | L1DCFG_L1DMODE_32K );
#else
/* Sets up 'Level 1" page table entries.
* The page table entry consists of the base address of the page
* and the attributes for the page. The following operation is to
* setup one-to-one mapping page table for DDR memeory range and set
* the atributes for the same. The DDR memory range is from 0xC0000000
* to 0xCFFFFFFF. Thus the base of the page table ranges from 0xC00 to
* 0xCFF. Cache(C bit) and Write Buffer(B bit) are enabled only for
* those page table entries which maps to DDR RAM and internal RAM.
* All the pages in the DDR range are provided with R/W permissions */
for(index = 0; index < (4*1024); index++)
{
if((index >= 0xC00 && index < 0xD00)|| (index == 0x800))
{
pageTable[index] = (index << 20) | 0x00000C1E;
}
else
{
pageTable[index] = (index << 20) | 0x00000C12;
}
}
/* Configures translation table base register
* with pagetable base address. */
CP15TtbSet((unsigned int )pageTable);
/* Enables MMU */
CP15MMUEnable();
/* Enable Instruction Cache */
CP15ICacheEnable();
/* Enable Data Cache */
CP15DCacheEnable();
#endif
/* Allocate pointers to buffers */
buff_luma[0] = buff_luma1;
buff_luma[1] = buff_luma2;
buff_chroma[0] = buff_chroma1;
buff_chroma[1] = buff_chroma2;
/* Initializing palette for first buffer */
Rgb_buffer1[0] = 0x4000;
for (i = 1; i < 16; i++)
Rgb_buffer1[i] = 0x0000;
videoTopRgb1 = Rgb_buffer1 + i;
/* Initializing palette for second buffer */
Rgb_buffer2[0] = 0x4000;
for (i = 1; i < 16; i++)
Rgb_buffer2[i] = 0x0000;
videoTopRgb2 = Rgb_buffer2 + i;
/* Power on VPIF */
PSCModuleControl(SOC_PSC_1_REGS, HW_PSC_VPIF, PSC_POWERDOMAIN_ALWAYS_ON,
PSC_MDCTL_NEXT_ENABLE);
/* Initializing ARM/DSP INTC */
SetupIntc();
/* Initialize I2C and program UI GPIO expander, TVP5147, and ADV7343 via I2C */
I2CPinMuxSetup(0);
/* enable video via gpio expander to ensure we have exclusive access to the bus */
I2CCodecIfInit(SOC_I2C_0_REGS, INT_CHANNEL_I2C, I2C_SLAVE_UI_EXPANDER);
I2CGPIOInit(SOC_I2C_0_REGS);
I2CGPIOSetOutput(SOC_I2C_0_REGS);
/*Initialize the TVP5147 to accept composite video */
I2CCodecIfInit(SOC_I2C_0_REGS, INT_CHANNEL_I2C,
I2C_SLAVE_CODEC_TVP5147_2_COMPOSITE);
TVP5147CompositeInit(SOC_I2C_0_REGS);
/* Setup VPIF pinmux */
VPIFPinMuxSetup();
/* Setup LCD */
SetUpLCD();
/* Initialize VPIF */
SetUpVPIFRx();
VPIFDMARequestSizeConfig(SOC_VPIF_0_REGS, VPIF_REQSIZE_ONE_TWENTY_EIGHT);
VPIFEmulationControlSet(SOC_VPIF_0_REGS, VPIF_HALT);
/* Initialize buffer addresses for 1st frame*/
VPIFCaptureFBConfig(SOC_VPIF_0_REGS, VPIF_CHANNEL_0, VPIF_TOP_FIELD,
VPIF_LUMA, (unsigned int) buff_luma[0], CAPTURE_IMAGE_WIDTH*2);
VPIFCaptureFBConfig(SOC_VPIF_0_REGS, VPIF_CHANNEL_0, VPIF_TOP_FIELD,
VPIF_CHROMA, (unsigned int) buff_chroma[0], CAPTURE_IMAGE_WIDTH*2);
VPIFCaptureFBConfig(SOC_VPIF_0_REGS, VPIF_CHANNEL_0, VPIF_BOTTOM_FIELD,
VPIF_LUMA, (unsigned int) (buff_luma[0] + CAPTURE_IMAGE_WIDTH), CAPTURE_IMAGE_WIDTH*2);
VPIFCaptureFBConfig(SOC_VPIF_0_REGS, VPIF_CHANNEL_0, VPIF_BOTTOM_FIELD,
VPIF_CHROMA, (unsigned int) (buff_chroma[0] + CAPTURE_IMAGE_WIDTH), CAPTURE_IMAGE_WIDTH*2);
/* configuring the base ceiling */
RasterDMAFBConfig(SOC_LCDC_0_REGS, (unsigned int) Rgb_buffer2,
(unsigned int) (Rgb_buffer2 + DISPLAY_IMAGE_WIDTH * DISPLAY_IMAGE_HEIGHT + 15), 0);
RasterDMAFBConfig(SOC_LCDC_0_REGS, (unsigned int) Rgb_buffer2,
(unsigned int) (Rgb_buffer2 + DISPLAY_IMAGE_WIDTH * DISPLAY_IMAGE_HEIGHT + 15), 1);
/* Enable capture */
VPIFCaptureChanenEnable(SOC_VPIF_0_REGS, VPIF_CHANNEL_0);
/* Enable VPIF interrupt */
VPIFInterruptEnable(SOC_VPIF_0_REGS, VPIF_FRAMEINT_CH0);
VPIFInterruptEnableSet(SOC_VPIF_0_REGS, VPIF_FRAMEINT_CH0);
/* enable End of frame interrupt */
RasterEndOfFrameIntEnable(SOC_LCDC_0_REGS);
/* enable raster */
RasterEnable(SOC_LCDC_0_REGS);
buffcount++;
buffcount2 = buffcount - 1;
/* Run forever */
while (1)
{
/* Wait here till a new frame is not captured */
while (!captured);
/* Process the next buffer only when both the raster buffers
* are pointing to the current buffer to avoid jitter effect */
if (updated == 3)
{
processed = 0;
changed = 0;
updated = 0;
/* Convert the buffer from CBCR422 semi-planar to RGB565,
* Flush and invalidate the processed buffer so that the DMA reads the processed data,
* set the flag for the buffer to be displayed on the LCD (which would be the processed buffer)
* and notify the LCD of availability of a processed buffer.
* The output buffers are ping-ponged each time. */
if (pingpong)
{
cbcr422sp_to_rgb565_c(
(const unsigned char *) (videoTopC + OFFSET),
DISPLAY_IMAGE_HEIGHT, CAPTURE_IMAGE_WIDTH, ccCoeff,
(const unsigned char *) (videoTopY + OFFSET),
CAPTURE_IMAGE_WIDTH, videoTopRgb1, DISPLAY_IMAGE_WIDTH, DISPLAY_IMAGE_WIDTH);
#ifdef _TMS320C6X
CacheWBInv((unsigned int) videoTopRgb1, DISPLAY_IMAGE_WIDTH * DISPLAY_IMAGE_HEIGHT * 2);
#else
CP15DCacheCleanBuff((unsigned int) videoTopRgb1,DISPLAY_IMAGE_WIDTH * DISPLAY_IMAGE_HEIGHT * 2);
#endif
display_buff_1 = 1;
changed = 1;
}
else
{
cbcr422sp_to_rgb565_c(
(const unsigned char *) (videoTopC + OFFSET),
DISPLAY_IMAGE_HEIGHT, CAPTURE_IMAGE_WIDTH, ccCoeff,
(const unsigned char *) (videoTopY + OFFSET),
CAPTURE_IMAGE_WIDTH, videoTopRgb2, DISPLAY_IMAGE_WIDTH, DISPLAY_IMAGE_WIDTH);
#ifdef _TMS320C6X
CacheWBInv((unsigned int) videoTopRgb2, DISPLAY_IMAGE_WIDTH * DISPLAY_IMAGE_HEIGHT * 2);
#else
CP15DCacheCleanBuff((unsigned int) videoTopRgb2, DISPLAY_IMAGE_WIDTH * DISPLAY_IMAGE_HEIGHT * 2);
#endif
display_buff_1 = 0;
changed = 1;
}
pingpong = !pingpong;
captured = 0;
processed = 1;
}
}
}
//*****************************************************************************
//
// This is the main loop that runs the application.
//
//*****************************************************************************
static int
main(void)
{
// tRectangle sRect;
unsigned int index, i;
unsigned char *src, *dest;
/* Sets up 'Level 1" page table entries.
* The page table entry consists of the base address of the page
* and the attributes for the page. The following operation is to
* setup one-to-one mapping page table for DDR memeory range and set
* the atributes for the same. The DDR memory range is from 0xC0000000
* to 0xDFFFFFFF. Thus the base of the page table ranges from 0xC00 to
* 0xDFF. Cache(C bit) and Write Buffer(B bit) are enabled only for
* those page table entries which maps to DDR RAM and internal RAM.
* All the pages in the DDR range are provided with R/W permissions
*/
#ifdef DMA_MODE
for(index = 0; index < (4*1024); index++)
{
if((index >= 0xC00 && index < 0xE00)|| (index == 0x800))
{
pageTable[index] = (index << 20) | 0x00000C1E;
}
else
{
pageTable[index] = (index << 20) | 0x00000C12;
}
}
/* Configures translation table base register
* with pagetable base address.
*/
CP15TtbSet((unsigned int )pageTable);
/* Enables MMU */
CP15MMUEnable();
/* Enable Data Cache */
CP15DCacheEnable();
/* Disable Instruction Cache*/
CP15ICacheDisable();
#endif
#if 0 // No LCD -- ertl-liyixiao
//
//configures arm interrupt controller to generate raster interrupt
//
SetupIntc();
//
//Configures raster to display image
//
SetUpLCD();
/* configuring the base ceiling */
RasterDMAFBConfig(SOC_LCDC_0_REGS,
(unsigned int)(g_pucBuffer+PALETTE_OFFSET),
(unsigned int)(g_pucBuffer+PALETTE_OFFSET) + sizeof(g_pucBuffer) - 2 - PALETTE_OFFSET,
0);
RasterDMAFBConfig(SOC_LCDC_0_REGS,
(unsigned int)(g_pucBuffer+PALETTE_OFFSET),
(unsigned int)(g_pucBuffer+PALETTE_OFFSET) + sizeof(g_pucBuffer) - 2 - PALETTE_OFFSET,
1);
// Copy palette info into buffer
src = (unsigned char *) palette_32b;
dest = (unsigned char *) (g_pucBuffer+PALETTE_OFFSET);
for( i = 4; i < (PALETTE_SIZE+4); i++)
{
*dest++ = *src++;
}
GrOffScreen16BPPInit(&g_sSHARP480x272x16Display, g_pucBuffer, LCD_WIDTH, LCD_HEIGHT);
// Initialize a drawing context.
GrContextInit(&g_sContext, &g_sSHARP480x272x16Display);
/* enable End of frame interrupt */
RasterEndOfFrameIntEnable(SOC_LCDC_0_REGS);
/* enable raster */
RasterEnable(SOC_LCDC_0_REGS);
ConfigRasterDisplayEnable();
//
// Fill the top 15 rows of the screen with blue to create the banner.
//
sRect.sXMin = 0;
sRect.sYMin = 0;
sRect.sXMax = GrContextDpyWidthGet(&g_sContext) - 1;
sRect.sYMax = DISPLAY_BANNER_HEIGHT;
GrContextForegroundSet(&g_sContext, ClrDarkBlue);
GrRectFill(&g_sContext, &sRect);
//
// Put a white box around the banner.
//
GrContextForegroundSet(&g_sContext, ClrWhite);
GrRectDraw(&g_sContext, &sRect);
//
// Put the application name in the middle of the banner.
//
GrContextFontSet(&g_sContext, &g_sFontCm20);
GrStringDrawCentered(&g_sContext, "usb-dev-msc", -1,
GrContextDpyWidthGet(&g_sContext) / 2, 10, 0);
//
// Initialize the idle timeout and reset all flags.
//
g_ulIdleTimeout = 0;
g_ulFlags = 0;
//
// Initialize the state to idle.
//
g_eMSCState = MSC_DEV_IDLE;
//
// Draw the status bar and set it to idle.
//
UpdateStatus("Idle", 1);
#endif
//SetupAINTCInt();
//ConfigureAINTCIntUSB();
//DelayTimerSetup();
#if 0 // No LCD
SystickConfigure(SysTickHandler);
SystickPeriodSet(10);
SystickEnable();
#endif
USBDMSCInit(0, (tUSBDMSCDevice *)&g_sMSCDevice);
#ifdef DMA_MODE
Cppi41DmaInit(USB_INSTANCE, epInfo, NUMBER_OF_ENDPOINTS);
for(;g_bufferIndex < NUM_OF_RX_BDs; g_bufferIndex++)
{
dataBuffer = (unsigned char *)cppiDmaAllocBuffer();
doDmaRxTransfer(USB_INSTANCE, USB_MSC_BUFER_SIZE, dataBuffer,
g_sMSCDevice.psPrivateData->ucOUTEndpoint);
}
#endif
#if 0 // No LCD -- ertl-liyixiao
//
// Drop into the main loop.
//
//
// Drop into the main loop.
//
while(1)
{
switch(g_eMSCState)
{
case MSC_DEV_READ:
{
//
// Update the screen if necessary.
//
if(g_ulFlags & FLAG_UPDATE_STATUS)
{
UpdateStatus("Reading", 0);
g_ulFlags &= ~FLAG_UPDATE_STATUS;
}
//
// If there is no activity then return to the idle state.
//
if(g_ulIdleTimeout == 0)
{
UpdateStatus("Idle ", 0);
g_eMSCState = MSC_DEV_IDLE;
}
break;
}
case MSC_DEV_WRITE:
{
//
// Update the screen if necessary.
//
if(g_ulFlags & FLAG_UPDATE_STATUS)
{
UpdateStatus("Writing ", 0);
g_ulFlags &= ~FLAG_UPDATE_STATUS;
}
//
// If there is no activity then return to the idle state.
//
if(g_ulIdleTimeout == 0)
{
UpdateStatus("Idle ", 0);
g_eMSCState = MSC_DEV_IDLE;
}
break;
}
case MSC_DEV_IDLE:
default:
{
break;
}
}
}
#endif
}
