示例#1
0
文件: cpld.c 项目: Aorjoa/bootloader
int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	int rc = 0;
	unsigned int i;

	if (argc <= 1)
		return cmd_usage(cmdtp);

	if (strcmp(argv[1], "reset") == 0) {
		if (strcmp(argv[2], "altbank") == 0)
			cpld_set_altbank();
		else
			cpld_clear_altbank();

		cpld_reset();
	} else if (strcmp(argv[1], "watchdog") == 0) {
		static char *period[8] = {"1ms", "10ms", "30ms", "disable",
			"100ms", "1s", "10s", "60s"};
		for (i = 0; i < ARRAY_SIZE(period); i++) {
			if (strcmp(argv[2], period[i]) == 0)
				CPLD_WRITE(wd_cfg, i);
		}
	} else if (strcmp(argv[1], "lane_mux") == 0) {
		u32 lane = simple_strtoul(argv[2], NULL, 16);
		u8 val = (u8)simple_strtoul(argv[3], NULL, 16);
		u8 reg = CPLD_READ(serdes_mux);

		switch (lane) {
		case 0x6:
			reg &= ~SERDES_MUX_LANE_6_MASK;
			reg |= val << SERDES_MUX_LANE_6_SHIFT;
			break;
		case 0xa:
			reg &= ~SERDES_MUX_LANE_A_MASK;
			reg |= val << SERDES_MUX_LANE_A_SHIFT;
			break;
		case 0xc:
			reg &= ~SERDES_MUX_LANE_C_MASK;
			reg |= val << SERDES_MUX_LANE_C_SHIFT;
			break;
		case 0xd:
			reg &= ~SERDES_MUX_LANE_D_MASK;
			reg |= val << SERDES_MUX_LANE_D_SHIFT;
			break;
		default:
			printf("Invalid value\n");
			break;
		}

		CPLD_WRITE(serdes_mux, reg);
#ifdef DEBUG
	} else if (strcmp(argv[1], "dump") == 0) {
		cpld_dump_regs();
#endif
	} else
		rc = cmd_usage(cmdtp);

	return rc;
}
示例#2
0
/**
 * Set the boot bank to the alternate bank
 */
void __cpld_set_altbank(void)
{
	u8 reg5 = CPLD_READ(sw_ctl_on);

	CPLD_WRITE(sw_ctl_on, reg5 | CPLD_SWITCH_BANK_ENABLE);
	CPLD_WRITE(fbank_sel, 1);
	CPLD_WRITE(system_rst, 1);
}
示例#3
0
文件: cpld.c 项目: 01hyang/u-boot
/* Set the boot bank to the alternate bank */
void cpld_set_altbank(void)
{
	u8 reg4 = CPLD_READ(soft_mux_on);
	u8 reg7 = CPLD_READ(vbank);

	CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL);

	reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK;
	CPLD_WRITE(vbank, reg7);

	CPLD_WRITE(system_rst, 1);
}
示例#4
0
文件: cpld.c 项目: 01hyang/u-boot
void cpld_set_sd(void)
{
	u16 reg = CPLD_CFG_RCW_SRC_SD;
	u8 reg5 = (u8)(reg >> 1);
	u8 reg6 = (u8)(reg & 1);

	cpld_rev_bit(&reg5);

	CPLD_WRITE(soft_mux_on, 1);

	CPLD_WRITE(cfg_rcw_src1, reg5);
	CPLD_WRITE(cfg_rcw_src2, reg6);

	CPLD_WRITE(system_rst, 1);
}
示例#5
0
void
zflash_reg8_write(void *arg, int reg, u_int8_t value)
{
	struct zflash_softc *sc = arg;

	switch (reg) {
	case FLASH_REG_DATA:
	case FLASH_REG_COL:
	case FLASH_REG_ROW:
	case FLASH_REG_CMD:
		CPLD_WRITE(sc, CPLD_REG_FLASHIO, value);
		break;
	case FLASH_REG_ALE:
		CPLD_SETORCLR(sc, CPLD_REG_FLASHCTL, FLASHCTL_ALE, value);
		break;
	case FLASH_REG_CLE:
		CPLD_SETORCLR(sc, CPLD_REG_FLASHCTL, FLASHCTL_CLE, value);
		break;
	case FLASH_REG_CE:
		CPLD_SETORCLR(sc, CPLD_REG_FLASHCTL, FLASHCTL_NCE, !value);
		break;
	case FLASH_REG_WP:
		CPLD_SETORCLR(sc, CPLD_REG_FLASHCTL, FLASHCTL_NWP, !value);
		break;
#ifdef DIAGNOSTIC
	default:
		printf("%s: write to pseudo-register %02x\n",
		    sc->sc_flash.sc_dev.dv_xname, reg);
#endif
	}
}
示例#6
0
int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	int rc = 0;

	if (argc <= 1)
		return cmd_usage(cmdtp);

	if (strcmp(argv[1], "reset") == 0) {
		if (strcmp(argv[2], "altbank") == 0)
			cpld_set_altbank();
		else
			cpld_set_defbank();
	} else if (strcmp(argv[1], "lane_mux") == 0) {
		u32 lane = simple_strtoul(argv[2], NULL, 16);
		u8 val = (u8)simple_strtoul(argv[3], NULL, 16);
		u8 reg = CPLD_READ(serdes_mux);

		switch (lane) {
		case 0x6:
			reg &= ~SERDES_MUX_LANE_6_MASK;
			reg |= val << SERDES_MUX_LANE_6_SHIFT;
			break;
		case 0xa:
			reg &= ~SERDES_MUX_LANE_A_MASK;
			reg |= val << SERDES_MUX_LANE_A_SHIFT;
			break;
		case 0xc:
			reg &= ~SERDES_MUX_LANE_C_MASK;
			reg |= val << SERDES_MUX_LANE_C_SHIFT;
			break;
		case 0xd:
			reg &= ~SERDES_MUX_LANE_D_MASK;
			reg |= val << SERDES_MUX_LANE_D_SHIFT;
			break;
		default:
			printf("Invalid value\n");
			break;
		}

		CPLD_WRITE(serdes_mux, reg);
#ifdef DEBUG
	} else if (strcmp(argv[1], "dump") == 0) {
		cpld_dump_regs();
#endif
	} else
		rc = cmd_usage(cmdtp);

	return rc;
}
示例#7
0
void
zflashattach(struct device *parent, struct device *self, void *aux)
{
	struct zflash_softc *sc = (struct zflash_softc *)self;
	struct pxaip_attach_args *pxa = aux;
	bus_addr_t addr = pxa->pxa_addr;
	bus_size_t size = pxa->pxa_size;

	sc->sc_iot = pxa->pxa_iot;

	if ((int)addr == -1 || (int)size == 0) {
		addr = 0x0c000000;
		size = 0x00001000;
	}

	if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh) != 0) {
		printf(": failed to map controller\n");
		return;
	}

	/* Disable and write-protect the chip. */
	CPLD_WRITE(sc, CPLD_REG_FLASHCTL, FLASHCTL_NCE);

	flashattach(&sc->sc_flash, &zflash_ctl_tag, sc);

	switch (sc->sc_flash.sc_flashdev->id) {
	case FLASH_DEVICE_SAMSUNG_K9F2808U0C: /* C3000 */
		sc->sc_ioobpostbadblk = 4;
		sc->sc_ioobbadblk = 5;
		break;
	case FLASH_DEVICE_SAMSUNG_K9F1G08U0A: /* C3100 */
		sc->sc_ioobpostbadblk = 4;
		sc->sc_ioobbadblk = 0;
		break;
	}
}
示例#8
0
文件: cpld.c 项目: 01hyang/u-boot
/* Set the boot bank to the default bank */
void cpld_set_defbank(void)
{
	CPLD_WRITE(global_rst, 1);
}
示例#9
0
/**
 * Set the boot bank to the default bank
 */
void __cpld_set_defbank(void)
{
	CPLD_WRITE(system_rst_default, 1);
}
示例#10
0
/*
 * Reset the board. This honors the por_cfg registers.
 */
void __cpld_reset(void)
{
	CPLD_WRITE(system_rst, 1);
}
示例#11
0
int
zflash_regx_write_page(void *arg, caddr_t data, caddr_t oob)
{
	struct zflash_softc *sc = arg;
	int i;

	if (oob == NULL || sc->sc_flash.sc_flashdev->pagesize != 512) {
		flash_reg8_write_page(&sc->sc_flash, data, oob);
		return 0;
	}

	if (oob[OOB_JFFS2_ECC0] != 0xff || oob[OOB_JFFS2_ECC1] != 0xff ||
	    oob[OOB_JFFS2_ECC2] != 0xff || oob[OOB_JFFS2_ECC3] != 0xff ||
	    oob[OOB_JFFS2_ECC4] != 0xff || oob[OOB_JFFS2_ECC5] != 0xff) {
#ifdef DIAGNOSTIC
		printf("%s: non-FF ECC bytes in OOB data\n",
		    sc->sc_flash.sc_dev.dv_xname);
#endif
		return EINVAL;
	}

	CPLD_WRITE(sc, CPLD_REG_ECCCLRR, 0x00);
	for (i = 0; i < sc->sc_flash.sc_flashdev->pagesize / 2; i++)
		flash_reg8_write(&sc->sc_flash, FLASH_REG_DATA, data[i]);

	oob[OOB_JFFS2_ECC0] = ~CPLD_READ(sc, CPLD_REG_ECCLPUB);
	oob[OOB_JFFS2_ECC1] = ~CPLD_READ(sc, CPLD_REG_ECCLPLB);
	oob[OOB_JFFS2_ECC2] = (~CPLD_READ(sc, CPLD_REG_ECCCP) << 2) | 0x03;

	if (CPLD_READ(sc, CPLD_REG_ECCCNTR) != 0) {
		printf("%s: ECC failed\n", sc->sc_flash.sc_dev.dv_xname);
		oob[OOB_JFFS2_ECC0] = 0xff;
		oob[OOB_JFFS2_ECC1] = 0xff;
		oob[OOB_JFFS2_ECC2] = 0xff;
		return EIO;
	}

	CPLD_WRITE(sc, CPLD_REG_ECCCLRR, 0x00);
	for (; i < sc->sc_flash.sc_flashdev->pagesize; i++)
		flash_reg8_write(&sc->sc_flash, FLASH_REG_DATA, data[i]);

	oob[OOB_JFFS2_ECC3] = ~CPLD_READ(sc, CPLD_REG_ECCLPUB);
	oob[OOB_JFFS2_ECC4] = ~CPLD_READ(sc, CPLD_REG_ECCLPLB);
	oob[OOB_JFFS2_ECC5] = (~CPLD_READ(sc, CPLD_REG_ECCCP) << 2) | 0x03;

	if (CPLD_READ(sc, CPLD_REG_ECCCNTR) != 0) {
		printf("%s: ECC failed\n", sc->sc_flash.sc_dev.dv_xname);
		oob[OOB_JFFS2_ECC0] = 0xff;
		oob[OOB_JFFS2_ECC1] = 0xff;
		oob[OOB_JFFS2_ECC2] = 0xff;
		oob[OOB_JFFS2_ECC3] = 0xff;
		oob[OOB_JFFS2_ECC4] = 0xff;
		oob[OOB_JFFS2_ECC5] = 0xff;
		return EIO;
	}

	for (i = 0; i < sc->sc_flash.sc_flashdev->oobsize; i++)
		flash_reg8_write(&sc->sc_flash, FLASH_REG_DATA, oob[i]);

	oob[OOB_JFFS2_ECC0] = 0xff;
	oob[OOB_JFFS2_ECC1] = 0xff;
	oob[OOB_JFFS2_ECC2] = 0xff;
	oob[OOB_JFFS2_ECC3] = 0xff;
	oob[OOB_JFFS2_ECC4] = 0xff;
	oob[OOB_JFFS2_ECC5] = 0xff;
	return 0;
}
示例#12
0
文件: cpld.c 项目: Aorjoa/bootloader
/**
 * Set the boot bank to the default bank
 */
void __cpld_clear_altbank(void)
{
	CPLD_WRITE(fbank_sel, 0);
}
示例#13
0
文件: cpld.c 项目: Aorjoa/bootloader
/**
 * Set the boot bank to the alternate bank
 */
void __cpld_set_altbank(void)
{
	CPLD_WRITE(fbank_sel, 1);
}