void db_cpuinfo_cmd(db_expr_t addr, int have_addr, db_expr_t count, char *modif) { int i; for (i = 0; i < MAXCPUS; i++) { if (cpu_info[i] != NULL) { db_printf("%c%4d: ", (i == cpu_number()) ? '*' : ' ', CPU_INFO_UNIT(cpu_info[i])); switch(cpu_info[i]->ci_ddb_paused) { case CI_DDB_RUNNING: db_printf("running\n"); break; case CI_DDB_SHOULDSTOP: db_printf("stopping\n"); break; case CI_DDB_STOPPED: db_printf("stopped\n"); break; case CI_DDB_ENTERDDB: db_printf("entering ddb\n"); break; case CI_DDB_INDDB: db_printf("ddb\n"); break; default: db_printf("? (%d)\n", cpu_info[i]->ci_ddb_paused); break; } } } }
void amptimer_cpu_initclocks() { struct amptimer_softc *sc = amptimer_cd.cd_devs[0]; struct amptimer_pcpu_softc *pc = &sc->sc_pstat[CPU_INFO_UNIT(curcpu())]; uint64_t next; #if defined(USE_GTIMER_CMP) uint32_t reg; #endif stathz = hz; profhz = hz * 10; if (sc->sc_ticks_per_second != amptimer_frequency) { amptimer_set_clockrate(amptimer_frequency); } amptimer_setstatclockrate(stathz); sc->sc_ticks_per_intr = sc->sc_ticks_per_second / hz; sc->sc_ticks_err_cnt = sc->sc_ticks_per_second % hz; pc->pc_ticks_err_sum = 0; /* establish interrupts */ /* XXX - irq */ #if defined(USE_GTIMER_CMP) ampintc_intr_establish(27, IPL_CLOCK, amptimer_intr, NULL, "tick"); #else ampintc_intr_establish(29, IPL_CLOCK, amptimer_intr, NULL, "tick"); #endif next = amptimer_readcnt64(sc) + sc->sc_ticks_per_intr; pc->pc_nexttickevent = pc->pc_nextstatevent = next; #if defined(USE_GTIMER_CMP) reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GTIMER_CTRL); reg &= ~GTIMER_CTRL_COMP; bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTIMER_CTRL, reg); bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTIMER_CMP_LOW, next & 0xffffffff); bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTIMER_CMP_HIGH, next >> 32); reg |= GTIMER_CTRL_COMP | GTIMER_CTRL_IRQ; bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTIMER_CTRL, reg); #else bus_space_write_4(sc->sc_iot, sc->sc_pioh, PTIMER_CTRL, (PTIMER_CTRL_ENABLE | PTIMER_CTRL_IRQEN)); bus_space_write_4(sc->sc_iot, sc->sc_pioh, PTIMER_LOAD, sc->sc_ticks_per_intr); #endif }
void amptimer_startclock(void) { struct amptimer_softc *sc = amptimer_cd.cd_devs[0]; struct amptimer_pcpu_softc *pc = &sc->sc_pstat[CPU_INFO_UNIT(curcpu())]; uint64_t nextevent; nextevent = amptimer_readcnt64(sc) + sc->sc_ticks_per_intr; pc->pc_nexttickevent = pc->pc_nextstatevent = nextevent; bus_space_write_4(sc->sc_iot, sc->sc_pioh, PTIMER_LOAD, sc->sc_ticks_per_intr); }
void db_command_loop(void) { label_t db_jmpbuf; label_t *savejmp; extern int db_output_line; /* * Initialize 'prev' and 'next' to dot. */ db_prev = db_dot; db_next = db_dot; db_cmd_loop_done = 0; savejmp = db_recover; db_recover = &db_jmpbuf; (void) setjmp(&db_jmpbuf); while (!db_cmd_loop_done) { if (db_print_position() != 0) db_printf("\n"); db_output_line = 0; #ifdef MULTIPROCESSOR db_printf("ddb{%d}> ", CPU_INFO_UNIT(curcpu())); #else db_printf("ddb> "); #endif (void) db_read_line(); db_command(&db_last_command, db_command_table); } db_recover = savejmp; }
int amptimer_intr(void *frame) { struct amptimer_softc *sc = amptimer_cd.cd_devs[0]; struct amptimer_pcpu_softc *pc = &sc->sc_pstat[CPU_INFO_UNIT(curcpu())]; uint64_t now; uint64_t nextevent; uint32_t r, reg; #if defined(USE_GTIMER_CMP) int skip = 1; #else int64_t delay; #endif int rc = 0; /* * DSR - I know that the tick timer is 64 bits, but the following * code deals with rollover, so there is no point in dealing * with the 64 bit math, just let the 32 bit rollover * do the right thing */ now = amptimer_readcnt64(sc); while (pc->pc_nexttickevent <= now) { pc->pc_nexttickevent += sc->sc_ticks_per_intr; pc->pc_ticks_err_sum += sc->sc_ticks_err_cnt; /* looping a few times is faster than divide */ while (pc->pc_ticks_err_sum > hz) { pc->pc_nexttickevent += 1; pc->pc_ticks_err_sum -= hz; } #ifdef AMPTIMER_DEBUG sc->sc_clk_count.ec_count++; #endif rc = 1; hardclock(frame); } while (pc->pc_nextstatevent <= now) { do { r = random() & (sc->sc_statvar -1); } while (r == 0); /* random == 0 not allowed */ pc->pc_nextstatevent += sc->sc_statmin + r; /* XXX - correct nextstatevent? */ #ifdef AMPTIMER_DEBUG sc->sc_stat_count.ec_count++; #endif rc = 1; statclock(frame); } if (pc->pc_nexttickevent < pc->pc_nextstatevent) nextevent = pc->pc_nexttickevent; else nextevent = pc->pc_nextstatevent; #if defined(USE_GTIMER_CMP) again: reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GTIMER_CTRL); reg &= ~GTIMER_CTRL_COMP; bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTIMER_CTRL, reg); bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTIMER_CMP_LOW, nextevent & 0xffffffff); bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTIMER_CMP_HIGH, nextevent >> 32); reg |= GTIMER_CTRL_COMP; bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTIMER_CTRL, reg); now = amptimer_readcnt64(sc); if (now >= nextevent) { nextevent = now + skip; skip += 1; goto again; } #else /* clear old status */ bus_space_write_4(sc->sc_iot, sc->sc_pioh, PTIMER_STATUS, PTIMER_STATUS_EVENT); delay = nextevent - now; if (delay < 0) delay = 1; reg = bus_space_read_4(sc->sc_iot, sc->sc_pioh, PTIMER_CTRL); if ((reg & (PTIMER_CTRL_ENABLE | PTIMER_CTRL_IRQEN)) != (PTIMER_CTRL_ENABLE | PTIMER_CTRL_IRQEN)) bus_space_write_4(sc->sc_iot, sc->sc_pioh, PTIMER_CTRL, (PTIMER_CTRL_ENABLE | PTIMER_CTRL_IRQEN)); bus_space_write_4(sc->sc_iot, sc->sc_pioh, PTIMER_LOAD, delay); #endif return (rc); }