void soc_sleep_config(void)
{
int i = 0;
for (i = 0; i < CRU_CLKGATES_CON_CNT; i++)
mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), 0xffff0000);
pm_plls_suspend();
for (i = 0; i < CRU_CLKGATES_CON_CNT; i++)
mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), 0xffff0000);
}
static void rk30_arch_reset(char mode, const char *cmd)
{
u32 boot_flag = 0;
u32 boot_mode = BOOT_MODE_REBOOT;
if (cmd) {
if (!strcmp(cmd, "loader") || !strcmp(cmd, "bootloader"))
boot_flag = SYS_LOADER_REBOOT_FLAG + BOOT_LOADER;
else if(!strcmp(cmd, "recovery"))
boot_flag = SYS_LOADER_REBOOT_FLAG + BOOT_RECOVER;
else if (!strcmp(cmd, "charge"))
boot_mode = BOOT_MODE_CHARGE;
} else {
if (system_state != SYSTEM_RESTART)
boot_mode = BOOT_MODE_PANIC;
}
writel_relaxed(boot_flag, RK30_PMU_BASE + PMU_SYS_REG0); // for loader
writel_relaxed(boot_mode, RK30_PMU_BASE + PMU_SYS_REG1); // for linux
dsb();
{ //zyf emmc reset to boot mode
writel_relaxed(0x40000000, RK30_CRU_BASE + CRU_CLKGATES_CON(2)); // bit14
writel_relaxed(0x10000000, RK30_CRU_BASE + CRU_CLKGATES_CON(5)); // bit12
#define RK30_EMMC_BASE RK30_IO_TO_VIRT0(RK30_EMMC_PHYS)
writel_relaxed(0, RK30_EMMC_BASE + 0x04);// power disable
writel_relaxed(0, RK30_EMMC_BASE + 0x78); //reset on
dsb();
mdelay(200);
writel_relaxed(1, RK30_EMMC_BASE + 0x04); // power enable
writel_relaxed(1, RK30_EMMC_BASE + 0x78); // reset off
dsb();
sram_printascii("reset\n");
}
/* disable remap */
writel_relaxed(1 << (12 + 16), RK30_GRF_BASE + GRF_SOC_CON0);
/* pll enter slow mode */
writel_relaxed(PLL_MODE_SLOW(APLL_ID) | PLL_MODE_SLOW(CPLL_ID) | PLL_MODE_SLOW(GPLL_ID), RK30_CRU_BASE + CRU_MODE_CON);
dsb();
writel_relaxed(0xeca8, RK30_CRU_BASE + CRU_GLB_SRST_SND);
dsb();
}
static void __sramfunc rk29_pwm_set_core_voltage(unsigned int uV)
{
u32 clk_gate2;
char id = 3;
//sram_printch('y');
#if 1
gate_save_soc_clk(0
| (1 << CLK_GATE_ACLK_PEIRPH % 16)
| (1 << CLK_GATE_HCLK_PEIRPH % 16)
| (1 << CLK_GATE_PCLK_PEIRPH % 16)
, clk_gate2, CRU_CLKGATES_CON(2), 0
| (1 << ((CLK_GATE_ACLK_PEIRPH % 16) + 16))
| (1 << ((CLK_GATE_HCLK_PEIRPH % 16) + 16))
| (1 << ((CLK_GATE_PCLK_PEIRPH % 16) + 16)));
#endif
/* iomux pwm3 */
writel_relaxed((readl_relaxed(RK30_GRF_BASE + 0xB4) & ~(0x1<<14)) | (0x1<<14) |(0x1<<30), RK30_GRF_BASE + 0xB4);//PWM
if (uV) {
pwm_lrc = pwm_read_reg(id,PWM_REG_LRC);
pwm_hrc = pwm_read_reg(id,PWM_REG_HRC);
writel_relaxed((readl_relaxed(RK30_GRF_BASE + 0xB4) & ~(0x1<<14)) | (0x1<<30), RK30_GRF_BASE + 0xB4);//GPIO
grf_writel(GPIO0_PD7_DIR_OUT, GRF_GPIO0H_DIR_ADDR);
grf_writel(GPIO0_PD7_DO_HIGH, GRF_GPIO0H_DO_ADDR);
grf_writel(GPIO0_PD7_EN_MASK, GRF_GPIO0H_EN_ADDR);
}else
{
pwm_write_reg(id,PWM_REG_CTRL, PWM_DIV|PWM_RESET);
pwm_write_reg(id,PWM_REG_LRC, pwm_lrc);
pwm_write_reg(id,PWM_REG_HRC, pwm_hrc);
pwm_write_reg(id,PWM_REG_CNTR, 0);
pwm_write_reg(id,PWM_REG_CTRL, PWM_DIV|PWM_ENABLE|PWM_TimeEN);
}
LOOP(10 * 1000 * LOOPS_PER_USEC); /* delay 10ms */
cru_writel(clk_gate2, CRU_CLKGATES_CON(2));
}
