/** * @brief * Configure the sgmii Serdes on devices using the initialization sequence */ void configSerdes() { /* Unlock the chip configuration registers to allow SGMII SERDES registers to * be written */ CSL_BootCfgUnlockKicker(); /* Configure the SERDES */ /* Multiply to be 8 with Quarter Rate in the Rx registers */ CSL_BootCfgSetSGMIIConfigPLL (0x00000041); platform_delaycycles(100); //31:25 Reserved 0000000 //23:24 LOOPBACK 00 // 22 ENOC 1 //21:18 EQ 0001 //17:15 CDR 001 -- first order threshold of 17 //14:12 LOS 000 -- tie off //11:10 ALIGN 01 -- Comma Aligned //09:07 TERM 100 -- tie off (100) // 06 INVPAIR 0 //05:04 RATE 01 -- tie off (10) //00 = Full Rate, 01 = Half Rate (*0.5), 10 = Quarter Rate (*0.25) //03:01 BUSWIDTH 000 -- tie off // 00 ENRX 1 // 0000 0000 0100 0100 0000 0010 0001 0001 = 0x0044_0211 -- My estimated value // 0000 0000 0100 0100 0000 0100 0001 0001 = 0x0044_0411 -- New DV value // 0000 0000 0000 1000 0000 1000 0100 0001 = 0x0008_0841 -- Original DV value CSL_BootCfgSetSGMIIRxConfig (0, 0x00700621); CSL_BootCfgSetSGMIIRxConfig (1, 0x00700621); //31:22 Reserved 0 //21:20 LOOPBACK 00 //19:18 RDTCT 00 -- tie off // 17 ENIDL 0 -- tie off // 16 MYSNC 1 -- tie off //15:12 DEMPHASIS ???? - 0001 Lets give some de-emphasis //11:08 SWING ???? // 07 CM 1 -- tie off // 06 INVPAIR 0 //05:04 RATE 01 -- tie off //03:01 BUSWIDTH 000 -- tie off // 00 ENTX 1 // 0000 0000 0011 0001 ???? ???? 1001 0001 = 0x0031_1E91 -- My estimated value // 0000 0000 0000 0001 0000 1111 0001 0001 = 0x0001_0F11 -- New DV value // 0000 0000 0100 0000 0001 1110 0100 0001 = 0x0040_1e41 -- Original DV value CSL_BootCfgSetSGMIITxConfig (0, 0x000108A1); CSL_BootCfgSetSGMIITxConfig (1, 0x000108A1); /* All done with configuration. Return Now. */ return; }
/** ============================================================================ * @n@b Init_SGMII_SERDES * * @b Description * @n This API sets up the configuration for the SGMII SERDES. Assumes a 125 MHz * reference clock. * * @param[in] * @n None * * @return * @n None * ============================================================================= */ Int32 Init_SGMII_SERDES(Void) { CSL_SGMII_STATUS sgmii_status; /* * The following SERDES configuration is required for chip simulator only. * The platform-dependent SERDES configuration should be done by the corresponding * CCS GEL scripts or platformLib */ //if (cpswSimTest) //{ /* Unlock the chip configuration registers to allow SGMII SERDES registers to * be written */ CSL_BootCfgUnlockKicker(); CSL_BootCfgSetSGMIIConfigPLL (0x00000041); CSL_BootCfgSetSGMIIRxConfig (0, 0x00700621); CSL_BootCfgSetSGMIITxConfig (0, 0x000108A1); CSL_BootCfgSetSGMIIRxConfig (1, 0x00700621); CSL_BootCfgSetSGMIITxConfig (1, 0x000108A1); /* Re-lock the chip configuration registers to prevent unintentional writes */ CSL_BootCfgLockKicker(); // } /* Poll the SGMII0 lock bit to confirm that the sgmii module has recognized that the SERDES PLL has locked */ do { CSL_SGMII_getStatus(0, &sgmii_status); } while (sgmii_status.bIsLocked != 1); /* Poll the SGMII1 lock bit to confirm that the sgmii module has recognized that the SERDES PLL has locked */ do { CSL_SGMII_getStatus(1, &sgmii_status); } while (sgmii_status.bIsLocked != 1); //platform_write("serdes PLL locked for both PHY \n"); /* SGMII SERDES Configuration complete. Return. */ return 0; }
/** * @brief * Configure the sgmii Serdes on devices using the initialization sequence */ void configSerdes() { CSL_SGMII_STATUS sgmii_status; uint32_t loopCount; /* Unlock the chip configuration registers to allow SGMII SERDES registers to * be written */ CSL_BootCfgUnlockKicker(); /* Configure the SERDES */ /* Multiply to be 8 with Quarter Rate in the Rx registers */ CSL_BootCfgSetSGMIIConfigPLL (0x00000051); loopCount = 100; while (loopCount--) { asm(" NOP"); } //31:25 Reserved 0000000 //23:24 LOOPBACK 00 // 22 ENOC 1 //21:18 EQ 0001 //17:15 CDR 001 -- first order threshold of 17 //14:12 LOS 000 -- tie off //11:10 ALIGN 01 -- Comma Aligned //09:07 TERM 100 -- tie off (100) // 06 INVPAIR 0 //05:04 RATE 01 -- tie off (10) //00 = Full Rate, 01 = Half Rate (*0.5), 10 = Quarter Rate (*0.25) //03:01 BUSWIDTH 000 -- tie off // 00 ENRX 1 // 0000 0000 0100 0100 0000 0010 0001 0001 = 0x0044_0211 -- My estimated value // 0000 0000 0100 0100 0000 0100 0001 0001 = 0x0044_0411 -- New DV value // 0000 0000 0000 1000 0000 1000 0100 0001 = 0x0008_0841 -- Original DV value CSL_BootCfgSetSGMIIRxConfig (0, 0x00700621); CSL_BootCfgSetSGMIIRxConfig (1, 0x00700621); //31:22 Reserved 0 //21:20 LOOPBACK 00 //19:18 RDTCT 00 -- tie off // 17 ENIDL 0 -- tie off // 16 MYSNC 1 -- tie off //15:12 DEMPHASIS ???? - 0001 Lets give some de-emphasis //11:08 SWING ???? // 07 CM 1 -- tie off // 06 INVPAIR 0 //05:04 RATE 01 -- tie off //03:01 BUSWIDTH 000 -- tie off // 00 ENTX 1 // 0000 0000 0011 0001 ???? ???? 1001 0001 = 0x0031_1E91 -- My estimated value // 0000 0000 0000 0001 0000 1111 0001 0001 = 0x0001_0F11 -- New DV value // 0000 0000 0100 0000 0001 1110 0100 0001 = 0x0040_1e41 -- Original DV value CSL_BootCfgSetSGMIITxConfig (0, 0x000108A1); CSL_BootCfgSetSGMIITxConfig (1, 0x000108A1); /* Poll the SGMII0 lock bit to confirm that the sgmii module has recognized that the SERDES PLL has locked */ do { CSL_SGMII_getStatus(0, &sgmii_status); } while (sgmii_status.bIsLocked != 1); /* Poll the SGMII1 lock bit to confirm that the sgmii module has recognized that the SERDES PLL has locked */ do { CSL_SGMII_getStatus(1, &sgmii_status); } while (sgmii_status.bIsLocked != 1); /* All done with configuration. Return Now. */ return; }