/** ===========================================================================
* @n@b GPT_close
*
* @b Description
* @n This function close GPT operation.
*
* @b Arguments
* @verbatim
hGpt Handle to the GPT
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Close successful
* @li CSL_ESYS_BADHANDLE - Invalid handle
*
* <b> Pre Condition </b>
* @n GPT_open() must be called before this function call.
*
* <b> Post Condition </b>
* @n After calling this function no other function can call.
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_status status;
CSL_Handle hGpt;
...
hgpt = GPT_open(GPT_0, &gptObj, &status);
status = GPT_close(hgpt);
@endverbatim
* ===========================================================================
*/
CSL_Status GPT_close(CSL_Handle hGpt)
{
ioport volatile CSL_SysRegs *sysRegs;
if(NULL == hGpt)
{
return (CSL_ESYS_BADHANDLE);
}
sysRegs = (CSL_SysRegs *)CSL_SYSCTRL_REGS;
/* Disable Module related timmer registers */
switch(hGpt->Instance)
{
case GPT_0:
CSL_FINS(sysRegs->PCGCR1, SYS_PCGCR1_TMR0CG,
CSL_SYS_PCGCR1_TMR0CG_DISABLED);
break;
case GPT_1:
CSL_FINS(sysRegs->PCGCR1, SYS_PCGCR1_TMR1CG,
CSL_SYS_PCGCR1_TMR1CG_DISABLED);
break;
case GPT_2:
CSL_FINS(sysRegs->PCGCR1, SYS_PCGCR1_TMR2CG,
CSL_SYS_PCGCR1_TMR2CG_DISABLED);
break;
}
/* Set the handler value to NULL */
hGpt->regs = NULL;
hGpt = NULL;
return (CSL_SOK);
}
/*
* EZDSP5535_SPI_init( )
*
* Enables and configures SPI for the SPIFLASH
* ( CS0, EBSR Mode 1, 8-bit, 100KHz clock )
*/
void EZDSP5535_SPI_init(void)
{
/* Configuration for SPI
SPI_Config hwConfig;
hwConfig.wLen = SPI_WORD_LENGTH_8; // 8-bit
hwConfig.spiClkDiv = 0x0041; // 100KHz clock (12MHz / 120)
hwConfig.csNum = SPI_CS_NUM_2; // Select CS2
hwConfig.frLen = 1;
hwConfig.dataDelay = SPI_DATA_DLY_0;
hwConfig.clkPol = SPI_CLKP_LOW_AT_IDLE;
*/
/* Disable the serial Data clock */
CSL_SPI_REGS->SPICCR = 0x0000;
CSL_SPI_REGS->SPICDR = 0x002f; // 100KHz clock (12MHz / 120)
EZDSP5535_waitusec(1);
/* Enable the serial Data clock */
CSL_SPI_REGS->SPICCR = 0x8000;
/* Set Data delay, cs pol, clk pol and clpck pkase bit as per chip select */
CSL_FINS(CSL_SPI_REGS->SPIDCR2, SPI_SPIDCR2_DD2, SPI_DATA_DLY_0);
CSL_FINS(CSL_SPI_REGS->SPIDCR2, SPI_SPIDCR2_CSP2, 0);
CSL_FINS(CSL_SPI_REGS->SPIDCR2, SPI_SPIDCR2_CKP2, SPI_CLKP_LOW_AT_IDLE);
CSL_FINS(CSL_SPI_REGS->SPIDCR2, SPI_SPIDCR2_CKPH2, 0);
CSL_CPU_REGS->IER1 |= 0x0008; // SPI interrupt
}
/** ===========================================================================
* @n@b GPT_config
*
* @b Description
* @n This function is to Configure the GPT haware related registers
*
* @b Arguments
* @verbatim
hGpt Handle to the GPT
hwConfig configuration structure.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Close successful
* @li CSL_ESYS_BADHANDLE - Invalid handle
*
* <b> Pre Condition </b>
* @n GPT_open() must be called before this function call.
*
* <b> Post Condition </b>
* @n After calling this function GPT_reset() API should call to close
* gpt operation.
*
* @b Modifies
* @n This function modifies the GPT object structure.
*
* @b Example
* @verbatim
CSL_status status;
CSL_Handle hGpt;
CSL_Config hwConfig;
...
hwConfig.autoLoad = GPT_AUTO_ENABLE;
hwConfig.ctrlTim = GPT_TIMER_ENABLE;
hwConfig.preScaleDiv = GPT_PRE_SC_DIV_3;
hwConfig.prdLow = 0xFFFF;
hwConfig.prdHigh = 0x0000;
hgpt = GPT_open(GPT_0, &gptObj, &status);
status = GPT_config(hgpt, &hwConfig);
@endverbatim
* ===========================================================================
*/
CSL_Status GPT_config(CSL_Handle hGpt, CSL_Config *hwConfig)
{
CSL_TimRegsOvly regPtr;
if(NULL == hGpt)
{
return (CSL_ESYS_BADHANDLE);
}
if(NULL == hwConfig)
{
return (CSL_ESYS_INVPARAMS);
}
regPtr = hGpt->regs;
/* Set Timer Disable */
CSL_FINS(regPtr->TCR, TIM_TCR_TIMEN, CSL_TIM_TCR_TIMEN_DISABLE);
/* Set the Pre-scale devider */
CSL_FINS(regPtr->TCR, TIM_TCR_PSCDIV, hwConfig->preScaleDiv);
/* Auto load enable or disable */
CSL_FINS(regPtr->TCR, TIM_TCR_AUTORELOAD, hwConfig->autoLoad);
/* Enable/Disable pre-scale control timer */
CSL_FINS(regPtr->TCR, TIM_TCR_TIMEN, hwConfig->ctrlTim);
/* Set GPT counter register to default value as 0 */
regPtr->TIMCNT1 = CSL_TIM_TIMCNT1_RESETVAL;
regPtr->TIMCNT2 = CSL_TIM_TIMCNT2_RESETVAL;
/* Set period register */
regPtr->TIMPRD1 = hwConfig->prdLow;
regPtr->TIMPRD2 = hwConfig->prdHigh;
return (CSL_SOK);
}
void profileInit(int i)
{
CSL_TmrRegsOvly timer;
timer = TIMER_REGS[i];
resetTimer(timer);
setupTimer64(timer, 0xFFFFFFFFFFFFFFFF);
CSL_FINS(timer->TIM12, TMR_TIM12_CNT12, 0); // Load GPTx TIM1234 Counter w/ 0 (Start at beginning)
CSL_FINS(timer->TIM34, TMR_TIM34_CNT34, 0);
}
/**
* @b Description
* @n
* This function sets the threshold at which the queue threshold pin is asserted and
* threshold bit in threshold status register is set.
* "hilo" indicates whether the number of items in the queue should be greater than/equal to
* OR less than the confgiured threshold value before the queue ecnt status bit is asserted and
* threshold bit in threshold status register is set.
* The threshold value is 10'h3ff when it is ten or higher. It is (2^threshold-1) for other values.
*
* @param[in] hnd
* Queue handle.
*
* @param[in] hilo
* 1 - High
* 0 - Low.
*
* @param[in] threshold
* Threshold value.
*
* @pre
* Qmss_queueOpen function should be called before calling this function.
*
* @retval
* None
*/
void Qmss_setQueueThreshold (Qmss_QueueHnd hnd, uint16_t hilo, uint8_t threshold)
{
uint32_t temp = 0;
if (threshold > 10)
threshold = 10;
CSL_FINS (temp, QM_QUEUE_STATUS_CONFIG_QUEUE_STATUS_CONFIG_REG_D_THRESHOLD_HILO, hilo);
CSL_FINS (temp, QM_QUEUE_STATUS_CONFIG_QUEUE_STATUS_CONFIG_REG_D_THRESHOLD, threshold);
qmssLObj.qmQueStatReg->QUEUE_STATUS_CONFIG_GROUP[hnd].QUEUE_STATUS_CONFIG_REG_D = temp;
return;
}
Qmss_Result Qmss_setEoiVector (Qmss_IntdInterruptType type, uint8_t interruptNum)
{
if (qmssLObjIsValid == 0)
return QMSS_NOT_INITIALIZED;
if (type == Qmss_IntdInterruptType_HIGH)
CSL_FINS (qmssLObj.qmQueIntdReg->EOI_REG, QM_INTD_EOI_REG_EOI_VECTOR, Qmss_highEoiVector[interruptNum]);
else if (type == Qmss_IntdInterruptType_LOW)
CSL_FINS (qmssLObj.qmQueIntdReg->EOI_REG, QM_INTD_EOI_REG_EOI_VECTOR, Qmss_lowEoiVector[interruptNum]);
else
CSL_FINS (qmssLObj.qmQueIntdReg->EOI_REG, QM_INTD_EOI_REG_EOI_VECTOR, Qmss_cdmaEoiVector[interruptNum]);
return QMSS_SOK;
}
CSL_Status CSL_rszBufSwitch(CSL_RszHandle hndl, Uint8 rszMod, Uint32 timestamp, Uint32 count)
{
CSL_Status status = CSL_SOK;
Uint8 *pAddrY, *pAddrC;
if (rszMod >= CSL_RSZ_CH_MAX)
return CSL_EFAIL;
if (hndl->outBufSwitchEnable[rszMod]) {
/* update buffer height and width from hardware regs */
if (hndl->curBufInfo[rszMod].id != CSL_BUF_ID_INVALID) {
if (rszMod == CSL_RSZ_A) {
hndl->curBufInfo[rszMod].width = (hndl->regs->RZA_O_HSZ +1);
hndl->curBufInfo[rszMod].height = (hndl->regs->RZA_O_VSZ +1);
} else if (rszMod == CSL_RSZ_B) {
hndl->curBufInfo[rszMod].width = (hndl->regs->RZB_O_HSZ +1);
hndl->curBufInfo[rszMod].height = (hndl->regs->RZB_O_VSZ +1);
}
}
/* do buffer switch*/
status = CSL_bufSwitchFull(&hndl->outBuf[rszMod], &hndl->curBufInfo[rszMod], 1, timestamp, count);
if (hndl->curBufInfo[rszMod].id != CSL_BUF_ID_INVALID) {
pAddrY = (Uint8 *) hndl->curBufInfo[rszMod].addr;
pAddrC = (Uint8 *)( pAddrY + hndl->yuv420BufCoffset[rszMod]);
if(hndl->flipV[rszMod]) {
pAddrY += hndl->flipVOffsetY[rszMod];
pAddrC += hndl->flipVOffsetC[rszMod];
}
if(hndl->flipH[rszMod]) {
pAddrY += hndl->flipHOffsetYC[rszMod];
pAddrC += hndl->flipHOffsetYC[rszMod];
}
if(rszMod==CSL_RSZ_A) {
CSL_FINS(hndl->regs->SEQ, RSZ_SEQ_HRVA, hndl->flipH[rszMod]);
CSL_FINS(hndl->regs->SEQ, RSZ_SEQ_VRVA, hndl->flipV[rszMod]);
} else {
CSL_FINS(hndl->regs->SEQ, RSZ_SEQ_HRVB, hndl->flipH[rszMod]);
CSL_FINS(hndl->regs->SEQ, RSZ_SEQ_VRVB, hndl->flipV[rszMod]);
}
CSL_rszSetOutAddr(hndl, rszMod, pAddrY, pAddrC);
}
}
return status;
}
void setupTimer64(CSL_TmrRegsOvly timer, Uint64 Period)
{
Uint32 prd12, prd34;
CSL_FINST(timer->TGCR, TMR_TGCR_TIMMODE, 64BIT_GPTIM); // Init GPTx in 64-bit mode
CSL_FINST(timer->TGCR, TMR_TGCR_TIM12RS, NOT_IN_RESET); // Remove GPTx TIM12 from Reset
CSL_FINST(timer->TGCR, TMR_TGCR_TIM34RS, NOT_IN_RESET); // Remove GPTx TIM34 from Reset (required in 64-bit)
prd12 = Period >> 32;
prd34 = Period;
CSL_FINS(timer->PRD12, TMR_PRD12_PRD12, prd12); // Load GPTx TIM1234 Period
CSL_FINS(timer->PRD34, TMR_PRD34_PRD34, prd34);
}
/** ===========================================================================
* @n@b GPT_open
*
* @b Description
* @n This is the initialization function for the GPT CSL. The function
* must be called before calling any other API from this CSL. This
* function is idem-potent. Currently, the function just returns handler
* to application.
*
* @b Arguments
* @verbatim
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Always returns
*
* CSL_Handle
* Pointer to the object structure.
* <b> Pre Condition </b>
* @n This should be call first before calling any other GPT Function.
*
* <b> Post Condition </b>
* @n The status is updated in the status variable. If status
* returned is
* @li CSL_SOK - Valid GPT handle is returned
* @li CSL_ESYS_INVPARAMS - Invalid parameter
*
* @b Modifies
* @n 1. The status variable
* @n 2. The object structure handler.
*
* @b Example
* @verbatim
CSL_Handle hgpt;
CSL_Instance instance;
CSL_GptObj gptObj;
CSL_Status status;
....
....
instance = GPT_0.
hgpt = GPT_open(GPT_0, &gptObj, &status);
@endverbatim
* ===========================================================================
*/
CSL_Handle GPT_open(CSL_Instance instance,
CSL_GptObj *gptObj,
CSL_Status *status)
{
CSL_Handle hGpt;
ioport volatile CSL_SysRegs *sysRegs;
*status = CSL_SOK;
hGpt = NULL;
if(NULL == gptObj)
{
*status = CSL_ESYS_BADHANDLE;
return (hGpt);
}
if((instance < GPT_0) || (instance >= GPT_INVALID))
{
*status = CSL_ESYS_INVPARAMS;
return (hGpt);
}
hGpt = gptObj;
sysRegs = (CSL_SysRegs *)CSL_SYSCTRL_REGS;
switch (instance)
{
case GPT_0:
hGpt->Instance = GPT_0;
hGpt->regs = (CSL_TimRegsOvly)(CSL_TIM_0_REGS);
CSL_FINS(sysRegs->PCGCR1, SYS_PCGCR1_TMR0CG,
CSL_SYS_PCGCR1_TMR0CG_ACTIVE);
break;
case GPT_1:
hGpt->Instance = GPT_1;
hGpt->regs = (CSL_TimRegsOvly)(CSL_TIM_1_REGS);
CSL_FINS(sysRegs->PCGCR1, SYS_PCGCR1_TMR1CG,
CSL_SYS_PCGCR1_TMR1CG_ACTIVE);
break;
case GPT_2:
hGpt->Instance = GPT_2;
hGpt->regs = (CSL_TimRegsOvly)(CSL_TIM_2_REGS);
CSL_FINS(sysRegs->PCGCR1, SYS_PCGCR1_TMR2CG,
CSL_SYS_PCGCR1_TMR2CG_ACTIVE);
break;
default:
*status = CSL_ESYS_INVPARAMS;
}
return (hGpt);
}
/*Resets the Timer and the state variables This should be done only once during initialization*/
void TimerReset(TimerState* tState, int i)
{
CSL_TmrRegsOvly timer;
timer = TIMER_REGS[i];
tState->Count = 0;
tState->TotalCycles = 0;
tState->CurrentCycleCount = 0;
tState->AverageCycleCount = 0;
tState->PeakCycleCount = 0;
resetTimer(timer);
setupTimer64(timer, 0xFFFFFFFFFFFFFFFF);
CSL_FINS(timer->TIM12, TMR_TIM12_CNT12, 0); // Load GPTx TIM1234 Counter w/ 0 (Start at beginning)
CSL_FINS(timer->TIM34, TMR_TIM34_CNT34, 0);
}
CSL_Status SAR_chanOpen (
CSL_SarHandleObj *SarObj,
CSL_SarChanSel chanSel
)
{
if(NULL == SarObj)
{
return CSL_ESYS_BADHANDLE;
}
if( chanSel < 0 || chanSel > CSL_SAR_CHAN_5 )
{
return CSL_ESYS_INVPARAMS;
}
/* Select the channel */
CSL_FINS (CSL_SAR_REGS->SARCTRL, ANACTRL_SARCTRL_CHSEL, chanSel);
/* Set multich discharge of array for every conversion*/
CSL_FINST (CSL_SAR_REGS->SARCTRL, ANACTRL_SARCTRL_MULTCH, SET);
SarObj->chanNo = chanSel;
SarObj->baseAddr = CSL_SAR_REGS;
SarObj->status = CSL_SAR_OPEN;
return CSL_SOK;
}
/** ===========================================================================
* @n@b SPI_write
*
* @b Description
* @n This function Write data to specified device.
*
* @b Arguments
* @verbatim
hSpi Pointer to handler
writeBuff Pointer to the write buffer.
buffLen Maximum read buffer size.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Write successful
* @li CSL_ESYS_BADHANDLE - Invalid handle
*
* <b> Pre Condition </b>
* This function can call by SPI_dataTransaction function.
*
* <b> Post Condition </b>
* @n SPI_deInit can be call after this function call.
*
* @b Modifies
* @n
*
* @b Example
* @verbatim
CSL_SpiHandle hSpi
Uint16 writeBuff[size];
Uint16 buffLen;
CSL_status status;
status = SPI_write(hSpi,&writeBuff, buffLen);
@endverbatim
* ===========================================================================
*/
CSL_Status SPI_write (CSL_SpiHandle hSpi,
Uint16 *writeBuffer,
Uint16 bufLen)
{
Uint16 getWLen;
volatile Uint16 bufIndex;
Uint16 spiStatusReg;
volatile Uint16 spiBusyStatus;
volatile Uint16 spiWcStaus;
volatile Uint16 delay;
bufIndex = 0;
if((NULL == writeBuffer) || (0 == bufLen))
{
return (CSL_ESYS_INVPARAMS);
}
/* Read the word length form the register */
getWLen = CSL_FEXT(CSL_SPI_REGS->SPICMD2, SPI_SPICMD2_CLEN) + 1;
if(getWLen >= SPI_MAX_WORD_LEN)
{
return (CSL_ESYS_INVPARAMS);
}
/* Write Word length set by the user */
while(bufIndex < bufLen)
{
/* Write to registers more then 16 bit word length */
if(getWLen == 16)
{
CSL_SPI_REGS->SPIDR2 = writeBuffer[bufIndex];
CSL_SPI_REGS->SPIDR1 = 0x0000;
bufIndex ++;
}
/* Write to register less then or equal to 16 bit word length */
else if(getWLen == 8)
{
CSL_SPI_REGS->SPIDR2 = (Uint16)(writeBuffer[bufIndex] << 0x08);
CSL_SPI_REGS->SPIDR1 = 0x0000;
bufIndex++;
}
/* Set command for Writting to registers */
CSL_FINS(CSL_SPI_REGS->SPICMD2, SPI_SPICMD2_CMD, SPI_WRITE_CMD);
for(delay = 0; delay < 100; delay++);
do
{
spiStatusReg = CSL_SPI_REGS->SPISTAT1;
spiBusyStatus = (spiStatusReg & CSL_SPI_SPISTAT1_BSY_MASK);
spiWcStaus = (spiStatusReg & CSL_SPI_SPISTAT1_CC_MASK);
}while((spiBusyStatus == CSL_SPI_SPISTAT1_BSY_BUSY) &&
(spiWcStaus != CSL_SPI_SPISTAT1_CC_MASK));
}
return (CSL_SOK);
}
void DMA_HwInit(void)
{
ioport volatile unsigned int *io_ptr;
Uint16 i;
/* In PCGCR LSW, set DMA0 CG to 0 for bringing DMA0 module out of idle */
CSL_FINS((*IDLE_PCGCRL_ADDR), IDLE_PCGCRL_DMA0_IDLE, 0);
/* In PCGCR MSW, set DMA1 CG, DMA2 CG and DMA3 CG to 0
* for bringing the DMA1, DMA2, DMA3 modules out of idle */
CSL_FINS((*IDLE_PCGCRM_ADDR), IDLE_PCGCRM_DMA1_CG, 0);
CSL_FINS((*IDLE_PCGCRM_ADDR), IDLE_PCGCRM_DMA2_CG, 0);
CSL_FINS((*IDLE_PCGCRM_ADDR), IDLE_PCGCRM_DMA3_CG, 0);
/* Configure the Peripheral Software Reset Counter Register */
CSL_FINS((*PER_RSTCOUNT_ADDR), PER_RSTCOUNT, 0x20); //jb changed to 0x20
/* Configure the Peripheral Reset Control Register */
CSL_FINS((*PER_RESET_ADDR), PER_RESET_RESETEN_DMA, 1);
/* Give some delay after reset */
for (i=0; i<100; i++);
/* Clear the IFR of DMA */
io_ptr = (ioport volatile unsigned int*)(DMA_IFR_ADDR);
*io_ptr = DMA_IFR_RESET_VAL;
/* Enable interrupts for DMA module */
CSL_FINS((*CPU_IER0_ADDR), CPUIER0_DMAINT_ENABLE, 1);
io_ptr = (ioport volatile unsigned int*)(DMA_IMR_ADDR);
*io_ptr = DMA_IMR_VAL;
}
/** ===========================================================================
* @n@b SPI_read
*
* @b Description
* @n This function Read data form specified device.
*
* @b Arguments
* @verbatim
hSpi Pointer to handler
readBuff Pointer to the read buffer.
buffLen Maximum read buffer size.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Read successful
* @li CSL_ESYS_BADHANDLE - Invalid handle
*
* <b> Pre Condition </b>
* @n This function can call by SPI_dataTransaction function.
*
* <b> Post Condition </b>
* @n SPI_deInit can be call after this function call.
*
* @b Modifies
* @n
*
* @b Example
* @verbatim
CSL_SpiHandle hSpi
Uint16 readBuff[size];
Uint16 buffLen;
CSL_status status;
status = SPI_read(hSpi,&readBuff, buffLen);
@endverbatim
* ===========================================================================
*/
CSL_Status SPI_read (CSL_SpiHandle hSpi,
Uint16 *readBuffer,
Uint16 bufLen)
{
Int16 getWLen;
volatile Uint16 bufIndex;
Int16 spiStatusReg;
volatile Int16 spiBusyStatus;
volatile Int16 spiWcStaus;
volatile Uint16 delay;
bufIndex = 0;
if((NULL == readBuffer) || (0 == bufLen))
{
return (CSL_ESYS_INVPARAMS);
}
/* Read the word length form the register */
getWLen = CSL_FEXT(CSL_SPI_REGS->SPICR2, SPI_SPICR2_WLEN) + 1;
if(getWLen >= SPI_MAX_WORD_LEN)
{
return (CSL_ESYS_INVPARAMS);
}
/* Read Word length set by the user */
while(bufIndex < bufLen)
{
/* Set command for reading buffer */
CSL_FINS(CSL_SPI_REGS->SPICR2, SPI_SPICR2_CMD,
CSL_SPI_SPICR2_CMD_READ);
for(delay = 0; delay < 100; delay++);
do
{
spiStatusReg = CSL_SPI_REGS->SPISR1;
spiBusyStatus = (spiStatusReg & CSL_SPI_SPISR1_BSY_MASK);
spiWcStaus = (spiStatusReg & CSL_SPI_SPISR1_WC_MASK);
}while((spiBusyStatus == CSL_SPI_SPISR1_BSY_MASK) &&
(spiWcStaus != CSL_SPI_SPISR1_WC_MASK));
if(getWLen == 16)
{
//printf("value in reg before read = %d, in reg 2 = %d\n",(Int16) CSL_SPI_REGS->SPIDR1, (Int16) CSL_SPI_REGS->SPIDR2);
readBuffer[bufIndex] = CSL_SPI_REGS->SPIDR1;
bufIndex++;
}
else if(getWLen == 8)
{
readBuffer[bufIndex] = (CSL_SPI_REGS->SPIDR1 & 0xFF);
bufIndex++;
}
}
return (CSL_SOK);
}
CSL_Status SAR_GPODirSet (
CSL_SarHandleObj *hSar,
CSL_SarGPOPinSel Index,
CSL_SarGPODir dir
)
{
if(NULL == hSar)
{
return CSL_ESYS_BADHANDLE;
}
if(CSL_SAR_GPO_IN != dir && CSL_SAR_GPO_OUT != dir)
{
return CSL_ESYS_INVPARAMS;
}
switch(Index)
{
case CSL_SAR_GPO_0:
CSL_FINS (hSar->baseAddr->SARGPOCTRL,ANACTRL_SARGPOCTRL_GPO0EN, dir);
break;
case CSL_SAR_GPO_1:
CSL_FINS (hSar->baseAddr->SARGPOCTRL,ANACTRL_SARGPOCTRL_GPO1EN, dir);
break;
case CSL_SAR_GPO_2:
CSL_FINS (hSar->baseAddr->SARGPOCTRL, ANACTRL_SARGPOCTRL_GPO2EN, dir);
break;
case CSL_SAR_GPO_3:
CSL_FINS (hSar->baseAddr->SARGPOCTRL, ANACTRL_SARGPOCTRL_GPO3EN, dir);
break;
default:
return CSL_ESYS_INVPARAMS;
}
return CSL_SOK;
}
/** ===========================================================================
* @n@b LCD_init
*
* @b Description
* @n This is the initialization function for the LCD CSL. The function
* must be called before calling any other API from this CSL. This
* function is for enabling the clock to the LCD Controller.
* Currently, the function just return status CSL_SOK. as of now no
* checking is done inside the definition of function , but in near
* future it can be implemented.
*
* @b Arguments
* @verbatim
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Always returns
*
* <b> Pre Condition </b>
* @n This must be first API to use LCDC module.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_status status;
status = LCD_init();
@endverbatim
* ===========================================================================
*/
CSL_Status LCD_init(void)
{
/*enable the corresponding LCD clock from PCGCR Registers*/
CSL_FINST(CSL_SYSCTRL_REGS->PCGCR2, SYS_PCGCR2_LCDCG, ACTIVE);
/* set the reset clock cycle */
CSL_FINS(CSL_SYSCTRL_REGS->PSRCR,
SYS_PSRCR_COUNT, CSL_LCD_RESET_CLOCK_CYCLE);
CSL_FINST(CSL_SYSCTRL_REGS->PRCR, SYS_PRCR_PG4_RST, RST);
return CSL_SOK;
}
static void Qmss_internaldownloadFirmware (Qmss_PdspId pdspId, void *image, uint32_t size)
{
uint32_t i, count;
volatile uint32_t enable;
uint32_t *data = (uint32_t *) image;
/* Reset the PDSP */
CSL_FINS (qmssLObj.qmPdspCtrlReg[pdspId]->PDSP_CONTROL_REG, PDSP_PDSP_CONTROL_REG_PDSP_ENABLE, 0);
/* Confirm PDSP has halted */
do
{
enable = CSL_FEXT (qmssLObj.qmPdspCtrlReg[pdspId]->PDSP_CONTROL_REG, PDSP_PDSP_CONTROL_REG_PDSP_STATE);
}while (enable);
count = size / 4;
/* Download the firmware */
for(i = 0; i < count; i++)
qmssLObj.qmPdspIRamReg[pdspId][i] = data[i];
/* Use the command register to sync the PDSP */
*qmssLObj.qmPdspCmdReg[pdspId] = 0xFFFFFFFF;
/* Wait to the memory write to land */
for(i = 0; i < 20000 && *qmssLObj.qmPdspCmdReg[pdspId] != 0xFFFFFFFF; i++);
/* Reset program counter to zero */
CSL_FINS (qmssLObj.qmPdspCtrlReg[pdspId]->PDSP_CONTROL_REG, PDSP_PDSP_CONTROL_REG_PCOUNTER_RST_VAL, 0);
/* Set soft reset to zero to load the program counter */
CSL_FINS (qmssLObj.qmPdspCtrlReg[pdspId]->PDSP_CONTROL_REG, PDSP_PDSP_CONTROL_REG_SOFT_RST_N, 0);
/* Enable the PDSP */
CSL_FINS (qmssLObj.qmPdspCtrlReg[pdspId]->PDSP_CONTROL_REG, PDSP_PDSP_CONTROL_REG_PDSP_ENABLE, 1);
/* Wait for the command register to clear */
while (*qmssLObj.qmPdspCmdReg[pdspId]);
return;
}
static void LOCAL_exampleInit(Uint8 pruNum)
{
Uint32 i;
Uint32 *pruDataMem;
// Turn on the EDMA CC and TCs
DEVICE_LPSCTransition(CSL_PSC_0, CSL_PSC_CC0, 0, CSL_PSC_MDCTL_NEXT_ENABLE);
DEVICE_LPSCTransition(CSL_PSC_0, CSL_PSC_TC0, 0, CSL_PSC_MDCTL_NEXT_ENABLE);
DEVICE_LPSCTransition(CSL_PSC_0, CSL_PSC_TC1, 0, CSL_PSC_MDCTL_NEXT_ENABLE);
// Initialize memory pointer
if (pruNum == 0)
{
pruDataMem = (Uint32 *) PRU0_DATA_RAM_START;
}
else if (pruNum == 1)
{
pruDataMem = (Uint32 *) PRU1_DATA_RAM_START;
}
// Put src and dst addresses into PRU data memory so PRU code can read them
pruDataMem[0] = (Uint32) srcBuf;
pruDataMem[1] = (Uint32) dstBuf;
// Init src and dst buffers
for (i = 0; i < sizeof(srcBuf); i++)
{
srcBuf[i] = rand() & 0xFF;
dstBuf[i] = 0;
}
// Clear EDMA CC0 interrupt
CSL_FINST(intcRegs->EVTCLR[0], DSPINTC_EVTCLR_EC8, SET);
// Connect the EDMA CC0 event to the DSP interrupt 12
CSL_FINS(intcRegs->INTMUX3, DSPINTC_INTMUX3_INTSEL12, EDMA3_CC0_INT1);
// Set ISTP to point to the vector table address
ISTP = (Uint32)intcVectorTable;
// Clear all interrupts, bits 4 thru 15
ICR = 0xFFF0;
// Enable the bits for non maskable interrupt 12 and NMIE
IER = 0x1002;
// Enable interrupts, set GIE bit
_enable_interrupts();
}
/** ===========================================================================
* @n@b SPI_init
*
* @b Description
* @n This function intialize and activate the SPI module
*
* @b Arguments
* @verbatim
None
@endverbatim
*
* <b> Return Value </b> CSL_SOK
* @n Return value CSL_SOK for success
*
* <b> Pre Condition </b>
* @n This functionality has to call before any function call.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
void
result = SPI_init();
...
@endverbatim
* ===========================================================================
*/
CSL_Status SPI_init(void)
{
volatile Uint16 delay;
ioport volatile CSL_SysRegs *sysRegs;
sysRegs = (CSL_SysRegs *)CSL_SYSCTRL_REGS;
CSL_FINS(sysRegs->PCGCR1, SYS_PCGCR1_SPICG, CSL_SYS_PCGCR1_SPICG_ACTIVE);
/* Value of 'Reset Counter' */
CSL_FINS(sysRegs->PSRCR, SYS_PSRCR_COUNT, 0x20);
CSL_FINS(sysRegs->PRCR, SYS_PRCR_PG4_RST, CSL_SYS_PRCR_PG4_RST_RST);
for(delay = 0; delay < 100; delay++);
#ifdef VC5505_EZDSP
CSL_FINS(sysRegs->EBSR, SYS_EBSR_PPMODE, CSL_SYS_EBSR_PPMODE_MODE6);
#else
CSL_FINS(sysRegs->EBSR, SYS_EBSR_PPMODE, CSL_SYS_EBSR_PPMODE_MODE5);
#endif
return(CSL_SOK);
}
/** ===========================================================================
* @n@b GPT_start
*
* @b Description
* @n This function start to load value from period register to
* count down register.
*
* @b Arguments
* @verbatim
hGpt Handle to the GPT
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Close successful
* @li CSL_ESYS_BADHANDLE - Invalid handle
*
* <b> Pre Condition </b>
* @n GPT_config() must be called before this function call.
*
* <b> Post Condition </b>
* @n After calling this function GPT_stop() function can call to
* stop loading from period register to countdown register.
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_status status;
CSL_Handle hGpt;
...
hgpt = GPT_config(hGpt, &hwConfig);
status = GPT_start(hgpt);
@endverbatim
* ===========================================================================
*/
CSL_Status GPT_start(CSL_Handle hGpt)
{
CSL_TimRegsOvly regPtr;
if(NULL == hGpt)
{
return (CSL_ESYS_BADHANDLE);
}
regPtr = hGpt->regs;
/* Enable the start timer */
CSL_FINS(regPtr->TCR, TIM_TCR_START, CSL_TIM_TCR_START_MASK);
return (CSL_SOK);
}
/** ===========================================================================
* @n@b SPI_deInit
*
* @b Description
* @n This function unintialize and activate the SPI module
*
* @b Arguments
* @verbatim
void No parameter
@endverbatim
*
* <b> Return Value </b> CSL_SOK
* @n Return value CSL_SOK for success
*
* <b> Pre Condition </b>
* @n This function call call after SPI_init function.
*
* <b> Post Condition </b>
* @n SPI_close function can be call after this function call.
*
* @b Modifies
* @n 1. Set the register to activate SPI module
* @n 2.
*
* @b Example
* @verbatim
void
result = SPI_deInit();
...
@endverbatim
* ===========================================================================
*/
CSL_Status SPI_deInit(void)
{
ioport volatile CSL_SysRegs *sysRegs;
if(TRUE == SPI_Instance.configured)
{
SPI_Instance.configured = FALSE;
}
sysRegs = (CSL_SysRegs *)CSL_SYSCTRL_REGS;
/*Disable the SPI clock */
CSL_FINS(sysRegs->PCGCR1, SYS_PCGCR1_SPICG, CSL_SYS_PCGCR1_SPICG_DISABLED);
return (CSL_SOK);
}
/** ===========================================================================
* @n@b GPT_stop
*
* @b Description
* @n This function stop to load value from period register to
* count down register.
*
* @b Arguments
* @verbatim
hGpt Handle to the GPT
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Close successful
* @li CSL_ESYS_BADHANDLE - Invalid handle
*
* <b> Pre Condition </b>
* @n GPT_config() must be called before this function call.
*
* <b> Post Condition </b>
* @n After calling this function GPT_close() API should call to close
* gpt operation.
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_status status;
CSL_Handle hGpt;
...
status = GPT_start(hgpt);
status = GPT_stop(hgpt);
@endverbatim
* ===========================================================================
*/
CSL_Status GPT_stop(CSL_Handle hGpt)
{
CSL_TimRegsOvly regPtr;
if(NULL == hGpt)
{
return (CSL_ESYS_BADHANDLE);
}
regPtr = hGpt->regs;
/* Stop the start bit */
CSL_FINS(regPtr->TCR, TIM_TCR_START, CSL_TIM_TCR_START_RESETVAL);
/* Disable the auto reload bit */
//CSL_FINS(regPtr->TCR, TIM_TCR_AUTORELOAD, CSL_TIM_TCR_AUTORELOAD_DISABLE);
return (CSL_SOK);
}
/** ===========================================================================
* @n@b GPT_stop
*
* @b Description
* @n This function stop to load value from counter register to
* kick register.
*
* @b Arguments
* @verbatim
hWdt Handle to the WDT
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Close successful
* @li CSL_ESYS_BADHANDLE - Invalid handle
*
* <b> Pre Condition </b>
* @n GPT_start() must be called before this function call.
*
* <b> Post Condition </b>
* @n After calling this function WDTIM_close() API should call to close
* WDT operation.
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_status status;
CSL_WdtHandle hWdt;
...
status = WDTIM_start(hWdt);
status = WDTIM_stop(hWdt);
@endverbatim
* ===========================================================================
*/
CSL_Status WDTIM_stop(CSL_WdtHandle hWdt)
{
CSL_WdtRegsOvly regs;
if(NULL == hWdt)
{
return (CSL_ESYS_BADHANDLE);
}
regs = hWdt->hwRegs;
/* Set the Disable lock register sequence number to unlock */
regs->WDENLOK = CSl_WDT_WDENLOK_FIRST_SEQ;
regs->WDENLOK = CSl_WDT_WDENLOK_SECOND_SEQ;
regs->WDENLOK = CSl_WDT_WDENLOK_THIRD_SEQ;
/* Set the zero'th bit to 1 for Disable register */
CSL_FINS(regs->WDEN, WDT_WDEN_EN, CSL_WDT_WDEN_EN_DISABLE);
return (CSL_SOK);
}
/** ===========================================================================
* @n@b WDTIM_open
*
* @b Description
* @n This is the initialization function for the GPT CSL. The function
* must be called before calling any other API from this CSL. This
* function is idem-potent. Currently, the function just returns handler
* to application.
*
* @b Arguments
* @verbatim
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Always returns
*
* CSL_Handle
* Pointer to the object structure.
* <b> Pre Condition </b>
* @n This should be call first before calling any other WDT Function.
*
* <b> Post Condition </b>
* @n The status is updated in the status variable. If status
* returned is
* @li CSL_SOK - Valid GPT handle is returned
* @li CSL_ESYS_INVPARAMS - Invalid parameter
*
* @b Modifies
* @n 1. The status variable
* @n 2. The object structure handler.
*
* @b Example
* @verbatim
CSL_WdtHandle hWdt;
WDT_Instance wdtNum;
CSL_WdtObj wdtObj;
CSL_Status status;
....
....
instance = WDT_INST_0.
hWdt = WDTIM_open(WDT_INST_0, &wdtObj, &status);
@endverbatim
* ===========================================================================
*/
CSL_WdtHandle WDTIM_open(WDT_Instance wdtNum,
CSL_WdtObj *wdtObj,
CSL_Status *status)
{
CSL_WdtHandle hWdt;
ioport volatile CSL_SysRegs *sysRegs;
*status = CSL_SOK;
hWdt = NULL;
if(NULL == wdtObj)
{
*status = CSL_ESYS_BADHANDLE;
return (hWdt);
}
if((wdtNum < WDT_INST_0) || (wdtNum >= WDT_INST_INVALID))
{
*status = CSL_ESYS_INVPARAMS;
return (hWdt);
}
hWdt = wdtObj;
/* Set the system control register to enable WDT */
sysRegs = (CSL_SysRegs *)CSL_SYSCTRL_REGS;
switch(wdtNum)
{
case WDT_INST_0:
hWdt->wdtInstance = wdtNum;
hWdt->hwRegs = CSL_WDT_REGS;
CSL_FINS(sysRegs->PCGCR1, SYS_PCGCR1_TMR2CG,
CSL_SYS_PCGCR1_TMR2CG_ACTIVE);
break;
default:
*status = CSL_ESYS_INVPARAMS;
}
return (hWdt);
}
CSL_Status SAR_chanCycSet (
SAR_Handle hSar,
CSL_SarChanCyc cycSelect
)
{
if(NULL == hSar)
{
return CSL_ESYS_BADHANDLE;
}
if( (CSL_SAR_CONTINUOUS_CONVERSION != cycSelect
&& CSL_SAR_SINGLE_CONVERSION != cycSelect))
{
return CSL_ESYS_INVPARAMS;
}
/* Configuring SAR singleCyc operation */
CSL_FINS (hSar->baseAddr->SARCTRL, ANACTRL_SARCTRL_SNGCYC, cycSelect);
return CSL_SOK;
}
CSL_Status CSL_edmaHwChannelSetup(
/** pointer to the object that holds reference to the channel
* instance of the Specified DMA */
CSL_EdmaChanHandle hCh,
/** pointer to the setup structure */
CSL_EdmaHwChannelSetup *setup
)
{
if (hCh==NULL)
return CSL_ESYS_BADHANDLE;
if (setup==NULL)
return CSL_ESYS_INVPARAMS;
CSL_edmaChannelSetEvtQue(hCh,setup->que);
if (hCh->chaNum < CSL_EDMA_NUM_DMACH) {
#if CSL_EDMA_CHMAPEXIST
CSL_FINS(hCh->ccregs->DCHMAP[hCh->chaNum], EDMACC_DCHMAP_PAENTRY,setup->paramEntry);
#endif
} else
hCh->ccregs->QCHMAP[hCh->chaNum-CSL_EDMA_NUM_DMACH] = CSL_FMK(EDMACC_QCHMAP_PAENTRY,setup->paramEntry) | CSL_FMK(EDMACC_QCHMAP_TRWORD,setup->triggerWord);
return CSL_SOK;
}
/** ============================================================================
* @n@b I2C_config
*
* @b Description
* @n Configures the I2C module. Using this function application can pass the
* value of the each register to be configured.
*
* @b Arguments
* @verbatim
i2cConfig I2C config structure pointer
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Returned for success
* @li CSL_ESYS_INVPARAMS - Invalid parameter
*
* <b> Pre Condition </b>
* @n I2C_init should be called successfully
*
* <b> Post Condition </b>
* @n Configures the I2C registers
*
* @b Modifies
* @n I2C registers
*
* @b Example
* @verbatim
CSL_Status status;
CSL_I2cConfig i2cConfig;
i2cConfig.icoar = CSL_I2C_ICOAR_DEFVAL;
i2cConfig.icimr = CSL_I2C_ICIMR_DEFVAL;
i2cConfig.icclkl = CSL_I2C_ICCLK_DEFVAL;
i2cConfig.icclkh = CSL_I2C_ICCLK_DEFVAL;
i2cConfig.iccnt = CSL_I2C_DATA_SIZE;
i2cConfig.icsar = CSL_I2C_ICSAR_DEFVAL;
i2cConfig.icmdr = CSL_I2C_ICMDR_WRITE_DEFVAL;
i2cConfig.icemdr = CSL_I2C_ICEMDR_DEFVAL;
i2cConfig.icpsc = CSL_I2C_ICPSC_DEFVAL;
status = I2C_init(CSL_I2C0);
....
status = I2C_config(&i2cConfig);
@endverbatim
* ============================================================================
*/
CSL_Status I2C_config(CSL_I2cConfig *i2cConfig)
{
if(i2cConfig != NULL)
{
/* Configure I2C Own Address register */
CSL_FINS(i2cHandle->i2cRegs->ICOAR, I2C_ICOAR_OADDR,
i2cConfig->icoar);
/* Configure I2C interrupt mask register */
CSL_FINSR(i2cHandle->i2cRegs->ICIMR, CSL_I2C_ICIMR_AAS_SHIFT,
CSL_I2C_ICIMR_AL_SHIFT, i2cConfig->icimr);
/* Clear I2C interrupt status register */
i2cHandle->i2cRegs->ICSTR = CSL_I2C_ICSTR_RESET_VALUE;
/* Configure I2C clock low register */
CSL_FINS(i2cHandle->i2cRegs->ICCLKL, I2C_ICCLKL_ICCL,
i2cConfig->icclkl);
/* Configure I2C clock high register */
CSL_FINS(i2cHandle->i2cRegs->ICCLKH, I2C_ICCLKH_ICCH,
i2cConfig->icclkh);
/* Configure I2C count register */
CSL_FINS(i2cHandle->i2cRegs->ICCNT, I2C_ICCNT_ICDC, i2cConfig->iccnt);
/* Configure I2C slave address register */
CSL_FINS(i2cHandle->i2cRegs->ICSAR, I2C_ICSAR_SADDR, i2cConfig->icsar);
/* Configure I2C prescaler register */
CSL_FINS(i2cHandle->i2cRegs->ICPSC, I2C_ICPSC_IPSC, i2cConfig->icpsc);
/* Configure I2C extended mode address register */
CSL_FINSR(i2cHandle->i2cRegs->ICEMDR, CSL_I2C_ICEMDR_IGNACK_SHIFT,
CSL_I2C_ICEMDR_BCM_SHIFT, i2cConfig->icemdr);
/* Configure I2C mode address register */
i2cHandle->i2cRegs->ICMDR = i2cConfig->icmdr;
}
else
{
return(CSL_ESYS_INVPARAMS);
}
return(CSL_SOK);
}
/** ============================================================================
* @n@b I2C_init
*
* @b Description
* @n Initializes the I2C CSL module
*
* @b Arguments
* @verbatim
instanceNum I2C Hardware instance number
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Returned for success
* @li CSL_ESYS_INVPARAMS - Invalid parameter
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n Initializes I2C module
*
* @b Modifies
* @n I2C Object structure
*
* @b Example
* @verbatim
CSL_Status status;
status = I2C_init(CSL_I2C0);
@endverbatim
* ============================================================================
*/
CSL_Status I2C_init(Uint16 instanceNum)
{
CSL_Status status;
volatile Uint16 looper;
status = CSL_SOK;
switch(instanceNum)
{
case CSL_I2C0 :
i2cHandle = &gI2cObj[CSL_I2C0];
i2cHandle->i2cRegs = CSL_I2C_0_REGS;
i2cHandle->sysCtrlRegs = CSL_SYSCTRL_REGS;
/* Enable I2C module in Idle PCGCR */
CSL_FINST(i2cHandle->sysCtrlRegs->PCGCR1,
SYS_PCGCR1_I2CCG, ACTIVE);
/* Reset I2C module */
CSL_FINS(i2cHandle->sysCtrlRegs->PSRCR, SYS_PSRCR_COUNT,
CSL_I2C_RESET_COUNT_VAL);
CSL_FINST(i2cHandle->sysCtrlRegs->PRCR, SYS_PRCR_I2C_RST, RST);
/* Give some delay for the device to reset */
for(looper = 0; looper < CSL_I2C_RESET_DELAY; looper++)
{;}
break;
default :
status = CSL_ESYS_INVPARAMS;
break;
}
return(status);
}
/** ===========================================================================
* @n@b WDTIM_close
*
* @b Description
* @n This function close WDT operation.
*
* @b Arguments
* @verbatim
hWdt Handle to the WDT
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Close successful
* @li CSL_ESYS_BADHANDLE - Invalid handle
*
* <b> Pre Condition </b>
* @n WDTIM_open() must be called before this function call.
*
* <b> Post Condition </b>
* @n After calling this function no other function can call.
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_status status;
CSL_WdtHandle hWdt;
...
hWdt = WDTIM_open(WDT_INST_0, &wdtObj, &status);
status = WDTIM_close(hWdt);
@endverbatim
* ===========================================================================
*/
CSL_Status WDTIM_close(CSL_WdtHandle hWdt)
{
ioport volatile CSL_SysRegs *sysRegs;
if(NULL == hWdt)
{
return (CSL_ESYS_BADHANDLE);
}
sysRegs = (CSL_SysRegs *)CSL_SYSCTRL_REGS;
switch(hWdt->wdtInstance)
{
case WDT_INST_0:
CSL_FINS(sysRegs->PCGCR1, SYS_PCGCR1_TMR2CG,
CSL_SYS_PCGCR1_TMR2CG_DISABLED);
break;
}
hWdt->hwRegs = NULL;
hWdt = NULL;
return (CSL_SOK);
}
/** ===========================================================================
* @n@b LCD_setup
*
* @b Description
* @n It configures the LCDC register specific to LIDD controller to draw
* the images or text on LCD panel.
*
* @b Arguments
* @verbatim
hLcdc Handle to the LCDC.
setup Pointer to LCDC setup structure.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Hardware setup successful
* @li CSL_ESYS_BADHANDLE - Invalid handle
* @li CSL_ESYS_INVPARAMS - setup Parameter is invalid.
*
* <b> Pre Condition </b>
* @n LCD_open() API should be called before this.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n LCDC Registers will be populated.
*
* @b Example
* @verbatim
Uint16 instanceNum;
CSL_status status;
CSL_LcdcObj pLcdcObj
CSL_LcdcHandle hLcdc;
CSL_LcdcHwSetup setup;
...
CSL_LcdcConfigLidd configLIDD;
CSL_LcdcLiddTiming timingCs0LIDD;
CSL_LcdcLiddTiming timingCs1LIDD;
.........\\\\\\\\\\\\\ SETUP for LIDD Controller
configLIDD.clkDiv = 0x3;
configLIDD.fdoneIntEn = CSL_LCDC_LIDD_FDONE_DISABLE ;
configLIDD.dmaCs0Cs1 = CSL_LCDC_LIDD_CS0;
configLIDD.dmaEnable = CSL_LCDC_LIDD_DMA_DISABLE;
configLIDD.polControl = 0x0000;
configLIDD.modeSel = CSL_LCDC_LIDD_ASYNC_MPU80;
timingCs0LIDD.wSu = 0x1F;
timingCs0LIDD.wStrobe = 0x3F ;
timingCs0LIDD.wHold = 0x0F;
timingCs0LIDD.rSu = 0x1F;
timingCs0LIDD.rStrobe = 0x3F;
timingCs0LIDD.rHold = 0x0F;
timingCs0LIDD.ta = 0x01;
timingCs1LIDD.wSu = 0x1F;
timingCs1LIDD.wStrobe = 0x3F ;
timingCs1LIDD.wHold = 0x0F;
timingCs1LIDD.rSu = 0x1F;
timingCs1LIDD.rStrobe = 0x3F;
timingCs1LIDD.rHold = 0x0F;
timingCs1LIDD.ta = 0x01;
setup.config = configLIDD;
setup.useCs1 = CSL_LCDC_LIDD_NOT_USE_CS1;
setup.timingCs0 = timingCs0LIDD;
setup.extendSetup = NULL;
||||||||||||*******************************************************||||||||||||
instanceNum = CSL_LCDC_INSTANCE_0
hLcdc = LCD_open(instanceNum, &pLcdcObj, &status);
status = LCD_setup(hLcdc, &setup);
...
@endverbatim
* ===========================================================================
*/
CSL_Status LCD_setup (
CSL_LcdcHandle hLcdc,
CSL_LcdcHwSetup* setup )
{
Uint16 tempVar;
if((hLcdc != NULL) && (setup != NULL))
{
/* passed parameters are ok */
}
else
{
if(hLcdc == NULL)
{
return CSL_ESYS_BADHANDLE;
}
else
{
return CSL_ESYS_INVPARAMS;
}
}
/* clear the all data of the status register */
CSL_FINS(hLcdc->regs->LCDSR, LCDC_LCDSR_EOF1, CSL_LCD_ENABLE);
CSL_FINS(hLcdc->regs->LCDSR, LCDC_LCDSR_EOF0, CSL_LCD_ENABLE);
CSL_FINS(hLcdc->regs->LCDSR, LCDC_LCDSR_PL, CSL_LCD_ENABLE);
CSL_FINS(hLcdc->regs->LCDSR, LCDC_LCDSR_FUF, CSL_LCD_ENABLE);
CSL_FINS(hLcdc->regs->LCDSR, LCDC_LCDSR_ABC, CSL_LCD_ENABLE);
CSL_FINS(hLcdc->regs->LCDSR, LCDC_LCDSR_SYNC, CSL_LCD_ENABLE);
CSL_FINS(hLcdc->regs->LCDSR, LCDC_LCDSR_DONE, CSL_LCD_ENABLE);
/* set the lcd controller mode to LIDD */
CSL_FINST (hLcdc->regs->LCDCR, LCDC_LCDCR_MODESEL, LIDD);
/* configure the registers required for LIDD controller */
/* CSL_FINST (hLcdc->regs->LCDRASTCR0,
LCDC_LCDRASTCR0_LCDEN, DISABLE); */
/* configure LIDD control register */
tempVar = (setup->config).polControl;
CSL_FINS (hLcdc->regs->LCDLIDDCR, LCDC_LCDLIDDCR_DONE_INT_EN,
(setup->config).fdoneIntEn);
CSL_FINS (hLcdc->regs->LCDLIDDCR, LCDC_LCDLIDDCR_LIDD_MODE_SEL,
(setup->config).modeSel);
CSL_FINS (hLcdc->regs->LCDCR, LCDC_LCDCR_CLKDIV,
(setup->config).clkDiv);
CSL_FINS (hLcdc->regs->LCDLIDDCR, LCDC_LCDLIDDCR_DMA_CS0_CS1,
(setup->config).dmaCs0Cs1);
hLcdc->regs->LCDLIDDCR &= ~CSL_LCDC_LCDLIDDCR_CS1_E1_POL_MASK;
hLcdc->regs->LCDLIDDCR &= ~CSL_LCDC_LCDLIDDCR_CS0_E0_POL_MASK;
hLcdc->regs->LCDLIDDCR &= ~CSL_LCDC_LCDLIDDCR_WS_DIR_POL_MASK;
hLcdc->regs->LCDLIDDCR &= ~CSL_LCDC_LCDLIDDCR_RS_EN_POL_MASK;
hLcdc->regs->LCDLIDDCR &= ~CSL_LCDC_LCDLIDDCR_ALEPOL_MASK;
hLcdc->regs->LCDLIDDCR |=
(tempVar << CSL_LCDC_LCDLIDDCR_ALEPOL_SHIFT);
CSL_FINS (hLcdc->regs->LCDLIDDCR, LCDC_LCDLIDDCR_LIDD_DMA_EN,
(setup->config).dmaEnable);
/* configure LIDD chip selct configuration register */
if(CSL_LCDC_LIDD_NOT_USE_CS1 == (setup->useCs1))
{
/* configure LIDD CS0 configuration register */
tempVar = (setup->timingCs0).rSu;
CSL_FINS (hLcdc->regs->LCDLIDDCS0CONFIG0,
LCDC_LCDLIDDCS0CONFIG0_R_STROBE,
(setup->timingCs0).rStrobe);
CSL_FINS (hLcdc->regs->LCDLIDDCS0CONFIG0,
LCDC_LCDLIDDCS0CONFIG0_R_HOLD,
(setup->timingCs0).rHold);
CSL_FINS (hLcdc->regs->LCDLIDDCS0CONFIG0,
LCDC_LCDLIDDCS0CONFIG0_TA,
(setup->timingCs0).ta);
if(tempVar >= 16)
{
tempVar = tempVar - 15 ;
tempVar = tempVar >> 4;
hLcdc->regs->LCDLIDDCS0CONFIG0 |=
CSL_LCDC_LCDLIDDCS0CONFIG0_R_SU0_MASK;
CSL_FINS (hLcdc->regs->LCDLIDDCS0CONFIG1,
LCDC_LCDLIDDCS0CONFIG1_R_SU1, tempVar);
}
