/** ============================================================================
* @n@b MDIO_open()
*
* @b Description
* @n Opens the MDIO peripheral and start searching for a PHY device.
*
* It is assumed that the MDIO module is reset prior to calling this
* function.
*
* @b Arguments
* @verbatim
mdioModeFlags mode flags pof MII
@endverbatim
*
* <b> Return Value </b> Handle to the opened MDIO instance
*
* <b> Pre Condition </b>
* @n The MDIO module must be reset prior to calling this function.
*
* <b> Post Condition </b>
* @n Opens the MDIO peripheral and start searching for a PHY device.
*
* @b Example:
* @verbatim
#define MDIO_MODEFLG_FD1000 0x0020
#define MDIO_MODEFLG_EXTLOOPBACK 0x0100
Uint32 mdioModeFlags = MDIO_MODEFLG_FD1000 | MDIO_MODEFLG_LOOPBACK;
MDIO_open ( mdioModeFlags );
@endverbatim
* ============================================================================
*/
Handle MDIO_open( Uint32 mdioModeFlags )
{
/*
* Note: In a multi-instance environment, we'd have to allocate "localDev"
*/
static MDIO_Device localDev;
/* Find out what interface we are working with */
//macsel = CSL_FEXT(DEV_REGS->DEVSTAT, DEV_DEVSTAT_MACSEL);
/* Get the mode flags from the user - clear our reserved flag */
localDev.ModeFlags = mdioModeFlags & ~MDIO_MODEFLG_NWAYACTIVE;
/* Setup the MDIO state machine */
MDIO_initStateMachine( &localDev );
/* Enable MDIO and setup divider */
MDIO_REGS->CONTROL = CSL_FMKT(MDIO_CONTROL_ENABLE,YES) |
CSL_FMK(MDIO_CONTROL_CLKDIV,VBUSCLK) ;
/* We're done for now - all the rest is done via MDIO_event() */
return( &localDev );
}
// Clock gating for unused peripherals
void ClockGating(void)
{
Uint16 pcgcr_value, clkstop_value;
// set PCGCR1
pcgcr_value = 0;
// clock gating SPI
pcgcr_value |= CSL_FMKT(SYS_PCGCR1_SPICG, DISABLED);
// clock gating SD/MMC
pcgcr_value |= CSL_FMKT(SYS_PCGCR1_MMCSD0CG, DISABLED);
pcgcr_value |= CSL_FMKT(SYS_PCGCR1_MMCSD0CG, DISABLED);
// clock stop request for UART
clkstop_value = CSL_FMKT(SYS_CLKSTOP_URTCLKSTPREQ, REQ);
// write to CLKSTOP
CSL_FSET(CSL_SYSCTRL_REGS->CLKSTOP, 15, 0, clkstop_value);
// wait for acknowledge
while (CSL_FEXT(CSL_SYSCTRL_REGS->CLKSTOP, SYS_CLKSTOP_URTCLKSTPACK)==0);
// clock gating UART
pcgcr_value |= CSL_FMKT(SYS_PCGCR1_UARTCG, DISABLED);
// clock stop request for EMIF
//clkstop_value = CSL_FMKT(SYS_CLKSTOP_EMFCLKSTPREQ, REQ);
// write to CLKSTOP
//CSL_FSET(CSL_SYSCTRL_REGS->CLKSTOP, 15, 0, clkstop_value);
// wait for acknowledge
//while (CSL_FEXT(CSL_SYSCTRL_REGS->CLKSTOP, SYS_CLKSTOP_EMFCLKSTPACK)==0);
// clock gating EMIF
//pcgcr_value |= CSL_FMKT(SYS_PCGCR1_EMIFCG, DISABLED);
// clock gating unused I2S (I2S 0, 1, 3)
pcgcr_value |= CSL_FMKT(SYS_PCGCR1_I2S0CG, DISABLED);
pcgcr_value |= CSL_FMKT(SYS_PCGCR1_I2S1CG, DISABLED);
pcgcr_value |= CSL_FMKT(SYS_PCGCR1_I2S3CG, DISABLED);
// clcok gating DMA0
pcgcr_value |= CSL_FMKT(SYS_PCGCR1_DMA0CG, DISABLED);
// clcok gating Timer 1
//pcgcr_value |= CSL_FMKT(SYS_PCGCR1_TMR1CG, DISABLED);
// clcok gating Timer 2
pcgcr_value |= CSL_FMKT(SYS_PCGCR1_TMR2CG, DISABLED);
// write to PCGCR1
CSL_FSET(CSL_SYSCTRL_REGS->PCGCR1, 15, 0, pcgcr_value);
// set PCGCR2
pcgcr_value = 0;
// clock gating LCD
pcgcr_value |= CSL_FMKT(SYS_PCGCR2_LCDCG, DISABLED);
// clcok gating DMA2
pcgcr_value |= CSL_FMKT(SYS_PCGCR2_DMA2CG, DISABLED);
// clcok gating DMA3
pcgcr_value |= CSL_FMKT(SYS_PCGCR2_DMA3CG, DISABLED);
// write to PCGCR2
CSL_FSET(CSL_SYSCTRL_REGS->PCGCR2, 15, 0, pcgcr_value);
return;
}
