static int
mii_read(struct local *l, int phy, int reg)
{
uint32_t ctl;
do {
ctl = CSR_READ(l, MIIADDR);
} while (ctl & 01);
ctl = (phy << 11) | (reg << 6) | (0 << 1); /* READ op */
CSR_WRITE(l, MIIADDR, ctl);
do {
ctl = CSR_READ(l, MIIADDR);
} while (ctl & 01);
return CSR_READ(l, MIIDATA);
}
unsigned long winbond_gettimeoffset (void)
{
unsigned long offset;
/* instead of the variable "tick", the constant TICK_CONST is used here.
* This way, the multiplication and divide are optimized away by the compiler
* if "LATCH" equals "TICK_CONST"
*/
offset = (unsigned long) ((LATCH - CSR_READ(TDR0) - 1)*TICK_CONST)/LATCH;
if ((offset < (TICK_CONST / 2)) && (CSR_READ(AIC_ISR)&(1<<INT_TINT0)))
offset += TICK_CONST;
return offset;
}
static int s3c4510b_putc(char c)
{
CSR_WRITE(DEBUG_TX_BUFF_BASE, c);
while(!(CSR_READ(DEBUG_CHK_STAT_BASE) & DEBUG_TX_DONE_CHECK_BIT));
if(c == '\n')
s3c4510b_putc('\r');
}
void
mii_write(struct local *l, int phy, int reg, int val)
{
uint32_t ctl;
do {
ctl = CSR_READ(l, MIIADDR);
} while (ctl & 01);
ctl = (phy << 11) | (reg << 6) | (1 << 1); /* WRITE op */
CSR_WRITE(l, MIIDATA, val);
}
void *
sme_init(unsigned tag, void *data)
{
struct local *l;
struct desc *txd, *rxd;
unsigned mac32, mac16, val, fdx;
uint8_t *en;
l = ALLOC(struct local, 32); /* desc alignment */
memset(l, 0, sizeof(struct local));
l->csr = DEVTOV(pcicfgread(tag, 0x1c)); /* BAR3 mem space, LE */
l->phy = 1; /* 9420 internal PHY */
en = data;
mac32 = CSR_READ(l, ADDRL);
mac16 = CSR_READ(l, ADDRH);
en[0] = mac32;
en[1] = mac32 >> 8;
en[2] = mac32 >> 16;
en[3] = mac32 >> 24;
en[4] = mac16;
en[5] = mac16 >> 8;
printf("MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
en[0], en[1], en[2], en[3], en[4], en[5]);
DPRINTF(("PHY %d (%04x.%04x)\n", l->phy,
mii_read(l, l->phy, 2), mii_read(l, l->phy, 3)));
mii_dealan(l, 5);
/* speed and duplexity can be seen in MII 31 */
val = mii_read(l, l->phy, 31);
fdx = !!(val & (1U << 4));
printf("%s", (val & (1U << 3)) ? "100Mbps" : "10Mbps");
if (fdx)
printf("-FDX");
printf("\n");
txd = &l->txd[0];
rxd = &l->rxd[0];
rxd[0].xd0 = htole32(R0_OWN);
rxd[0].xd1 = htole32(R1_RCH | FRAMESIZE);
rxd[0].xd2 = htole32(VTOPHYS(l->rxstore[0]));
rxd[0].xd3 = htole32(VTOPHYS(&rxd[1]));
rxd[1].xd0 = htole32(R0_OWN);
rxd[1].xd1 = htole32(R1_RER | FRAMESIZE);
rxd[1].xd2 = htole32(VTOPHYS(l->rxstore[1]));
/* R1_RER neglects xd3 */
l->tx = l->rx = 0;
wbinv(l, sizeof(struct local));
CSR_WRITE(l, TXDBASE, VTOPHYS(txd));
CSR_WRITE(l, RXDBASE, VTOPHYS(rxd));
val = MACCR_TXEN | MACCR_RXEN;
if (fdx)
val |= MACCR_FDPX;
CSR_WRITE(l, BUSMODE, 0);
CSR_WRITE(l, DMACCTL, DMACCTL_ST | DMACCTL_SR);
CSR_WRITE(l, MAC_CR, val); /* (FDX), Tx/Rx enable */
CSR_WRITE(l, RXPOLLD, 01); /* start receiving */
return l;
}
void winbond_watchdog_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
CSR_WRITE(WTCR, (CSR_READ(WTCR)&0xF7)|0x01);
}