static uint32_t cs_mem_readl(void *opaque, target_phys_addr_t addr) { CSState *s = opaque; uint32_t saddr, ret; saddr = addr >> 2; switch (saddr) { case 1: switch (CS_RAP(s)) { case 3: // Write only ret = 0; break; default: ret = s->dregs[CS_RAP(s)]; break; } trace_cs4231_mem_readl_dreg(CS_RAP(s), ret); break; default: ret = s->regs[saddr]; trace_cs4231_mem_readl_reg(saddr, ret); break; } return ret; }
static uint32_t cs_mem_readl(void *opaque, target_phys_addr_t addr) { CSState *s = opaque; uint32_t saddr, ret; saddr = (addr & CS_MAXADDR) >> 2; switch (saddr) { case 1: switch (CS_RAP(s)) { case 3: // Write only ret = 0; break; default: ret = s->dregs[CS_RAP(s)]; break; } DPRINTF("read dreg[%d]: 0x%8.8x\n", CS_RAP(s), ret); break; default: ret = s->regs[saddr]; DPRINTF("read reg[%d]: 0x%8.8x\n", saddr, ret); break; } return ret; }
static void cs_mem_write(void *opaque, target_phys_addr_t addr, uint64_t val, unsigned size) { CSState *s = opaque; uint32_t saddr; saddr = addr >> 2; trace_cs4231_mem_writel_reg(saddr, s->regs[saddr], val); switch (saddr) { case 1: trace_cs4231_mem_writel_dreg(CS_RAP(s), s->dregs[CS_RAP(s)], val); switch(CS_RAP(s)) { case 11: case 25: // Read only break; case 12: val &= 0x40; val |= CS_CDC_VER; // Codec version s->dregs[CS_RAP(s)] = val; break; default: s->dregs[CS_RAP(s)] = val; break; } break; case 2: // Read only break; case 4: if (val & 1) { cs_reset(&s->busdev.qdev); } val &= 0x7f; s->regs[saddr] = val; break; default: s->regs[saddr] = val; break; } }
static void cs_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) { CSState *s = opaque; uint32_t saddr; saddr = addr >> 2; DPRINTF("write reg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->regs[saddr], val); switch (saddr) { case 1: DPRINTF("write dreg[%d]: 0x%2.2x -> 0x%2.2x\n", CS_RAP(s), s->dregs[CS_RAP(s)], val); switch(CS_RAP(s)) { case 11: case 25: // Read only break; case 12: val &= 0x40; val |= CS_CDC_VER; // Codec version s->dregs[CS_RAP(s)] = val; break; default: s->dregs[CS_RAP(s)] = val; break; } break; case 2: // Read only break; case 4: if (val & 1) cs_reset(s); val &= 0x7f; s->regs[saddr] = val; break; default: s->regs[saddr] = val; break; } }