static void phy_dsr(cyg_vector_t vector, cyg_ucount32 count,
cyg_addrword_t data)
{
cyg_uint32 status;
struct eth_drv_sc *sc = (struct eth_drv_sc *) data;
cyg_uint32 address =
((struct tsec_eth_info *) sc->driver_private)->phyAddress;
// os_printf("PHY DSR");
status = phy_read_register(address, MII_PHY_IRQ_REG);
if (status & (MII_PHY_IRQ_LINK_CHANGE| MII_PHY_IRQ_DUPLEX_CHANGE
| MII_PHY_IRQ_SPEED_CHANGE))
{
int esa_ok = 0;
(sc->funs->stop)(sc);
// Try to read the ethernet address of the transciever ...
#ifdef CYGPKG_REDBOOT
esa_ok = flash_get_config("tsec_esa", enaddr, CONFIG_ESA);
#else
esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"tsec_esa", enaddr, CONFIG_ESA);
#endif
if (!esa_ok)
{
// Can't figure out ESA
os_printf("TSEC_ETH - Warning! ESA unknown\n");
memcpy(&enaddr, &_default_enaddr, sizeof(enaddr));
}
(sc->funs->start)(sc, (unsigned char *) enaddr, 1);
}
cyg_drv_interrupt_unmask(vector);
}
// Initialize the interface - performed at system startup
// This function must set up the interface, including arranging to
// handle interrupts, etc, so that it may be "started" cheaply later.
static bool emaclite_init(struct cyg_netdevtab_entry *dtp)
{
struct eth_drv_sc *sc = (struct eth_drv_sc *)dtp->device_instance;
struct emaclite_info *qi = (struct emaclite_info *)sc->driver_private;
unsigned char _enaddr[6];
bool esa_ok;
/* Try to read the ethernet address of the transciever ... */
#if defined(CYGPKG_REDBOOT) && defined(CYGSEM_REDBOOT_FLASH_CONFIG)
esa_ok = flash_get_config(qi->esa_key, _enaddr, CONFIG_ESA);
#else
esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
qi->esa_key, _enaddr, CONFIG_ESA);
#endif
if (esa_ok) {
memcpy(qi->enaddr, _enaddr, sizeof(qi->enaddr));
} else {
/* No 'flash config' data available - use default */
diag_printf("Emaclite_ETH - Warning! Using default ESA for '%s'\n", dtp->name);
}
/* Initialize Xilinx driver - device id 0*/
if (XEmacLite_Initialize(&qi->dev, 0) != XST_SUCCESS) {
diag_printf("Emaclite_ETH - can't initialize\n");
return false;
}
if (XEmacLite_SelfTest(&qi->dev) != XST_SUCCESS) {
diag_printf("Emaclite_ETH - self test failed\n");
return false;
}
XEmacLite_SetMacAddress(&qi->dev, qi->enaddr);
XEmacLite_SetSendHandler(&qi->dev, sc, emaclite_TxEvent);
XEmacLite_SetRecvHandler(&qi->dev, sc, emaclite_RxEvent);
#ifdef CYGPKG_NET
/* Set up to handle interrupts */
cyg_drv_interrupt_create(qi->int_vector,
0, // Highest //CYGARC_SIU_PRIORITY_HIGH,
(cyg_addrword_t)sc, // Data passed to ISR
(cyg_ISR_t *)emaclite_isr,
(cyg_DSR_t *)eth_drv_dsr,
&qi->emaclite_interrupt_handle,
&qi->emaclite_interrupt);
cyg_drv_interrupt_attach(qi->emaclite_interrupt_handle);
cyg_drv_interrupt_acknowledge(qi->int_vector);
cyg_drv_interrupt_unmask(qi->int_vector);
#endif
/* Operating mode */
_s3esk_dev = &qi->dev;
/* Initialize upper level driver for ecos */
(sc->funs->eth_drv->init)(sc, (unsigned char *)&qi->enaddr);
return true;
}
// Initialize the interface - performed at system startup
// This function must set up the interface, including arranging to
// handle interrupts, etc, so that it may be "started" cheaply later.
static bool
s3esk_eth_init(struct cyg_netdevtab_entry *dtp)
{
struct eth_drv_sc *sc = (struct eth_drv_sc *)dtp->device_instance;
struct s3esk_eth_info *qi = (struct s3esk_eth_info *)sc->driver_private;
//Xuint32 opt;
unsigned char _enaddr[6];
bool esa_ok;
// Try to read the ethernet address of the transciever ...
#if defined(CYGPKG_REDBOOT) && defined(CYGSEM_REDBOOT_FLASH_CONFIG)
esa_ok = flash_get_config(qi->esa_key, _enaddr, CONFIG_ESA);
#else
esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
qi->esa_key, _enaddr, CONFIG_ESA);
#endif
if (esa_ok) {
memcpy(qi->enaddr, _enaddr, sizeof(qi->enaddr));
} else {
// No 'flash config' data available - use default
diag_printf("s3esk_ETH - Warning! Using default ESA for '%s'\n", dtp->name);
}
// Initialize Xilinx driver
if (XEmacLite_Initialize(&qi->dev, XPAR_ETHERNET_MAC_DEVICE_ID) != XST_SUCCESS) {
diag_printf("s3esk_ETH - can't initialize\n");
return false;
}
//if (XEmac_mIsSgDma(&qi->dev)) {
// diag_printf("s3esk_ETH - DMA support?\n");
// return false;
//}
if (XEmacLite_SelfTest(&qi->dev) != XST_SUCCESS) {
diag_printf("s3esk_ETH - self test failed\n");
return false;
}
//XEmac_ClearStats(&qi->dev);
// Configure device operating mode
//opt = XEM_UNICAST_OPTION |
// XEM_BROADCAST_OPTION |
// XEM_INSERT_PAD_OPTION |
// XEM_INSERT_FCS_OPTION |
// XEM_STRIP_PAD_FCS_OPTION;
//if (XEmac_SetOptions(&qi->dev, opt) != XST_SUCCESS) {
// diag_printf("s3esk_ETH - can't configure mode\n");
// return false;
//}
//if (XEmacLite_SetMacAddress(&qi->dev, qi->enaddr) != XST_SUCCESS) {
// diag_printf("s3esk_ETH - can't set ESA\n");
// return false;
//}
XEmacLite_SetMacAddress(&qi->dev, qi->enaddr);
// Set up FIFO handling routines - these are callbacks from the
// Xilinx driver code which happen at interrupt time
XEmacLite_SetSendHandler(&qi->dev, sc, s3esk_eth_TxEvent);
XEmacLite_SetRecvHandler(&qi->dev, sc, s3esk_eth_RxEvent);
//XEmac_SetErrorHandler(&qi->dev, sc, s3esk_eth_ErrEvent);
#ifdef CYGPKG_NET
// Set up to handle interrupts
cyg_drv_interrupt_create(qi->int_vector,
0, // Highest //CYGARC_SIU_PRIORITY_HIGH,
(cyg_addrword_t)sc, // Data passed to ISR
(cyg_ISR_t *)s3esk_eth_isr,
(cyg_DSR_t *)eth_drv_dsr,
&qi->s3esk_eth_interrupt_handle,
&qi->s3esk_eth_interrupt);
cyg_drv_interrupt_attach(qi->s3esk_eth_interrupt_handle);
cyg_drv_interrupt_acknowledge(qi->int_vector);
cyg_drv_interrupt_unmask(qi->int_vector);
#endif
// Operating mode
_s3esk_dev = &qi->dev;
//if (!_eth_phy_init(qi->phy)) {
// return false;
//}
//#ifdef CYGSEM_DEVS_ETH_POWERPC_s3esk_RESET_PHY
//_eth_phy_reset(qi->phy);
//#endif
// Initialize upper level driver for ecos
(sc->funs->eth_drv->init)(sc, (unsigned char *)&qi->enaddr);
return true;
}
//
// Initialize the interface - performed at system startup
// This function must set up the interface, including arranging to
// handle interrupts, etc, so that it may be "started" cheaply later.
//
static bool
quicc_eth_init(struct cyg_netdevtab_entry *tab)
{
struct eth_drv_sc *sc = (struct eth_drv_sc *)tab->device_instance;
struct quicc_eth_info *qi = (struct quicc_eth_info *)sc->driver_private;
volatile EPPC *eppc = (volatile EPPC *)eppc_base();
struct cp_bufdesc *rxbd, *txbd;
unsigned char *RxBUF, *TxBUF, *ep, *ap;
volatile struct ethernet_pram *enet_pram;
volatile struct scc_regs *scc;
int TxBD, RxBD;
int cache_state;
int i;
bool esa_ok;
// Fetch the board address from the VPD
#define VPD_ETHERNET_ADDRESS 0x08
if (_mbx_fetch_VPD(VPD_ETHERNET_ADDRESS, enaddr, sizeof(enaddr)) == 0) {
#if defined(CYGPKG_REDBOOT) && \
defined(CYGSEM_REDBOOT_FLASH_CONFIG)
esa_ok = flash_get_config("quicc_esa", enaddr, CONFIG_ESA);
#else
esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"quicc_esa", enaddr, CONFIG_ESA);
#endif
if (!esa_ok) {
// Can't figure out ESA
diag_printf("QUICC_ETH - Warning! ESA unknown\n");
memcpy(&enaddr, &_default_enaddr, sizeof(enaddr));
}
}
// Ensure consistent state between cache and what the QUICC sees
HAL_DCACHE_IS_ENABLED(cache_state);
HAL_DCACHE_SYNC();
HAL_DCACHE_DISABLE();
#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
// Set up to handle interrupts
cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_CPM_SCC1,
CYGARC_SIU_PRIORITY_HIGH,
(cyg_addrword_t)sc, // Data item passed to interrupt handler
(cyg_ISR_t *)quicc_eth_isr,
(cyg_DSR_t *)eth_drv_dsr,
&quicc_eth_interrupt_handle,
&quicc_eth_interrupt);
cyg_drv_interrupt_attach(quicc_eth_interrupt_handle);
cyg_drv_interrupt_acknowledge(CYGNUM_HAL_INTERRUPT_CPM_SCC1);
cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_CPM_SCC1);
#endif
qi->pram = enet_pram = &eppc->pram[0].enet_scc;
qi->ctl = scc = &eppc->scc_regs[0]; // Use SCC1
// Shut down ethernet, in case it is already running
scc->scc_gsmr_l &= ~(QUICC_SCC_GSML_ENR | QUICC_SCC_GSML_ENT);
memset((void *)enet_pram, 0, sizeof(*enet_pram));
TxBD = 0x2C00; // FIXME
RxBD = TxBD + CYGNUM_DEVS_ETH_POWERPC_QUICC_TxNUM * sizeof(struct cp_bufdesc);
txbd = (struct cp_bufdesc *)((char *)eppc + TxBD);
rxbd = (struct cp_bufdesc *)((char *)eppc + RxBD);
qi->tbase = txbd;
qi->txbd = txbd;
qi->tnext = txbd;
qi->rbase = rxbd;
qi->rxbd = rxbd;
qi->rnext = rxbd;
RxBUF = &quicc_eth_rxbufs[0][0];
TxBUF = &quicc_eth_txbufs[0][0];
// setup buffer descriptors
for (i = 0; i < CYGNUM_DEVS_ETH_POWERPC_QUICC_RxNUM; i++) {
rxbd->length = 0;
rxbd->buffer = RxBUF;
rxbd->ctrl = QUICC_BD_CTL_Ready | QUICC_BD_CTL_Int;
RxBUF += CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE;
rxbd++;
}
rxbd--;
rxbd->ctrl |= QUICC_BD_CTL_Wrap; // Last buffer
for (i = 0; i < CYGNUM_DEVS_ETH_POWERPC_QUICC_TxNUM; i++) {
txbd->length = 0;
txbd->buffer = TxBUF;
txbd->ctrl = 0;
TxBUF += CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE;
txbd++;
}
txbd--;
txbd->ctrl |= QUICC_BD_CTL_Wrap; // Last buffer
// Set up parallel ports for connection to MC68160 ethernet tranceiver
eppc->pio_papar |= (QUICC_MBX_PA_RXD | QUICC_MBX_PA_TXD);
eppc->pio_padir &= ~(QUICC_MBX_PA_RXD | QUICC_MBX_PA_TXD);
eppc->pio_paodr &= ~QUICC_MBX_PA_TXD;
eppc->pio_pcpar &= ~(QUICC_MBX_PC_COLLISION | QUICC_MBX_PC_Rx_ENABLE);
eppc->pio_pcdir &= ~(QUICC_MBX_PC_COLLISION | QUICC_MBX_PC_Rx_ENABLE);
eppc->pio_pcso |= (QUICC_MBX_PC_COLLISION | QUICC_MBX_PC_Rx_ENABLE);
eppc->pio_papar |= (QUICC_MBX_PA_Tx_CLOCK | QUICC_MBX_PA_Rx_CLOCK);
eppc->pio_padir &= ~(QUICC_MBX_PA_Tx_CLOCK | QUICC_MBX_PA_Rx_CLOCK);
// Set up clock routing
eppc->si_sicr &= ~QUICC_MBX_SICR_MASK;
eppc->si_sicr |= QUICC_MBX_SICR_ENET;
eppc->si_sicr &= ~QUICC_MBX_SICR_SCC1_ENABLE;
// Set up DMA mode
eppc->dma_sdcr = 0x0001;
// Initialize shared PRAM
enet_pram->rbase = RxBD;
enet_pram->tbase = TxBD;
// Set Big Endian mode
enet_pram->rfcr = QUICC_SCC_FCR_BE;
enet_pram->tfcr = QUICC_SCC_FCR_BE;
// Size of receive buffers
enet_pram->mrblr = CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE;
// Initialize CRC calculations
enet_pram->c_pres = 0xFFFFFFFF;
enet_pram->c_mask = 0xDEBB20E3; // Actual CRC formula
enet_pram->crcec = 0;
enet_pram->alec = 0;
enet_pram->disfc = 0;
// Frame padding
enet_pram->pads = 0x8888;
enet_pram->pads = 0x0000;
// Retries
enet_pram->ret_lim = 15;
enet_pram->ret_cnt = 0;
// Frame sizes
enet_pram->mflr = IEEE_8023_MAX_FRAME;
enet_pram->minflr = IEEE_8023_MIN_FRAME;
enet_pram->maxd1 = CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE;
enet_pram->maxd2 = CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE;
// Group address hash
enet_pram->gaddr1 = 0;
enet_pram->gaddr2 = 0;
enet_pram->gaddr3 = 0;
enet_pram->gaddr4 = 0;
// Device physical address
ep = &enaddr[sizeof(enaddr)];
ap = (unsigned char *)&enet_pram->paddr_h;
for (i = 0; i < sizeof(enaddr); i++) {
*ap++ = *--ep;
}
// Persistence counter
enet_pram->p_per = 0;
// Individual address filter
enet_pram->iaddr1 = 0;
enet_pram->iaddr2 = 0;
enet_pram->iaddr3 = 0;
enet_pram->iaddr4 = 0;
// Temp address
enet_pram->taddr_h = 0;
enet_pram->taddr_m = 0;
enet_pram->taddr_l = 0;
// Initialize the CPM (set up buffer pointers, etc).
eppc->cp_cr = QUICC_CPM_SCC1 | QUICC_CPM_CR_INIT_TXRX | QUICC_CPM_CR_BUSY;
while (eppc->cp_cr & QUICC_CPM_CR_BUSY) ;
// Clear any pending interrupt/exceptions
scc->scc_scce = 0xFFFF;
// Enable interrupts
scc->scc_sccm = QUICC_SCCE_INTS;
// Set up SCC1 to run in ethernet mode
scc->scc_gsmr_h = 0;
scc->scc_gsmr_l = QUICC_SCC_GSML_TCI | QUICC_SCC_GSML_TPL_48 |
QUICC_SCC_GSML_TPP_01 | QUICC_SCC_GSML_MODE_ENET;
// Sync delimiters
scc->scc_dsr = 0xD555;
// Protocol specifics (as if GSML wasn't enough)
scc->scc_psmr = QUICC_PMSR_ENET_CRC | QUICC_PMSR_SEARCH_AFTER_22 |
QUICC_PMSR_RCV_SHORT_FRAMES;
// Configure board interface
*MBX_CTL1 = MBX_CTL1_ETEN | MBX_CTL1_TPEN; // Enable ethernet, TP mode
// Enable ethernet interface
eppc->pio_pcpar |= QUICC_MBX_PC_Tx_ENABLE;
eppc->pio_pcdir &= ~QUICC_MBX_PC_Tx_ENABLE;
if (cache_state)
HAL_DCACHE_ENABLE();
// Initialize upper level driver
(sc->funs->eth_drv->init)(sc, (unsigned char *)&enaddr);
return true;
}
// Initialize the interface - performed at system startup
// This function must set up the interface, including arranging to
// handle interrupts, etc, so that it may be "started" cheaply later.
static bool
fcc_eth_init(struct cyg_netdevtab_entry *dtp)
{
struct eth_drv_sc *sc = (struct eth_drv_sc *)dtp->device_instance;
struct fcc_eth_info *qi = (struct fcc_eth_info *)sc->driver_private;
volatile t_Fcc_Pram *fcc = (volatile t_Fcc_Pram *)0;
volatile t_EnetFcc_Pram *E_fcc;
int i, fcc_chan;
bool esa_ok;
unsigned char *c_ptr;
unsigned char _enaddr[6];
unsigned long rxbase, txbase;
struct fcc_bd *rxbd, *txbd;
// The FCC seems rather picky about these...
static long rxbd_base = 0x3000;
static long txbd_base = 0xB000;
#ifdef CYGPKG_DEVS_ETH_PHY
unsigned short phy_state = 0;
#endif
// Set up pointers to FCC controller
switch (qi->int_vector) {
case CYGNUM_HAL_INTERRUPT_FCC1:
qi->fcc_reg = &(IMM->fcc_regs[FCC1]);
fcc = (volatile t_Fcc_Pram *)((unsigned long)IMM + FCC1_PRAM_OFFSET);
fcc_chan = FCC1_PAGE_SUBBLOCK;
break;
case CYGNUM_HAL_INTERRUPT_FCC2:
qi->fcc_reg = &(IMM->fcc_regs[FCC2]);
fcc = (volatile t_Fcc_Pram *)((unsigned long)IMM + FCC2_PRAM_OFFSET);
fcc_chan = FCC2_PAGE_SUBBLOCK;
break;
case CYGNUM_HAL_INTERRUPT_FCC3:
qi->fcc_reg = &(IMM->fcc_regs[FCC3]);
fcc = (volatile t_Fcc_Pram *)((unsigned long)IMM + FCC3_PRAM_OFFSET);
fcc_chan = FCC3_PAGE_SUBBLOCK;
break;
default:
os_printf("Can't initialize '%s' - unknown FCC!\n", dtp->name);
return false;
}
// just in case : disable Transmit and Receive
qi->fcc_reg->fcc_gfmr &= ~(FCC_GFMR_EN_Rx | FCC_GFMR_EN_Tx);
// Try to read the ethernet address of the transciever ...
#ifdef CYGPKG_REDBOOT
esa_ok = flash_get_config(qi->esa_key, _enaddr, CONFIG_ESA);
#else
esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
qi->esa_key, _enaddr, CONFIG_ESA);
#endif
if (esa_ok) {
memcpy(qi->enaddr, _enaddr, sizeof(qi->enaddr));
} else {
// No 'flash config' data available - use default
os_printf("FCC_ETH - Warning! Using default ESA for '%s'\n", dtp->name);
}
// Initialize Receive Buffer Descriptors
rxbase = rxbd_base;
fcc->riptr = rxbase; // temp work buffer
fcc->mrblr = FCC_PRAM_MRBLR; // Max Rx buffer
fcc->rstate &= FCC_FCR_INIT;
fcc->rstate |= FCC_FCR_MOT_BO;
rxbase += 64;
rxbd_base += sizeof(struct fcc_bd)*qi->rxnum + 64;
rxbd = (struct fcc_bd *)(CYGARC_IMM_BASE + rxbase);
fcc->rbase = (CYG_WORD)rxbd;
c_ptr = qi->rxbuf;
qi->rbase = rxbd;
qi->rxbd = rxbd;
qi->rnext = rxbd;
for (i = 0; i < qi->rxnum; i++, rxbd++) {
rxbd->ctrl = (FCC_BD_Rx_Empty | FCC_BD_Rx_Int);
rxbd->length = 0; // reset
c_ptr = (unsigned char *) ALIGN_TO_CACHE_LINES(c_ptr);
rxbd->buffer = (volatile unsigned char *)c_ptr;
c_ptr += CYGNUM_DEVS_ETH_POWERPC_FCC_BUFSIZE;
}
rxbd--;
rxbd->ctrl |= FCC_BD_Rx_Wrap;
// Initialize Transmit Buffer Descriptors
txbase = txbd_base;
fcc->tiptr = txbase; // in dual port RAM (see 28-11)
fcc->tstate &= FCC_FCR_INIT;
fcc->tstate |= FCC_FCR_MOT_BO;
txbase += 64;
txbd_base += sizeof(struct fcc_bd)*qi->txnum + 64;
txbd = (struct fcc_bd *)(CYGARC_IMM_BASE + txbase);
fcc->tbase = (CYG_WORD)txbd;
c_ptr = qi->txbuf;
qi->tbase = txbd;
qi->txbd = txbd;
qi->tnext = txbd;
for (i = 0; i < qi->txnum; i++, txbd++) {
txbd->ctrl = (FCC_BD_Tx_Pad | FCC_BD_Tx_Int);
txbd->length = 0; // reset : Write before send
c_ptr = (unsigned char *) ALIGN_TO_CACHE_LINES(c_ptr);
txbd->buffer = (volatile unsigned char *)c_ptr;
c_ptr += CYGNUM_DEVS_ETH_POWERPC_FCC_BUFSIZE;
}
txbd--;
txbd->ctrl |= FCC_BD_Tx_Wrap;
// Ethernet Specific FCC Parameter RAM Initialization
E_fcc = &(fcc->SpecificProtocol.e);
E_fcc->c_mask = FCC_PRAM_C_MASK; // (see 30-9)
E_fcc->c_pres = FCC_PRAM_C_PRES;
E_fcc->crcec = 0;
E_fcc->alec = 0;
E_fcc->disfc = 0;
E_fcc->ret_lim = FCC_PRAM_RETLIM;
E_fcc->p_per = FCC_PRAM_PER_LO;
E_fcc->gaddr_h = 0;
E_fcc->gaddr_l = 0;
E_fcc->tfcstat = 0;
E_fcc->mflr = FCC_MAX_FLR;
E_fcc->paddr1_h = ((short)qi->enaddr[5] << 8) | qi->enaddr[4];
E_fcc->paddr1_m = ((short)qi->enaddr[3] << 8) | qi->enaddr[2];
E_fcc->paddr1_l = ((short)qi->enaddr[1] << 8) | qi->enaddr[0];
E_fcc->iaddr_h = 0;
E_fcc->iaddr_l = 0;
E_fcc->minflr = FCC_MIN_FLR;
E_fcc->taddr_h = 0;
E_fcc->taddr_m = 0;
E_fcc->taddr_l = 0;
E_fcc->pad_ptr = fcc->tiptr; // No special padding char ...
E_fcc->cf_type = 0;
E_fcc->maxd1 = FCC_PRAM_MAXD;
E_fcc->maxd2 = FCC_PRAM_MAXD;
// FCC register initialization
qi->fcc_reg->fcc_gfmr = FCC_GFMR_INIT;
qi->fcc_reg->fcc_psmr = FCC_PSMR_INIT;
qi->fcc_reg->fcc_dsr = FCC_DSR_INIT;
#ifdef CYGPKG_NET
// clear the events of FCCX
qi->fcc_reg->fcc_fcce = 0xFFFF;
qi->fcc_reg->fcc_fccm = FCC_EV_TXE | FCC_EV_TXB | FCC_EV_RXF;
// Set up to handle interrupts
cyg_drv_interrupt_create(qi->int_vector,
0, // Highest //CYGARC_SIU_PRIORITY_HIGH,
(cyg_addrword_t)sc, // Data passed to ISR
(cyg_ISR_t *)fcc_eth_isr,
(cyg_DSR_t *)eth_drv_dsr,
&qi->fcc_eth_interrupt_handle,
&qi->fcc_eth_interrupt);
cyg_drv_interrupt_attach(qi->fcc_eth_interrupt_handle);
cyg_drv_interrupt_acknowledge(qi->int_vector);
cyg_drv_interrupt_unmask(qi->int_vector);
#else
// Mask the interrupts
qi->fcc_reg->fcc_fccm = 0;
#endif
// Issue Init RX & TX Parameters Command for FCCx
while ((IMM->cpm_cpcr & CPCR_FLG) != CPCR_READY_TO_RX_CMD);
IMM->cpm_cpcr = CPCR_INIT_TX_RX_PARAMS |
fcc_chan |
CPCR_MCN_FCC |
CPCR_FLG; /* ISSUE COMMAND */
while ((IMM->cpm_cpcr & CPCR_FLG) != CPCR_READY_TO_RX_CMD);
// Operating mode
if (!_eth_phy_init(qi->phy)) {
return false;
}
#ifdef CYGSEM_DEVS_ETH_POWERPC_FCC_RESET_PHY
_eth_phy_reset(qi->phy);
#endif
phy_state = _eth_phy_state(qi->phy);
os_printf("FCC %s: ", sc->dev_name);
if ((phy_state & ETH_PHY_STAT_LINK) != 0) {
if ((phy_state & ETH_PHY_STAT_100MB) != 0) {
// Link can handle 100Mb
os_printf("100Mb");
if ((phy_state & ETH_PHY_STAT_FDX) != 0) {
os_printf("/Full Duplex");
}
} else {
// Assume 10Mb, half duplex
os_printf("10Mb");
}
} else {
os_printf("/***NO LINK***\n");
#ifdef CYGPKG_REDBOOT
return false;
#endif
}
os_printf("\n");
// Initialize upper level driver for ecos
(sc->funs->eth_drv->init)(sc, (unsigned char *)&qi->enaddr);
return true;
}
void init_all_network_interfaces(void)
{
cyg_bool_t use_bootp;
cyg_bool_t setup_network = false;
in_addr_t local_ip_addr = 0;
in_addr_t broadcast_addr = 0;
in_addr_t server_addr = 0;
in_addr_t gateway_addr = 0;
in_addr_t network_mask = 0;
char server_str[16];
char network_str[16];
char gateway_str[16];
char broadcast_str[16];
char ip_addr_str[16];
int i;
int net_up = false;
static volatile int in_init_all_network_interfaces = 0;
cyg_scheduler_lock();
while ( in_init_all_network_interfaces ) {
// Another thread is doing this...
cyg_scheduler_unlock();
cyg_thread_delay( 10 );
cyg_scheduler_lock();
}
in_init_all_network_interfaces = 1;
cyg_scheduler_unlock();
#ifdef CYGHWR_NET_DRIVER_ETH0
// Fetch values from saved config data, if available
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"app_bootn", &setup_network,
CYGNUM_FLASH_CFG_OP_CONFIG_BOOL);
if (setup_network)
{
// Set defaults as appropriate
use_bootp = true;
// Fetch values from saved config data, if available
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"app_bootp", &use_bootp,
CYGNUM_FLASH_CFG_OP_CONFIG_BOOL);
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"app_bootp_localip_addr", &local_ip_addr,
CYGNUM_FLASH_CFG_OP_CONFIG_IP);
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"app_bootp_localip_mask", &network_mask,
CYGNUM_FLASH_CFG_OP_CONFIG_IP);
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"app_bootp_mygateway_addr", &gateway_addr,
CYGNUM_FLASH_CFG_OP_CONFIG_IP);
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"app_bootp_ubroadcast_addr",
&broadcast_addr,
CYGNUM_FLASH_CFG_OP_CONFIG_IP);
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"app_bootp_serverip_addr", &server_addr,
CYGNUM_FLASH_CFG_OP_CONFIG_IP);
if (use_bootp)
{
// Perform a complete initialization, using BOOTP/DHCP
eth0_up = true;
//#ifdef CYGHWR_NET_DRIVER_ETH0_DHCP
eth0_dhcpstate = 0; // Says that initialization is external to dhcp
if (do_dhcp(eth0_name, ð0_bootp_data, ð0_dhcpstate,
ð0_lease))
//#else
//#ifdef CYGPKG_NET_DHCP
// eth0_dhcpstate = DHCPSTATE_BOOTP_FALLBACK;
// so the dhcp machine does no harm if called
//#endif
// if (do_bootp(eth0_name, ð0_bootp_data))
//#endif
{
#ifdef CYGHWR_NET_DRIVER_ETH0_BOOTP_SHOW
show_bootp(eth0_name, ð0_bootp_data);
#endif
} else {
printf("BOOTP/DHCP failed on eth0\n");
eth0_up = false;
}
}
else
{
eth0_up = true;
strncpy(ip_addr_str,
inet_ntoa(*(struct in_addr *) &local_ip_addr), 16);
strncpy(broadcast_str,
inet_ntoa(*(struct in_addr *) &broadcast_addr), 16);
strncpy(gateway_str, inet_ntoa(*(struct in_addr *) &gateway_addr),
16);
strncpy(network_str, inet_ntoa(*(struct in_addr *) &network_mask),
16);
strncpy(server_str, inet_ntoa(*(struct in_addr *) &server_addr),
16);
/* load flash configuration parameters */
build_bootp_record(ð0_bootp_data, eth0_name, ip_addr_str,
network_str, broadcast_str, gateway_str,
server_str);
#ifdef CYGHWR_NET_DRIVER_ETH0_BOOTP_SHOW
show_bootp(eth0_name, ð0_bootp_data);
#endif
}
}
#endif
#ifdef CYGHWR_NET_DRIVER_ETH1
setup_network = false;
// Fetch values from saved config data, if available
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"app_c_bootn", &setup_network,
CYGNUM_FLASH_CFG_OP_CONFIG_BOOL);
if (setup_network)
{
// Set defaults as appropriate
use_bootp = true;
// Fetch values from saved config data, if available
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"app_c_bootp", &use_bootp,
CYGNUM_FLASH_CFG_OP_CONFIG_BOOL);
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"app_c_bootp_localip_addr", &local_ip_addr,
CYGNUM_FLASH_CFG_OP_CONFIG_IP);
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"app_c_bootp_localip_mask", &network_mask,
CYGNUM_FLASH_CFG_OP_CONFIG_IP);
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"app_c_bootp_mygateway_addr", &gateway_addr,
CYGNUM_FLASH_CFG_OP_CONFIG_IP);
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"app_c_bootp_ubroadcast_addr",
&broadcast_addr,
CYGNUM_FLASH_CFG_OP_CONFIG_IP);
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"app_c_bootp_serverip_addr", &server_addr,
CYGNUM_FLASH_CFG_OP_CONFIG_IP);
if (use_bootp)
{
// Perform a complete initialization, using BOOTP/DHCP
eth1_up = true;
//#ifdef CYGHWR_NET_DRIVER_ETH1_DHCP
eth1_dhcpstate = 0; // Says that initialization is external to dhcp
if (do_dhcp(eth1_name, ð1_bootp_data, ð1_dhcpstate,
ð1_lease))
//#else
//#ifdef CYGPKG_NET_DHCP
// eth0_dhcpstate = DHCPSTATE_BOOTP_FALLBACK;
// so the dhcp machine does no harm if called
//#endif
// if (do_bootp(eth1_name, ð1_bootp_data))
//#endif
{
#ifdef CYGHWR_NET_DRIVER_ETH1_BOOTP_SHOW
show_bootp(eth1_name, ð1_bootp_data);
#endif
} else {
printf("BOOTP/DHCP failed on eth1\n");
eth1_up = false;
}
}
else
{
eth1_up = true;
strncpy(ip_addr_str,
inet_ntoa(*(struct in_addr *) &local_ip_addr), 16);
strncpy(broadcast_str,
inet_ntoa(*(struct in_addr *) &broadcast_addr), 16);
strncpy(gateway_str, inet_ntoa(*(struct in_addr *) &gateway_addr),
16);
strncpy(network_str, inet_ntoa(*(struct in_addr *) &network_mask),
16);
strncpy(server_str, inet_ntoa(*(struct in_addr *) &server_addr),
16);
/* load flash configuration parameters */
build_bootp_record(ð1_bootp_data, eth1_name, ip_addr_str,
network_str, broadcast_str, gateway_str,
server_str);
#ifdef CYGHWR_NET_DRIVER_ETH1_BOOTP_SHOW
show_bootp(eth1_name, ð1_bootp_data);
#endif
}
}
#endif
#ifdef CYGHWR_NET_DRIVER_ETH0
if (eth0_up) {
if (!init_net(eth0_name, ð0_bootp_data)) {
printf("Network initialization failed for eth0\n");
eth0_up = false;
}
#ifdef CYGHWR_NET_DRIVER_ETH0_IPV6_PREFIX
if (!init_net_IPv6(eth0_name, ð0_bootp_data,
string(CYGHWR_NET_DRIVER_ETH0_IPV6_PREFIX))) {
diag_printf("Static IPv6 network initialization failed for eth0\n");
eth0_up = false; // ???
}
#endif
if (eth0_up)
{
unsigned int length = 4;
struct in_addr temp;
diag_printf("\nIP: %s", inet_ntoa(eth0_bootp_data.bp_yiaddr));
get_bootp_option(ð0_bootp_data, TAG_SUBNET_MASK,
(void *)&temp, &length);
diag_printf("/%s", inet_ntoa(temp));
get_bootp_option(ð0_bootp_data, TAG_GATEWAY,
(void *)&temp, &length);
// diag_printf(", Gateway: %s\n", inet_ntoa(eth0_bootp_data.bp_giaddr));
diag_printf(", Gateway: %s\n", inet_ntoa(temp));
diag_printf("Server: %s", inet_ntoa(eth0_bootp_data.bp_siaddr));
net_up = true;
}
}
#endif
#ifdef CYGHWR_NET_DRIVER_ETH1
if (eth1_up) {
if (!init_net(eth1_name, ð1_bootp_data)) {
printf("Network initialization failed for eth1\n");
eth1_up = false;
}
#ifdef CYGHWR_NET_DRIVER_ETH1_IPV6_PREFIX
if (!init_net_IPv6(eth1_name, ð1_bootp_data,
string(CYGHWR_NET_DRIVER_ETH1_IPV6_PREFIX))) {
diag_printf("Static IPv6 network initialization failed for eth1\n");
eth1_up = false; // ???
}
#endif
if (eth1_up)
{
unsigned int length = 4;
struct in_addr temp;
diag_printf("\nIP: %s", inet_ntoa(eth1_bootp_data.bp_yiaddr));
get_bootp_option(ð1_bootp_data, TAG_SUBNET_MASK,
(void *)&temp, &length);
diag_printf("/%s", inet_ntoa(temp));
get_bootp_option(ð1_bootp_data, TAG_GATEWAY,
(void *)&temp, &length);
// diag_printf(", Gateway: %s\n", inet_ntoa(eth1_bootp_data.bp_giaddr));
diag_printf(", Gateway: %s\n", inet_ntoa(temp));
diag_printf("Server: %s", inet_ntoa(eth1_bootp_data.bp_siaddr));
net_up = true;
}
}
#endif
#ifdef CYGPKG_NET_NLOOP
#if 0 < CYGPKG_NET_NLOOP
// Create a local IP Address for each of the DSP's */
for (i = 0; i < CYGPKG_NET_NLOOP; ++i)
init_loopback_interface(i);
#endif
#endif
#ifdef CYGOPT_NET_DHCP_DHCP_THREAD
dhcp_start_dhcp_mgt_thread();
#endif
#ifdef CYGOPT_NET_IPV6_ROUTING_THREAD
ipv6_start_routing_thread();
#endif
#ifdef CYGPKG_NS_DNS_BUILD
if (net_up)
{
struct in_addr dns_addr = {0};
int len;
char *dns_domainname;
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"app_dns_ip", &dns_addr,
CYGNUM_FLASH_CFG_OP_CONFIG_IP);
cyg_dns_res_init(&dns_addr);
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"app_dns_domain_name",
&dns_domainname,
CYGNUM_FLASH_CFG_OP_CONFIG_STRING);
len = strlen(dns_domainname);
setdomainname(dns_domainname,len);
diag_printf(", DNS server IP: %s",
inet_ntoa(*(struct in_addr *)&dns_addr));
}
#endif
if (!net_up)
{
diag_printf("Network Disabled");
}
diag_printf("\n\n");
}
// Initialize the interface - performed at system startup
// This function must set up the interface, including arranging to
// handle interrupts, etc, so that it may be "started" cheaply later.
static bool
fec_eth_init(struct cyg_netdevtab_entry *tab)
{
struct eth_drv_sc *sc = (struct eth_drv_sc *)tab->device_instance;
struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private;
volatile t_PQ2IMM *IMM = (volatile t_PQ2IMM *) QUICC2_VADS_IMM_BASE;
volatile t_Fcc_Pram *fcc = (volatile t_Fcc_Pram *) (QUICC2_VADS_IMM_BASE + FEC_PRAM_OFFSET);
volatile t_EnetFcc_Pram *E_fcc = &(fcc->SpecificProtocol.e);
#if defined(CYGPKG_HAL_POWERPC_VADS) || defined(CYGPKG_HAL_POWERPC_TS6)
volatile t_BCSR *CSR = (t_BCSR *) 0x04500000;
#endif
int i;
bool esa_ok;
bool fec_100;
unsigned char *c_ptr;
UINT16 link_speed;
// Link the memory to the driver control memory
qi->fcc_reg = & (IMM->fcc_regs[FCC2]);
// just in case : disable Transmit and Receive
qi->fcc_reg->fcc_gfmr &= ~(FEC_GFMR_EN_Rx | FEC_GFMR_EN_Tx);
// Via BCSR, (re)start LXT970
#if defined(CYGPKG_HAL_POWERPC_VADS) || defined(CYGPKG_HAL_POWERPC_TS6)
EnableResetPHY(CSR);
#endif
// Try to read the ethernet address of the transciever ...
#ifdef CYGPKG_REDBOOT
esa_ok = flash_get_config("fec_100", &fec_100, CONFIG_BOOL);
#else
esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"fec_100", &fec_100, CONFIG_BOOL);
#endif
link_speed = NOTLINKED;
if(esa_ok && fec_100){
// Via MII Management pins, tell LXT970 to initialize
os_printf("Attempting to acquire 100 Mbps half_duplex link ...");
InitEthernetPHY((VUINT32 *) &(IMM->io_regs[PORT_C].pdir),
(VUINT32 *) &(IMM->io_regs[PORT_C].pdat),
HUNDRED_HD);
link_speed = LinkTestPHY();
os_printf("\n");
if(link_speed == NOTLINKED){
os_printf("Failed to get 100 Mbps half_duplex link.\n");
}
}
if(link_speed == NOTLINKED){
os_printf("Attempting to acquire 10 Mbps half_duplex link ...");
InitEthernetPHY((VUINT32 *) &(IMM->io_regs[PORT_C].pdir),
(VUINT32 *) &(IMM->io_regs[PORT_C].pdat),
TEN_HD);
link_speed = LinkTestPHY();
os_printf("\n");
if(link_speed == NOTLINKED){
link_speed = LinkTestPHY();
os_printf("Failed to get 10 Mbps half_duplex link.\n");
}
}
switch ( link_speed ) {
case HUNDRED_FD:
os_printf("100 MB full-duplex ethernet link \n");
break;
case HUNDRED_HD:
os_printf("100 MB half-duplex ethernet link \n");
break;
case TEN_FD:
os_printf("10 MB full-duplex ethernet link \n");
break;
case TEN_HD:
os_printf("10 MB half-duplex ethernet link \n");
break;
default:
os_printf("NO ethernet link \n");
}
// Connect PORTC pins: (C19) to clk13, (C18) to clk 14
IMM->io_regs[PORT_C].ppar |= 0x00003000;
IMM->io_regs[PORT_C].podr &= ~(0x00003000);
IMM->io_regs[PORT_C].psor &= ~(0x00003000);
IMM->io_regs[PORT_C].pdir &= ~(0x00003000);
// Connect clk13 to RxClk and clk14 to TxClk on FCC2
IMM->cpm_mux_cmxfcr &= 0x7f007f00; // clear fcc2 clocks
IMM->cpm_mux_cmxfcr |= 0x00250000; // set fcc2 clocks (see 15-14)
IMM->cpm_mux_cmxuar = 0x0000; // Utopia address reg, just clear
// Initialize parallel port registers to connect FCC2 to MII
IMM->io_regs[PORT_B].podr &= 0xffffc000; // clear bits 18-31
IMM->io_regs[PORT_B].psor &= 0xffffc000;
IMM->io_regs[PORT_B].pdir &= 0xffffc000;
IMM->io_regs[PORT_B].psor |= 0x00000004;
IMM->io_regs[PORT_B].pdir |= 0x000003c5;
IMM->io_regs[PORT_B].ppar |= 0x00003fff;
// Initialize Receive Buffer Descriptors
qi->rbase = fec_eth_rxring;
qi->rxbd = fec_eth_rxring;
qi->rnext = fec_eth_rxring;
c_ptr = fec_eth_rxbufs;
for(i=0; i<CYGNUM_DEVS_ETH_POWERPC_QUICC2_RxNUM; i++) {
fec_eth_rxring[i].ctrl = (FEC_BD_Rx_Empty | FEC_BD_Rx_Int);
fec_eth_rxring[i].length = 0; // reset
c_ptr = (unsigned char *) ALIGN_TO_CACHE_LINES(c_ptr);
fec_eth_rxring[i].buffer = (volatile unsigned char *)c_ptr;
c_ptr += CYGNUM_DEVS_ETH_POWERPC_QUICC2_BUFSIZE;
}
fec_eth_rxring[CYGNUM_DEVS_ETH_POWERPC_QUICC2_RxNUM-1].ctrl |= FEC_BD_Rx_Wrap;
// Initialize Transmit Buffer Descriptors
qi->tbase = fec_eth_txring;
qi->txbd = fec_eth_txring;
qi->tnext = fec_eth_txring;
c_ptr = fec_eth_txbufs;
for(i=0; i<CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM; i++) {
fec_eth_txring[i].ctrl = (FEC_BD_Tx_Pad | FEC_BD_Tx_Int);
fec_eth_txring[i].length = 0; // reset : Write before send
c_ptr = (unsigned char *) ALIGN_TO_CACHE_LINES(c_ptr);
fec_eth_txring[i].buffer = (volatile unsigned char *)c_ptr;
c_ptr += CYGNUM_DEVS_ETH_POWERPC_QUICC2_BUFSIZE;
}
fec_eth_txring[CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM-1].ctrl |= FEC_BD_Tx_Wrap;
// Common FCC Parameter RAM initialization
fcc->riptr = FEC_PRAM_RIPTR; // in dual port RAM (see 28-11)
fcc->tiptr = FEC_PRAM_TIPTR; // in dual port RAM (see 28-11)
fcc->mrblr = FEC_PRAM_MRBLR; // ?? FROM 8101 code ...
fcc->rstate &= FEC_FCR_INIT;
fcc->rstate |= FEC_FCR_MOT_BO;
fcc->rbase = (long) fec_eth_rxring;
fcc->tstate &= FEC_FCR_INIT;
fcc->tstate |= FEC_FCR_MOT_BO;
fcc->tbase = (long) fec_eth_txring;
// Ethernet Specific FCC Parameter RAM Initialization
E_fcc->c_mask = FEC_PRAM_C_MASK; // (see 30-9)
E_fcc->c_pres = FEC_PRAM_C_PRES;
E_fcc->crcec = 0;
E_fcc->alec = 0;
E_fcc->disfc = 0;
E_fcc->ret_lim = FEC_PRAM_RETLIM;
E_fcc->p_per = FEC_PRAM_PER_LO;
E_fcc->gaddr_h = 0;
E_fcc->gaddr_l = 0;
E_fcc->tfcstat = 0;
E_fcc->mflr = FEC_MAX_FLR;
// Try to read the ethernet address of the transciever ...
#ifdef CYGPKG_REDBOOT
esa_ok = flash_get_config("fec_esa", enaddr, CONFIG_ESA);
#else
esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"fec_esa", enaddr, CONFIG_ESA);
#endif
if (!esa_ok) {
// If can't use the default ...
os_printf("FEC_ETH - Warning! ESA unknown\n");
memcpy(enaddr, _default_enaddr, sizeof(enaddr));
}
E_fcc->paddr1_h = ((short)enaddr[5] << 8) | enaddr[4]; // enaddr[2];
E_fcc->paddr1_m = ((short)enaddr[3] << 8) | enaddr[2]; // enaddr[1];
E_fcc->paddr1_l = ((short)enaddr[1] << 8) | enaddr[0]; // enaddr[0];
E_fcc->iaddr_h = 0;
E_fcc->iaddr_l = 0;
E_fcc->minflr = FEC_MIN_FLR;
E_fcc->taddr_h = 0;
E_fcc->taddr_m = 0;
E_fcc->taddr_l = 0;
E_fcc->pad_ptr = FEC_PRAM_TIPTR; // No special padding char ...
E_fcc->cf_type = 0;
E_fcc->maxd1 = FEC_PRAM_MAXD;
E_fcc->maxd2 = FEC_PRAM_MAXD;
// FCC register initialization
IMM->fcc_regs[FCC2].fcc_gfmr = FEC_GFMR_INIT;
IMM->fcc_regs[FCC2].fcc_psmr = FEC_PSMR_INIT;
IMM->fcc_regs[FCC2].fcc_dsr = FEC_DSR_INIT;
#ifdef CYGPKG_NET
// clear the events of FCC2
IMM->fcc_regs[FCC2].fcc_fcce = 0xFFFF0000;
IMM->fcc_regs[FCC2].fcc_fccm = FEC_EV_TXE | FEC_EV_TXB | FEC_EV_RXF;
// Set up to handle interrupts
cyg_drv_interrupt_create(FEC_ETH_INT,
0, // Highest //CYGARC_SIU_PRIORITY_HIGH,
(cyg_addrword_t)sc, // Data passed to ISR
(cyg_ISR_t *)fec_eth_isr,
(cyg_DSR_t *)eth_drv_dsr,
&fec_eth_interrupt_handle,
&fec_eth_interrupt);
cyg_drv_interrupt_attach(fec_eth_interrupt_handle);
cyg_drv_interrupt_acknowledge(FEC_ETH_INT);
cyg_drv_interrupt_unmask(FEC_ETH_INT);
#else
// Mask the interrupts
IMM->fcc_regs[FCC2].fcc_fccm = 0;
#endif
// Issue Init RX & TX Parameters Command for FCC2
while ((IMM->cpm_cpcr & CPCR_FLG) != CPCR_READY_TO_RX_CMD);
IMM->cpm_cpcr = CPCR_INIT_TX_RX_PARAMS |
CPCR_FCC2_CH |
CPCR_MCN_FEC |
CPCR_FLG; /* ISSUE COMMAND */
while ((IMM->cpm_cpcr & CPCR_FLG) != CPCR_READY_TO_RX_CMD);
// Initialize upper level driver for ecos
(sc->funs->eth_drv->init)(sc, (unsigned char *)&enaddr);
return true;
}
//
// Initialize the interface - performed at system startup
// This function must set up the interface, including arranging to
// handle interrupts, etc, so that it may be "started" cheaply later.
//
static bool tsec_eth_init(struct cyg_netdevtab_entry *tab)
{
struct eth_drv_sc *sc = (struct eth_drv_sc *) tab->device_instance;
struct tsec_eth_info *qi = (struct tsec_eth_info *) sc->driver_private;
volatile struct mpq_tsec *tsec =
(volatile struct mpq_tsec *) ((unsigned char *) CYGARC_IMM_BASE
+ CYGARC_REG_IMM_TSEC1);
int speed100 = 0;
int full_duplex = 0;
int link = 0;
bool esa_ok;
int i;
cyg_uint32 phy_state = 0;
cyg_uint32 int_state;
HAL_DISABLE_INTERRUPTS(int_state);
os_printf("ETH Init\n");
tsec_eth_set_rmii_io();
qi->tsec = tsec;
tsec_eth_stop(sc);
#ifdef _TSEC_USE_INTS
cyg_drv_interrupt_create(TSEC_ETH_INT,
0,
(cyg_addrword_t) sc, // Data item passed to interrupt handler
(cyg_ISR_t *) tsec_eth_isr,
(cyg_DSR_t *) eth_drv_dsr,
&tsec_eth_interrupt_handle_err,
&tsec_eth_interrupt_err);
cyg_drv_interrupt_attach(tsec_eth_interrupt_handle_err);
cyg_drv_interrupt_acknowledge(TSEC_ETH_INT);
cyg_drv_interrupt_unmask(TSEC_ETH_INT);
cyg_drv_interrupt_create(TSEC_ETH_INT + 1,
0,
(cyg_addrword_t) sc, // Data item passed to interrupt handler
(cyg_ISR_t *) tsec_eth_isr,
(cyg_DSR_t *) eth_drv_dsr,
&tsec_eth_interrupt_handle_rx,
&tsec_eth_interrupt_rx);
cyg_drv_interrupt_attach(tsec_eth_interrupt_handle_rx);
cyg_drv_interrupt_acknowledge(TSEC_ETH_INT + 1);
cyg_drv_interrupt_unmask(TSEC_ETH_INT + 1);
cyg_drv_interrupt_create(TSEC_ETH_INT + 2,
0,
(cyg_addrword_t) sc, // Data item passed to interrupt handler
(cyg_ISR_t *) tsec_eth_isr,
(cyg_DSR_t *) eth_drv_dsr,
&tsec_eth_interrupt_handle_tx,
&tsec_eth_interrupt_tx);
cyg_drv_interrupt_attach(tsec_eth_interrupt_handle_tx);
cyg_drv_interrupt_acknowledge(TSEC_ETH_INT + 2);
cyg_drv_interrupt_unmask(TSEC_ETH_INT + 2);
#endif
esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"tsec_esa", enaddr, CONFIG_ESA);
if (!esa_ok)
{
// Can't figure out ESA
os_printf("TSEC_ETH - Warning! ESA unknown\n");
memcpy(&enaddr, &_default_enaddr, sizeof(enaddr));
}
resetPHY();
i = 0;
while ((tsec->miimind & MIIMIND_BUSY) != 0 && i++ < 500)
{
// os_printf(".");
HAL_DELAY_US(10000);
}
for (qi->phyAddress = 1; qi->phyAddress < 0x1f; qi->phyAddress++)
{
phy_state = phy_read_register(qi->phyAddress, MII_PHY_ID1_REG);
phy_state = (phy_state & 0xffff) << 16;
phy_state |= phy_read_register(qi->phyAddress, MII_PHY_ID2_REG)
& 0xffff;
if (phy_state == 0xffffffff)
{
os_printf("The PHY management interface is not available! Hardware problem!\n");
}
else
{
// os_printf("life on 0x%02x, state = 0x%08x\n", qi->phyAddress, phy_state);
break;
}
}
createPHYInterrupt(sc);
phyAutoNegociate(qi->phyAddress, &link, &speed100, &full_duplex);
if (!tsec_eth_reset(sc, enaddr, (full_duplex ? RESET_FULL_DUPLEX
: 0x00000000) | (speed100 ? RESET_100MB : 0x00000000)))
{
return false;
}
(sc->funs->eth_drv->init)(sc, (unsigned char *) &enaddr);
HAL_RESTORE_INTERRUPTS(int_state);
#ifdef CYGNUM_DEVS_ETH_POWERPC_TSEC_LINK_MODE_Auto
if (!link)
{
return false;
}
#endif
return true;
}
void vme_master_init(void)
{
#ifndef REV_A_ARTWORK
cyg_bool enable;
cyg_uint32 size;
cyg_uint32 base_addr;
cyg_uint32 user_am;
cyg_uint32 dest_addr;
cyg_uint32 ctl_reg;
cyg_uint32 rqst_lvl;
cyg_uint32 rqst_md;
cyg_uint32 rls_md;
UNIV2_IMAGE imageSpace;
// Set up VME Request and Release Modes
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"vmem_urqst_lvl", &rqst_lvl, CONFIG_INT);
UNIV2SetRequestLevel(P4205_UNIV2_REGS, rqst_lvl);
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"vmem_urqst_md", &rqst_md, CONFIG_INT);
UNIV2SetRequestMode(P4205_UNIV2_REGS, rqst_md);
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"vmem_urls_md", &rls_md, CONFIG_INT);
UNIV2SetReleaseMode(P4205_UNIV2_REGS, rls_md);
// Set up A16/D16 VME Master Access
enable = 1;
base_addr = 0x80010000;
dest_addr = 0x0;
size = 0x10000;
imageSpace.CTL = (enable << 31) | UNIV2_LSICTL_PCI_AM_USER |
UNIV2_LSICTL_PCI_AM_DATA | UNIV2_LSICTL_PCI_VDW_16 |
UNIV2_LSICTL_PCI_AS_A16 | UNIV2_LSICTL_PCI_VCT_SINGLE |
UNIV2_LSICTL_PCI_MS;
imageSpace.BS = base_addr;
imageSpace.BD = imageSpace.BS + size;
imageSpace.TO = dest_addr - imageSpace.BS;
UNIV2SetMasterImage(P4205_UNIV2_REGS, UNIV2_IMAGE_0, &imageSpace);
enable = 1;
base_addr = 0x80020000;
dest_addr = 0x0;
size = 0x10000;
imageSpace.CTL = (enable << 31) | UNIV2_LSICTL_PCI_AM_USER |
UNIV2_LSICTL_PCI_AM_DATA | UNIV2_LSICTL_PCI_VDW_32 |
UNIV2_LSICTL_PCI_AS_A16 | UNIV2_LSICTL_PCI_VCT_SINGLE |
UNIV2_LSICTL_PCI_MS;
imageSpace.BS = base_addr;
imageSpace.BD = imageSpace.BS + size;
imageSpace.TO = dest_addr - imageSpace.BS;
UNIV2SetMasterImage(P4205_UNIV2_REGS, UNIV2_IMAGE_1, &imageSpace);
// Set up A24/D16 VME Master Access
enable = 1;
base_addr = 0x81000000;
dest_addr = 0x0;
size = 0x1000000;
imageSpace.CTL = (enable << 31) | UNIV2_LSICTL_PCI_AM_USER |
UNIV2_LSICTL_PCI_AM_DATA | UNIV2_LSICTL_PCI_VDW_16 |
UNIV2_LSICTL_PCI_AS_A24 | UNIV2_LSICTL_PCI_VCT_SINGLE |
UNIV2_LSICTL_PCI_MS;
imageSpace.BS = base_addr;
imageSpace.BD = imageSpace.BS + size;
imageSpace.TO = dest_addr - imageSpace.BS;
UNIV2SetMasterImage(P4205_UNIV2_REGS, UNIV2_IMAGE_2, &imageSpace);
// Set up A24/D32 VME Master Access
enable = 1;
base_addr = 0x82000000;
dest_addr = 0x0;
size = 0x1000000;
imageSpace.CTL = (enable << 31) | UNIV2_LSICTL_PCI_AM_USER |
UNIV2_LSICTL_PCI_AM_DATA | UNIV2_LSICTL_PCI_VDW_32 |
UNIV2_LSICTL_PCI_AS_A24 | UNIV2_LSICTL_PCI_VCT_SINGLE |
UNIV2_LSICTL_PCI_MS;
imageSpace.BS = base_addr;
imageSpace.BD = imageSpace.BS + size;
imageSpace.TO = dest_addr - imageSpace.BS;
UNIV2SetMasterImage(P4205_UNIV2_REGS, UNIV2_IMAGE_3, &imageSpace);
// Set up A32/D16 VME Master Access
enable = false;
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"vmem_a32_d16", &enable, CONFIG_BOOL);
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"vmem_a32_d16_pa", &base_addr, CONFIG_HEXINT);
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"vmem_a32_d16_va", &dest_addr, CONFIG_HEXINT);
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"vmem_a32_d16_vsz", &size, CONFIG_HEXINT);
imageSpace.CTL = (enable << 31) | UNIV2_LSICTL_PCI_AM_USER |
UNIV2_LSICTL_PCI_AM_DATA | UNIV2_LSICTL_PCI_VDW_16 |
UNIV2_LSICTL_PCI_AS_A32 | UNIV2_LSICTL_PCI_VCT_SINGLE |
UNIV2_LSICTL_PCI_MS;
imageSpace.BS = base_addr;
imageSpace.BD = imageSpace.BS + size;
imageSpace.TO = dest_addr - imageSpace.BS;
UNIV2SetMasterImage(P4205_UNIV2_REGS, UNIV2_IMAGE_4, &imageSpace);
// Set up A32/D32 VME Master Access
enable = false;
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"vmem_a32_d32", &enable, CONFIG_BOOL);
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"vmem_a32_d32_pa", &base_addr, CONFIG_HEXINT);
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"vmem_a32_d32_va", &dest_addr, CONFIG_HEXINT);
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"vmem_a32_d32_vsz", &size, CONFIG_HEXINT);
imageSpace.CTL = (enable << 31) | UNIV2_LSICTL_PCI_AM_USER |
UNIV2_LSICTL_PCI_AM_DATA | UNIV2_LSICTL_PCI_VDW_32 |
UNIV2_LSICTL_PCI_AS_A32 | UNIV2_LSICTL_PCI_VCT_SINGLE |
UNIV2_LSICTL_PCI_MS;
imageSpace.BS = base_addr;
imageSpace.BD = imageSpace.BS + size;
imageSpace.TO = dest_addr - imageSpace.BS;
UNIV2SetMasterImage(P4205_UNIV2_REGS, UNIV2_IMAGE_5, &imageSpace);
// Set up A32/D64 VME Master Access
enable = false;
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"vmem_a32_d64", &enable, CONFIG_BOOL);
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"vmem_a32_d64_pa", &base_addr, CONFIG_HEXINT);
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"vmem_a32_d64_va", &dest_addr, CONFIG_HEXINT);
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"vmem_a32_d64_vsz", &size, CONFIG_HEXINT);
imageSpace.CTL = (enable << 31) | UNIV2_LSICTL_PCI_AM_USER |
UNIV2_LSICTL_PCI_AM_DATA | UNIV2_LSICTL_PCI_VDW_64 |
UNIV2_LSICTL_PCI_AS_A32 | UNIV2_LSICTL_PCI_VCT_SINGLE |
UNIV2_LSICTL_PCI_MS;
imageSpace.BS = base_addr;
imageSpace.BD = imageSpace.BS + size;
imageSpace.TO = dest_addr - imageSpace.BS;
UNIV2SetMasterImage(P4205_UNIV2_REGS, UNIV2_IMAGE_6, &imageSpace);
#if 0
// Setup VME Master Image 6
enable = false;
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"vmem_ui6", &enable, CONFIG_BOOL);
if (enable)
{
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"vmem_ui6_pa", &base_addr, CONFIG_HEXINT);
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"vmem_ui6_va", &dest_addr, CONFIG_HEXINT);
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"vmem_ui6_vsz", &size, CONFIG_HEXINT);
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"vmem_ui6_uam", &user_am, CONFIG_HEXINT);
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"vmem_ui6_ucr", &ctl_reg, CONFIG_HEXINT);
imageSpace.CTL = ctl_reg;
imageSpace.BS = base_addr;
imageSpace.BD = imageSpace.BS + size;
imageSpace.TO = dest_addr - imageSpace.BS;
if (ctl_reg & UNIV2_LSICTL_PCI_AS_USER1)
UNIV2SetUserAM1(P4205_UNIV2_REGS, user_am);
else if (ctl_reg & UNIV2_LSICTL_PCI_AS_USER2)
UNIV2SetUserAM2(P4205_UNIV2_REGS, user_am);
}
else
{
imageSpace.CTL = 0;
imageSpace.BS = 0;
imageSpace.BD = 0;
imageSpace.TO = 0;
}
UNIV2SetMasterImage(P4205_UNIV2_REGS, UNIV2_IMAGE_6, &imageSpace);
#endif
// Setup VME Master Image 7
enable = false;
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"vmem_ui7", &enable, CONFIG_BOOL);
if (enable)
{
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"vmem_ui7_pa", &base_addr, CONFIG_HEXINT);
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"vmem_ui7_va", &dest_addr, CONFIG_HEXINT);
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"vmem_ui7_vsz", &size, CONFIG_HEXINT);
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"vmem_ui7_uam", &user_am, CONFIG_HEXINT);
CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"vmem_ui7_ucr", &ctl_reg, CONFIG_HEXINT);
imageSpace.CTL = ctl_reg;
imageSpace.BS = base_addr;
imageSpace.BD = imageSpace.BS + size;
imageSpace.TO = dest_addr - imageSpace.BS;
if (ctl_reg & UNIV2_LSICTL_PCI_AS_USER1)
UNIV2SetUserAM1(P4205_UNIV2_REGS, user_am);
else if (ctl_reg & UNIV2_LSICTL_PCI_AS_USER2)
UNIV2SetUserAM2(P4205_UNIV2_REGS, user_am);
}
else
{
imageSpace.CTL = 0;
imageSpace.BS = 0;
imageSpace.BD = 0;
imageSpace.TO = 0;
}
UNIV2SetMasterImage(P4205_UNIV2_REGS, UNIV2_IMAGE_7, &imageSpace);
#endif
}
//
// Initialize the interface - performed at system startup
// This function must set up the interface, including arranging to
// handle interrupts, etc, so that it may be "started" cheaply later.
//
static bool
fec_eth_init(struct cyg_netdevtab_entry *tab)
{
struct eth_drv_sc *sc = (struct eth_drv_sc *)tab->device_instance;
struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private;
volatile EPPC *eppc = (volatile EPPC *)eppc_base();
volatile struct fec *fec = (volatile struct fec *)((unsigned char *)eppc + FEC_OFFSET);
unsigned short phy_state = 0;
int cache_state;
int i;
unsigned long proc_rev;
bool esa_ok, phy_ok;
int phy_timeout = 5*1000; // Wait 5 seconds max for link to clear
// Ensure consistent state between cache and what the FEC sees
HAL_DCACHE_IS_ENABLED(cache_state);
HAL_DCACHE_SYNC();
HAL_DCACHE_DISABLE();
qi->fec = fec;
fec_eth_stop(sc); // Make sure it's not running yet
#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
#ifdef _FEC_USE_INTS
// Set up to handle interrupts
cyg_drv_interrupt_create(FEC_ETH_INT,
CYGARC_SIU_PRIORITY_HIGH,
(cyg_addrword_t)sc, // Data item passed to interrupt handler
(cyg_ISR_t *)fec_eth_isr,
(cyg_DSR_t *)eth_drv_dsr,
&fec_eth_interrupt_handle,
&fec_eth_interrupt);
cyg_drv_interrupt_attach(fec_eth_interrupt_handle);
cyg_drv_interrupt_acknowledge(FEC_ETH_INT);
cyg_drv_interrupt_unmask(FEC_ETH_INT);
#else // _FEC_USE_INTS
// Hack - use a thread to simulate interrupts
cyg_thread_create(1, // Priority
fec_fake_int, // entry
(cyg_addrword_t)sc, // entry parameter
"CS8900 int", // Name
&fec_fake_int_stack[0], // Stack
STACK_SIZE, // Size
&fec_fake_int_thread_handle, // Handle
&fec_fake_int_thread_data // Thread data structure
);
cyg_thread_resume(fec_fake_int_thread_handle); // Start it
#endif
#endif
// Set up parallel port for connection to ethernet tranceiver
eppc->pio_pdpar = 0x1FFF;
CYGARC_MFSPR( CYGARC_REG_PVR, proc_rev );
#define PROC_REVB 0x0020
if ((proc_rev & 0x0000FFFF) == PROC_REVB) {
eppc->pio_pddir = 0x1C58;
} else {
eppc->pio_pddir = 0x1FFF;
}
// Get physical device address
#ifdef CYGPKG_REDBOOT
esa_ok = flash_get_config("fec_esa", enaddr, CONFIG_ESA);
#else
esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"fec_esa", enaddr, CONFIG_ESA);
#endif
if (!esa_ok) {
// Can't figure out ESA
os_printf("FEC_ETH - Warning! ESA unknown\n");
memcpy(&enaddr, &_default_enaddr, sizeof(enaddr));
}
// Configure the device
if (!fec_eth_reset(sc, enaddr, 0)) {
return false;
}
// Reset PHY (transceiver)
eppc->pip_pbdat &= ~0x00004000; // Reset PHY chip
CYGACC_CALL_IF_DELAY_US(10000); // 10ms
eppc->pip_pbdat |= 0x00004000; // Enable PHY chip
// Enable transceiver (PHY)
phy_ok = 0;
phy_write(PHY_BMCR, 0, PHY_BMCR_RESET);
for (i = 0; i < 10; i++) {
phy_ok = phy_read(PHY_BMCR, 0, &phy_state);
if (!phy_ok) break;
if (!(phy_state & PHY_BMCR_RESET)) break;
}
if (!phy_ok || (phy_state & PHY_BMCR_RESET)) {
os_printf("FEC: Can't get PHY unit to reset: %x\n", phy_state);
return false;
}
fec->iEvent = 0xFFFFFFFF; // Clear all interrupts
phy_write(PHY_BMCR, 0, PHY_BMCR_AUTO_NEG|PHY_BMCR_RESTART);
while (phy_timeout-- >= 0) {
int ev = fec->iEvent;
unsigned short state;
fec->iEvent = ev;
if (ev & iEvent_MII) {
phy_ok = phy_read(PHY_BMSR, 0, &state);
if (phy_ok && (state & PHY_BMSR_AUTO_NEG)) {
// os_printf("State: %x\n", state);
break;
} else {
CYGACC_CALL_IF_DELAY_US(1000); // 1ms
}
}
}
if (phy_timeout <= 0) {
os_printf("** FEC Warning: PHY auto-negotiation failed\n");
}
// Initialize upper level driver
(sc->funs->eth_drv->init)(sc, (unsigned char *)&enaddr);
return true;
}
