static void cyg_hal_plf_serial_init(void) { hal_virtual_comm_table_t* comm; int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); // Disable interrupts. HAL_INTERRUPT_MASK(channels[0].isr_vector); HAL_INTERRUPT_MASK(channels[1].isr_vector); // Init channels init_serial_channel(&channels[0]); init_serial_channel(&channels[1]); // Setup procs in the vector table // Set channel 0 CYGACC_CALL_IF_SET_CONSOLE_COMM(0); comm = CYGACC_CALL_IF_CONSOLE_PROCS(); CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[0]); CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write); CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read); CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc); CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc); CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control); CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr); CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout); // Set channel 1 CYGACC_CALL_IF_SET_CONSOLE_COMM(1); comm = CYGACC_CALL_IF_CONSOLE_PROCS(); CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[1]); CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write); CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read); CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc); CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc); CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control); CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr); CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout); // Restore original console CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); }
void cyg_hal_plf_scif_init(int scif_index, int comm_index, int rcv_vect, cyg_uint8* base, bool irda_mode) { channel_data_t* chan = &channels[scif_index]; hal_virtual_comm_table_t* comm; int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); // Initialize channel table chan->base = base; chan->isr_vector = rcv_vect; chan->msec_timeout = 1000; chan->irda_mode = irda_mode; #ifdef CYGHWR_HAL_SH_SH2_SCIF_ASYNC_RXTX chan->async_rxtx_mode = false; #endif // Disable interrupts. HAL_INTERRUPT_MASK(chan->isr_vector); // Init channel cyg_hal_plf_scif_init_channel(chan); // Setup procs in the vector table // Initialize channel procs CYGACC_CALL_IF_SET_CONSOLE_COMM(comm_index); comm = CYGACC_CALL_IF_CONSOLE_PROCS(); CYGACC_COMM_IF_CH_DATA_SET(*comm, chan); CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_scif_write); CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_scif_read); CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_scif_putc); CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_scif_getc); CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_scif_control); CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_scif_isr); CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_scif_getc_timeout); // Restore original console CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); }
static void hal_a2fxxx_serial_init(void) { hal_virtual_comm_table_t* comm; int cur; int i; cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); for( i = 0; i < CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS ; i++ ) { hal_a2fxxx_serial_init_channel(&a2fxxx_ser_channels[i]); CYGACC_CALL_IF_SET_CONSOLE_COMM(i); comm = CYGACC_CALL_IF_CONSOLE_PROCS(); CYGACC_COMM_IF_CH_DATA_SET(*comm, &a2fxxx_ser_channels[i]); CYGACC_COMM_IF_WRITE_SET(*comm, hal_a2fxxx_serial_write); CYGACC_COMM_IF_READ_SET(*comm, hal_a2fxxx_serial_read); CYGACC_COMM_IF_PUTC_SET(*comm, hal_a2fxxx_serial_putc); CYGACC_COMM_IF_GETC_SET(*comm, hal_a2fxxx_serial_getc); CYGACC_COMM_IF_CONTROL_SET(*comm, hal_a2fxxx_serial_control); CYGACC_COMM_IF_DBG_ISR_SET(*comm, hal_a2fxxx_serial_isr); CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, hal_a2fxxx_serial_getc_timeout); } // Restore original console CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); // set debug channel baud rate if different #if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD) a2fxxx_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL]->baud_rate = CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD; update_baud_rate( &a2fxxx_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL] ); #endif }
/* * Early initialization of comm channels. Must not rely * on interrupts, yet. Interrupt operation can be enabled * in _bsp_board_init(). */ void cyg_hal_plf_serial_init(void) { hal_virtual_comm_table_t* comm; int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); static int init = 0; // It's wrong to do this more than once int chan = 0; if (init) return; init++; // Setup procs in the vector table #if CYGNUM_HAL_QUICC_SMC1 > 0 // Set up SMC1 cyg_hal_smcx_init_channel(&ports[chan], QUICC_CPM_SMC1); CYGACC_CALL_IF_SET_CONSOLE_COMM(chan);// Should be configurable! comm = CYGACC_CALL_IF_CONSOLE_PROCS(); CYGACC_COMM_IF_CH_DATA_SET(*comm, &ports[chan]); CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_sxx_write); CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_sxx_read); CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_sxx_putc); CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_sxx_getc); CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_sxx_control); CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_smcx_isr); CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_sxx_getc_timeout); chan++; #endif #if CYGNUM_HAL_QUICC_SMC2 > 0 // Set up SMC2 cyg_hal_smcx_init_channel(&ports[chan], QUICC_CPM_SMC2); CYGACC_CALL_IF_SET_CONSOLE_COMM(chan);// Should be configurable! comm = CYGACC_CALL_IF_CONSOLE_PROCS(); CYGACC_COMM_IF_CH_DATA_SET(*comm, &ports[chan]); CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_sxx_write); CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_sxx_read); CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_sxx_putc); CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_sxx_getc); CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_sxx_control); CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_smcx_isr); CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_sxx_getc_timeout); chan++; #endif #if CYGNUM_HAL_QUICC_SCC1 > 0 // Set up SCC1 cyg_hal_sccx_init_channel(&ports[chan], QUICC_CPM_SCC1); CYGACC_CALL_IF_SET_CONSOLE_COMM(chan);// Should be configurable! comm = CYGACC_CALL_IF_CONSOLE_PROCS(); CYGACC_COMM_IF_CH_DATA_SET(*comm, &ports[chan]); CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_sxx_write); CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_sxx_read); CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_sxx_putc); CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_sxx_getc); CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_sxx_control); CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_sccx_isr); CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_sxx_getc_timeout); chan++; #endif #if CYGNUM_HAL_QUICC_SCC2 > 0 // Set up SCC2 cyg_hal_sccx_init_channel(&ports[chan], QUICC_CPM_SCC2); CYGACC_CALL_IF_SET_CONSOLE_COMM(chan);// Should be configurable! comm = CYGACC_CALL_IF_CONSOLE_PROCS(); CYGACC_COMM_IF_CH_DATA_SET(*comm, &ports[chan]); CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_sxx_write); CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_sxx_read); CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_sxx_putc); CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_sxx_getc); CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_sxx_control); CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_sccx_isr); CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_sxx_getc_timeout); chan++; #endif #if CYGNUM_HAL_QUICC_SCC3 > 0 // Set up SCC3 cyg_hal_sccx_init_channel(&ports[chan], QUICC_CPM_SCC3); CYGACC_CALL_IF_SET_CONSOLE_COMM(chan);// Should be configurable! comm = CYGACC_CALL_IF_CONSOLE_PROCS(); CYGACC_COMM_IF_CH_DATA_SET(*comm, &ports[chan]); CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_sxx_write); CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_sxx_read); CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_sxx_putc); CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_sxx_getc); CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_sxx_control); CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_sccx_isr); CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_sxx_getc_timeout); chan++; #endif // Restore original console CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); }
static void cyg_hal_plf_serial_init(void) { hal_virtual_comm_table_t* comm; int cur; cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); // Init channels cyg_hal_plf_serial_init_channel(&mac7100_ser_channels[0]); #if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1 cyg_hal_plf_serial_init_channel(&mac7100_ser_channels[1]); #endif #if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 2 cyg_hal_plf_serial_init_channel(&mac7100_ser_channels[2]); #endif #if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 3 cyg_hal_plf_serial_init_channel(&mac7100_ser_channels[3]); #endif // Setup procs in the vector table // Set channel 0 CYGACC_CALL_IF_SET_CONSOLE_COMM(0); comm = CYGACC_CALL_IF_CONSOLE_PROCS(); CYGACC_COMM_IF_CH_DATA_SET(*comm, &mac7100_ser_channels[0]); CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write); CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read); CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc); CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc); CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control); CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr); CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout); #if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1 // Set channel 1 CYGACC_CALL_IF_SET_CONSOLE_COMM(1); comm = CYGACC_CALL_IF_CONSOLE_PROCS(); CYGACC_COMM_IF_CH_DATA_SET(*comm, &mac7100_ser_channels[1]); CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write); CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read); CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc); CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc); CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control); CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr); CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout); #endif #if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 2 CYGACC_CALL_IF_SET_CONSOLE_COMM(2); comm = CYGACC_CALL_IF_CONSOLE_PROCS(); CYGACC_COMM_IF_CH_DATA_SET(*comm, &mac7100_ser_channels[2]); CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write); CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read); CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc); CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc); CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control); CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr); CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout); #endif #if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 3 CYGACC_CALL_IF_SET_CONSOLE_COMM(3); comm = CYGACC_CALL_IF_CONSOLE_PROCS(); CYGACC_COMM_IF_CH_DATA_SET(*comm, &mac7100_ser_channels[3]); CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write); CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read); CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc); CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc); CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control); CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr); CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout); #endif // Restore original console CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); }