static void flush_dcache(void *__p, int __nbytes) { CYGARC_HAL_SAVE_GP(); #ifdef HAL_DCACHE_FLUSH HAL_DCACHE_FLUSH( __p , __nbytes ); #elif defined(HAL_DCACHE_INVALIDATE) HAL_DCACHE_INVALIDATE(); #endif CYGARC_HAL_RESTORE_GP(); }
cyg_uint8 cyg_hal_plf_serial_getc(void* __ch_data) { cyg_uint8 ch; CYGARC_HAL_SAVE_GP(); while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch)); CYGARC_HAL_RESTORE_GP(); return ch; }
static void cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf, cyg_uint32 __len) { CYGARC_HAL_SAVE_GP(); while(__len-- > 0) cyg_hal_plf_serial_putc(__ch_data, *__buf++); CYGARC_HAL_RESTORE_GP(); }
static void delay_us(cyg_int32 usecs) { CYGARC_HAL_SAVE_GP(); #ifdef CYGPKG_KERNEL { cyg_int32 start, elapsed; cyg_int32 usec_ticks, slice; // How many ticks total we should wait for. usec_ticks = usecs*CYGNUM_KERNEL_COUNTERS_RTC_PERIOD; usec_ticks /= CYGNUM_HAL_RTC_NUMERATOR/CYGNUM_HAL_RTC_DENOMINATOR/1000; do { // Spin in slices of 1/2 the RTC period. Allows interrupts // time to run without messing up the algorithm. If we spun // for 1 period (or more) of the RTC, there'd be also problems // figuring out when the timer wrapped. We may lose a tick or // two for each cycle but it shouldn't matter much. slice = usec_ticks % (CYGNUM_KERNEL_COUNTERS_RTC_PERIOD / 2); HAL_CLOCK_READ(&start); do { HAL_CLOCK_READ(&elapsed); elapsed = (elapsed - start); // counts up! if (elapsed < 0) elapsed += CYGNUM_KERNEL_COUNTERS_RTC_PERIOD; } while (elapsed < slice); // Adjust by elapsed, not slice, since an interrupt may have // been stalling us for some time. usec_ticks -= elapsed; } while (usec_ticks > 0); } #else // CYGPKG_KERNEL #ifdef HAL_DELAY_US // Use a HAL feature if defined HAL_DELAY_US(usecs); #else // If no accurate delay mechanism, just spin for a while. Having // an inaccurate delay is much better than no delay at all. The // count of 10 should mean the loop takes something resembling // 1us on most CPUs running between 30-100MHz [depends on how many // instructions this compiles to, how many dispatch units can be // used for the simple loop, actual CPU frequency, etc] while (usecs-- > 0) { int i; for (i = 0; i < 10; i++); } #endif // HAL_DELAY_US #endif // CYGPKG_KERNEL CYGARC_HAL_RESTORE_GP(); }
static int cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...) { static int irq_state = 0; channel_data_t* chan = (channel_data_t*)__ch_data; int ret = 0; va_list ap; CYGARC_HAL_SAVE_GP(); va_start(ap, __func); switch (__func) { case __COMMCTL_GETBAUD: ret = chan->baud_rate; break; case __COMMCTL_SETBAUD: chan->baud_rate = va_arg(ap, cyg_int32); // Should we verify this value here? cyg_hal_plf_serial_init_channel(chan); ret = 0; break; case __COMMCTL_IRQ_ENABLE: irq_state = 1; HAL_INTERRUPT_UNMASK(chan->isr_vector); break; case __COMMCTL_IRQ_DISABLE: ret = irq_state; irq_state = 0; HAL_INTERRUPT_MASK(chan->isr_vector); break; case __COMMCTL_DBG_ISR_VECTOR: ret = chan->isr_vector; break; case __COMMCTL_SET_TIMEOUT: { va_list ap; va_start(ap, __func); ret = chan->msec_timeout; chan->msec_timeout = va_arg(ap, cyg_uint32); va_end(ap); } default: break; } va_end(ap); CYGARC_HAL_RESTORE_GP(); return ret; }
static int cyg_hal_diag_mangler_gdb_control(void *__ch_data, __comm_control_cmd_t __func, ...) { CYGARC_HAL_SAVE_GP(); if (__func == __COMMCTL_FLUSH_OUTPUT) cyg_hal_diag_mangler_gdb_flush(__ch_data); CYGARC_HAL_RESTORE_GP(); return 0; }
static int cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...) { static int irq_state = 0; channel_data_t* chan = (channel_data_t*)__ch_data; int ret = -1; cyg_uint8 ier; va_list ap; CYGARC_HAL_SAVE_GP(); va_start(ap, __func); switch (__func) { case __COMMCTL_GETBAUD: ret = chan->baud_rate; break; case __COMMCTL_SETBAUD: chan->baud_rate = va_arg(ap, cyg_int32); // Should we verify this value here? init_channel(chan); ret = 0; break; case __COMMCTL_IRQ_ENABLE: HAL_INTERRUPT_UNMASK(chan->isr_vector); HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1); HAL_READ_UINT8(chan->base+PXA2X0_UART_IER, ier); ier |= PXA2X0_UART_IER_RAVIE; HAL_WRITE_UINT8(chan->base+PXA2X0_UART_IER, ier); irq_state = 1; break; case __COMMCTL_IRQ_DISABLE: ret = irq_state; irq_state = 0; HAL_INTERRUPT_MASK(chan->isr_vector); HAL_READ_UINT8(chan->base+PXA2X0_UART_IER, ier); ier &= ~PXA2X0_UART_IER_RAVIE; HAL_WRITE_UINT8(chan->base+PXA2X0_UART_IER, ier); break; case __COMMCTL_DBG_ISR_VECTOR: ret = chan->isr_vector; break; case __COMMCTL_SET_TIMEOUT: ret = chan->msec_timeout; chan->msec_timeout = va_arg(ap, cyg_uint32); break; default: break; } va_end(ap); CYGARC_HAL_RESTORE_GP(); return ret; }
static void return_to_redboot(int status) { CYGARC_HAL_SAVE_GP(); return_status = status; HAL_THREAD_LOAD_CONTEXT(&saved_context); // never returns // need this to balance above CYGARC_HAL_SAVE_GP on // some platforms. It will never run, though. CYGARC_HAL_RESTORE_GP(); }
// This gets called via the virtual vector console comms entry and // just forwards IO to the debug comms entries. // This differs from setting the console channel to the same as the // debug channel in that console output will go to the debug channel // even if the debug channel is changed. static cyg_uint8 cyg_hal_diag_mangler_null_getc(void* __ch_data) { cyg_uint8 __ch; hal_virtual_comm_table_t* __chan = CYGACC_CALL_IF_DEBUG_PROCS(); CYGARC_HAL_SAVE_GP(); __ch = CYGACC_COMM_IF_GETC(*__chan); CYGARC_HAL_RESTORE_GP(); return __ch; }
static int dbg_thread_syscall_rmt( enum dbg_syscall_ids id, union dbg_thread_syscall_parms * p ) { int ret; CYGARC_HAL_SAVE_GP(); switch (id) { case dbg_null_func : ret = 1 ; /* test the syscall apparatus */ break; #ifdef CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT case dbg_capabilities_func : ret = dbg_thread_capabilities(p->cap_parms.abilities) ; break ; case dbg_currthread_func : ret = dbg_currthread(p->currthread_parms.ref) ; break ; case dbg_threadlist_func : ret = dbg_threadlist(p->threadlist_parms.startflag, p->threadlist_parms.lastid, p->threadlist_parms.nextthreadid) ; break ; case dbg_threadinfo_func : ret = dbg_threadinfo(p->info_parms.ref, p->info_parms.info ) ; break ; case dbg_getthreadreg_func : ret = dbg_getthreadreg(p->reg_parms.thread, p->reg_parms.regcount, p->reg_parms.registers) ; break ; case dbg_setthreadreg_func : ret = dbg_setthreadreg(p->reg_parms.thread, p->reg_parms.regcount, p->reg_parms.registers) ; break ; case dbg_scheduler_func : ret = dbg_scheduler(p->scheduler_parms.thread, p->scheduler_parms.lock, p->scheduler_parms.mode) ; break ; #endif /* CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT */ default : ret = 0 ; /* failure due to non-implementation */ } CYGARC_HAL_RESTORE_GP(); return ret; }
void install_async_breakpoint(void *epc) { CYGARC_HAL_SAVE_GP(); asyncBuffer.targetAddr = epc; asyncBuffer.savedInstr = *(t_inst *)epc; *(t_inst *)epc = *(t_inst *)_breakinst; HAL_DCACHE_SYNC(); HAL_ICACHE_SYNC(); CYGARC_HAL_RESTORE_GP(); }
static void cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len) { CYGARC_HAL_SAVE_GP(); // Some of the diagnostic print code calls through here with no idea what the ch_data is. // Go ahead and assume it is channels[0]. if (__ch_data == 0) __ch_data = (void*)&channels[0]; while(__len-- > 0) *__buf++ = cyg_hal_plf_serial_getc(__ch_data); CYGARC_HAL_RESTORE_GP(); }
static int cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...) { static int irq_state = 0; channel_data_t* chan = (channel_data_t*)__ch_data; int ret = 0; cyg_uint8 status; CYGARC_HAL_SAVE_GP(); switch (__func) { case __COMMCTL_IRQ_ENABLE: irq_state = 1; // Ensure that only Receive ints are generated. status = IO_READ(chan->base + AMBA_UARTCR); status |= (AMBA_UARTCR_RTIE | AMBA_UARTCR_RIE); HAL_WRITE_UINT32(chan->base + AMBA_UARTCR, status); HAL_INTERRUPT_UNMASK(chan->isr_vector); break; case __COMMCTL_IRQ_DISABLE: ret = irq_state; irq_state = 0; status = IO_READ(chan->base + AMBA_UARTCR); status &= ~(AMBA_UARTCR_RTIE | AMBA_UARTCR_TIE | AMBA_UARTCR_RIE | AMBA_UARTCR_MSIE); HAL_WRITE_UINT32(chan->base + AMBA_UARTCR, status); HAL_INTERRUPT_MASK(chan->isr_vector); break; case __COMMCTL_DBG_ISR_VECTOR: ret = chan->isr_vector; break; case __COMMCTL_SET_TIMEOUT: { va_list ap; va_start(ap, __func); ret = chan->msec_timeout; chan->msec_timeout = va_arg(ap, cyg_uint32); va_end(ap); } default: break; } CYGARC_HAL_RESTORE_GP(); return ret; }
static int cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...) { static int irq_state = 0; channel_data_t* chan = (channel_data_t*)__ch_data; cyg_uint8 ier; int ret = 0; CYGARC_HAL_SAVE_GP(); switch (__func) { case __COMMCTL_IRQ_ENABLE: irq_state = 1; HAL_READ_UINT8(chan->base+CYG_DEVICE_BK0_IER, ier); ier |= CYG_DEVICE_BK0_IER_RXHDL_IE; HAL_WRITE_UINT8(chan->base+CYG_DEVICE_BK0_IER, ier); HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1); HAL_INTERRUPT_UNMASK(chan->isr_vector); break; case __COMMCTL_IRQ_DISABLE: ret = irq_state; irq_state = 0; HAL_READ_UINT8(chan->base+CYG_DEVICE_BK0_IER, ier); ier &= ~CYG_DEVICE_BK0_IER_RXHDL_IE; HAL_WRITE_UINT8(chan->base+CYG_DEVICE_BK0_IER, ier); HAL_INTERRUPT_MASK(chan->isr_vector); break; case __COMMCTL_DBG_ISR_VECTOR: ret = chan->isr_vector; break; case __COMMCTL_SET_TIMEOUT: { va_list ap; va_start(ap, __func); ret = chan->msec_timeout; chan->msec_timeout = va_arg(ap, cyg_uint32); va_end(ap); } default: break; } CYGARC_HAL_RESTORE_GP(); return ret; }
void cyg_hal_plf_serial_putc(void *__ch_data, char c) { cyg_uint8* base = ((channel_data_t*)__ch_data)->base; CYGARC_HAL_SAVE_GP(); FLOWCTL_SET(DTR); cyg_hal_plf_serial_putc_aux(base,c); FLOWCTL_CLEAR(DTR); CYGARC_HAL_RESTORE_GP(); }
//=========================================================================== // Write single character //=========================================================================== void cyg_hal_plf_serial_putc(void *__ch_data, char c) { cyg_uint8* base = ((channel_data_t*)__ch_data)->base; cyg_uint8 stat; CYGARC_HAL_SAVE_GP(); do { HAL_READ_UINT32(base + CYGARC_HAL_LPC24XX_REG_UxLSR, stat); } while ((stat & CYGARC_HAL_LPC24XX_REG_UxLSR_THRE) == 0); HAL_WRITE_UINT32(base + CYGARC_HAL_LPC24XX_REG_UxTHR, c); CYGARC_HAL_RESTORE_GP(); }
void cyg_hal_plf_serial_putc(void *__ch_data, char c) { channel_data_t* chan = (channel_data_t*)__ch_data; CYGARC_HAL_SAVE_GP(); // Wait for Tx FIFO not full while ((chan->base->stat & SYSFLG1_UTXFF1) != 0) ; chan->base->data.write = c; CYGARC_HAL_RESTORE_GP(); }
cyg_uint8 cyg_hal_plf_serial_getc(void* __ch_data) { cyg_uint8 ch; CYGARC_HAL_SAVE_GP(); // Some of the diagnostic print code calls through here with no idea what the ch_data is. // Go ahead and assume it is channels[0]. if (__ch_data == 0) __ch_data = (void*)&channels[0]; while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch)); CYGARC_HAL_RESTORE_GP(); return ch; }
static void cyg_hal_diag_mangler_gdb_putc(void* __ch_data, cyg_uint8 c) { // No need to send CRs if( c == '\r' ) return; CYGARC_HAL_SAVE_GP(); __mangler_line[__mangler_pos++] = c; if( c == '\n' || __mangler_pos == sizeof(__mangler_line) ) cyg_hal_diag_mangler_gdb_flush(__ch_data); CYGARC_HAL_RESTORE_GP(); }
void cyg_hal_plf_serial_putc(void *__ch_data, char c) { cyg_uint8* base = ((channel_data_t*)__ch_data)->base; cyg_uint8 lsr; CYGARC_HAL_SAVE_GP(); do { HAL_READ_UINT8(base+CYG_DEV_LSR, lsr); } while ((lsr & SIO_LSR_THRE) == 0); HAL_WRITE_UINT8(base+CYG_DEV_THR, c); CYGARC_HAL_RESTORE_GP(); }
void cyg_hal_plf_serial_putc(void *__ch_data, char c) { cyg_uint8* base = ((channel_data_t*)__ch_data)->base; cyg_uint32 status, ch; CYGARC_HAL_SAVE_GP(); do { HAL_READ_UINT32(base+AT91_US_CSR, status); } while ((status & AT91_US_CSR_TxRDY) == 0); ch = (cyg_uint32)c; HAL_WRITE_UINT32(base+AT91_US_THR, ch); CYGARC_HAL_RESTORE_GP(); }
void cyg_hal_plf_serial_putc(void *__ch_data, char c) { cyg_uint8* base = ((channel_data_t*)__ch_data)->base; cyg_uint32 status, ch; CYGARC_HAL_SAVE_GP(); do { HAL_READ_UINT32(base+E7T_UART_STAT, status); } while ((status & E7T_UART_STAT_TXE) == 0); ch = (cyg_uint32)c; HAL_WRITE_UINT32(base+E7T_UART_TXBUF, ch); CYGARC_HAL_RESTORE_GP(); }
void hal_a2fxxx_serial_putc(void *__ch_data, char c) { CYG_ADDRESS base = ((channel_data_t*)__ch_data)->base; cyg_uint32 lsr; CYGARC_HAL_SAVE_GP(); do { HAL_READ_UINT32(base + CYGHWR_HAL_A2FXXX_UART16550_LSR, lsr ); } while ((lsr & CYGHWR_HAL_A2FXXX_UART16550_LSR_THRE) == 0); HAL_WRITE_UINT32(base + CYGHWR_HAL_A2FXXX_UART16550_THR, c ); CYGARC_HAL_RESTORE_GP(); }
void hal_stm32_serial_putc(void *__ch_data, char c) { CYG_ADDRESS base = ((channel_data_t*)__ch_data)->base; cyg_uint32 sr; CYGARC_HAL_SAVE_GP(); do { HAL_READ_UINT32( base + CYGHWR_HAL_STM32_UART_SR, sr ); } while ((sr & CYGHWR_HAL_STM32_UART_SR_TXE) == 0); HAL_WRITE_UINT32( base + CYGHWR_HAL_STM32_UART_DR, c ); CYGARC_HAL_RESTORE_GP(); }
static void cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf, cyg_uint32 __len) { cyg_uint8* base = ((channel_data_t*)__ch_data)->base; CYGARC_HAL_SAVE_GP(); FLOWCTL_SET(DTR); while(__len-- > 0) cyg_hal_plf_serial_putc_aux(__ch_data, *__buf++); FLOWCTL_CLEAR(DTR); CYGARC_HAL_RESTORE_GP(); }
static int net_io_isr(void *__ch_data, int* __ctrlc, CYG_ADDRWORD __vector, CYG_ADDRWORD __data) { char ch; CYGARC_HAL_SAVE_GP(); *__ctrlc = 0; if (net_io_getc_nonblock(__ch_data, &ch)) { if (ch == 0x03) { *__ctrlc = 1; } } CYGARC_HAL_RESTORE_GP(); return CYG_ISR_HANDLED; }
static cyg_bool flash_fis_op( int op, char *name, void *val) { cyg_bool res = false; struct fis_image_desc *fis; int num; CYGARC_HAL_SAVE_GP(); fis = fis_lookup(name, &num); if(fis != NULL) { switch ( op ) { case CYGNUM_CALL_IF_FLASH_FIS_GET_FLASH_BASE: *(CYG_ADDRESS *)val = fis->flash_base; res = true; break; case CYGNUM_CALL_IF_FLASH_FIS_GET_SIZE: *(unsigned long *)val = fis->size; res = true; break; case CYGNUM_CALL_IF_FLASH_FIS_GET_MEM_BASE: *(CYG_ADDRESS *)val = fis->mem_base; res = true; break; case CYGNUM_CALL_IF_FLASH_FIS_GET_ENTRY_POINT: *(CYG_ADDRESS *)val = fis->entry_point; res = true; break; case CYGNUM_CALL_IF_FLASH_FIS_GET_DATA_LENGTH: *(unsigned long *)val = fis->data_length; res = true; break; case CYGNUM_CALL_IF_FLASH_FIS_GET_DESC_CKSUM: *(unsigned long *)val = fis->desc_cksum; res = true; break; case CYGNUM_CALL_IF_FLASH_FIS_GET_FILE_CKSUM: *(unsigned long *)val = fis->file_cksum; res = true; break; default: break; } } CYGARC_HAL_RESTORE_GP(); return res; }
static int cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...) { static int irq_state = 0; cyg_uint32 intm; channel_data_t* chan = (channel_data_t*)__ch_data; cyg_uint8* base = ((channel_data_t*)__ch_data)->base; int ret = 0; CYGARC_HAL_SAVE_GP(); switch (__func) { case __COMMCTL_IRQ_ENABLE: irq_state = 1; HAL_READ_UINT32(base+AAEC_UART_INTM, intm); intm |= AAEC_UART_INT_RIS|AAEC_UART_INT_RTIS; HAL_WRITE_UINT32(base+AAEC_UART_INTM, intm); HAL_INTERRUPT_UNMASK(chan->isr_vector); break; case __COMMCTL_IRQ_DISABLE: ret = irq_state; irq_state = 0; HAL_READ_UINT32(base+AAEC_UART_INTM, intm); intm &= ~(AAEC_UART_INT_RIS|AAEC_UART_INT_RTIS); HAL_WRITE_UINT32(base+AAEC_UART_INTM, intm); HAL_INTERRUPT_MASK(chan->isr_vector); break; case __COMMCTL_DBG_ISR_VECTOR: ret = chan->isr_vector; break; case __COMMCTL_SET_TIMEOUT: { va_list ap; va_start(ap, __func); ret = chan->msec_timeout; chan->msec_timeout = va_arg(ap, cyg_uint32); va_end(ap); } default: break; } CYGARC_HAL_RESTORE_GP(); return ret; }
static int set_console_comm(int __comm_id) { static int __selected_id = CYGNUM_CALL_IF_SET_COMM_ID_EMPTY; int res = 1, update = 0; CYGARC_HAL_SAVE_GP(); CYG_ASSERT(__comm_id >= CYGNUM_CALL_IF_SET_COMM_ID_MANGLER && __comm_id < CYGNUM_HAL_VIRTUAL_VECTOR_NUM_CHANNELS, "Invalid channel"); switch (__comm_id) { case CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT: if (__selected_id > 0) res = __selected_id-1; else if (__selected_id == 0) res = CYGNUM_CALL_IF_SET_COMM_ID_MANGLER; else res = __selected_id; break; case CYGNUM_CALL_IF_SET_COMM_ID_EMPTY: CYGACC_CALL_IF_CONSOLE_PROCS_SET(0); __selected_id = __comm_id; break; case CYGNUM_CALL_IF_SET_COMM_ID_MANGLER: __comm_id = 0; update = 1; break; default: __comm_id++; // skip mangler entry update = 1; break; } if (update) { __selected_id = __comm_id; CYGACC_CALL_IF_CONSOLE_PROCS_SET(comm_channels[__comm_id]); } CYGARC_HAL_RESTORE_GP(); return res; }
void CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR cyg_hal_plf_serial_putc(void* __ch_data, char ch_out) { channel_data_t* chan = (channel_data_t*)__ch_data; CYG_ADDRESS uart_p = (CYG_ADDRESS) chan->base; cyg_uint32 uart_s1; CYGARC_HAL_SAVE_GP(); do { HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_S1, uart_s1); } while (!(uart_s1 & CYGHWR_DEV_FREESCALE_UART_S1_TDRE)); HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_D, ch_out); CYGARC_HAL_RESTORE_GP(); }