void
malo_cardbus_attach(struct device *parent, struct device *self, void *aux)
{
struct malo_cardbus_softc *csc = (struct malo_cardbus_softc *)self;
struct cardbus_attach_args *ca = aux;
struct malo_softc *sc = &csc->sc_malo;
cardbus_devfunc_t ct = ca->ca_ct;
bus_addr_t base;
int error;
sc->sc_dmat = ca->ca_dmat;
csc->sc_ct = ct;
csc->sc_tag = ca->ca_tag;
csc->sc_intrline = ca->ca_intrline;
/* power management hooks */
sc->sc_enable = malo_cardbus_enable;
sc->sc_disable = malo_cardbus_disable;
#if 0
sc->sc_power = malo_cardbus_power;
#endif
/* map control/status registers */
error = Cardbus_mapreg_map(ct, CARDBUS_BASE0_REG,
CARDBUS_MAPREG_TYPE_MEM, 0, &sc->sc_mem1_bt,
&sc->sc_mem1_bh, &base, &csc->sc_mapsize1);
if (error != 0) {
printf(": could not map 1st memory space\n");
return;
}
csc->sc_bar1_val = base | CARDBUS_MAPREG_TYPE_MEM;
/* map control/status registers */
error = Cardbus_mapreg_map(ct, CARDBUS_BASE1_REG,
CARDBUS_MAPREG_TYPE_MEM, 0, &sc->sc_mem2_bt,
&sc->sc_mem2_bh, &base, &csc->sc_mapsize2);
if (error != 0) {
printf(": could not map 2nd memory space\n");
Cardbus_mapreg_unmap(ct, CARDBUS_BASE0_REG, sc->sc_mem1_bt,
sc->sc_mem1_bh, csc->sc_mapsize1);
return;
}
csc->sc_bar2_val = base | CARDBUS_MAPREG_TYPE_MEM;
/* set up the PCI configuration registers */
malo_cardbus_setup(csc);
printf(": irq %d", csc->sc_intrline);
error = malo_attach(sc);
if (error != 0)
malo_cardbus_detach(&sc->sc_dev, 0);
Cardbus_function_disable(ct);
}
static void
fxp_cardbus_attach(struct device *parent, struct device *self,
void *aux)
{
struct fxp_cardbus_softc *csc = device_private(self);
struct fxp_softc *sc = &csc->sc;
struct cardbus_attach_args *ca = aux;
bus_space_tag_t iot, memt;
bus_space_handle_t ioh, memh;
bus_addr_t adr;
bus_size_t size;
sc->sc_dev = self;
csc->ct = ca->ca_ct;
/*
* Map control/status registers.
*/
if (Cardbus_mapreg_map(csc->ct, CARDBUS_BASE1_REG,
PCI_MAPREG_TYPE_IO, 0, &iot, &ioh, &adr, &size) == 0) {
csc->base1_reg = adr | 1;
sc->sc_st = iot;
sc->sc_sh = ioh;
csc->size = size;
} else if (Cardbus_mapreg_map(csc->ct, CARDBUS_BASE0_REG,
PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT,
0, &memt, &memh, &adr, &size) == 0) {
csc->base0_reg = adr;
sc->sc_st = memt;
sc->sc_sh = memh;
csc->size = size;
} else
panic("%s: failed to allocate mem and io space", __func__);
if (ca->ca_cis.cis1_info[0] && ca->ca_cis.cis1_info[1])
printf(": %s %s\n", ca->ca_cis.cis1_info[0],
ca->ca_cis.cis1_info[1]);
else
printf("\n");
sc->sc_dmat = ca->ca_dmat;
sc->sc_enable = fxp_cardbus_enable;
sc->sc_disable = fxp_cardbus_disable;
sc->sc_enabled = 0;
fxp_enable(sc);
fxp_attach(sc);
fxp_disable(sc);
if (!pmf_device_register(self, NULL, NULL))
aprint_error_dev(self, "couldn't establish power handler\n");
else
pmf_class_network_register(self, &sc->sc_ethercom.ec_if);
}
/*
* Attach the interface. Allocate softc structures, do ifmedia
* setup and ethernet/BPF attach.
*/
void
re_cardbus_attach(struct device *parent, struct device *self, void *aux)
{
struct re_cardbus_softc *csc = (struct re_cardbus_softc *)self;
struct rl_softc *sc = &csc->sc_rl;
struct cardbus_attach_args *ca = aux;
struct cardbus_softc *psc =
(struct cardbus_softc *)sc->sc_dev.dv_parent;
cardbus_chipset_tag_t cc = psc->sc_cc;
cardbus_function_tag_t cf = psc->sc_cf;
cardbus_devfunc_t ct = ca->ca_ct;
bus_addr_t adr;
char intrstr[16];
sc->sc_dmat = ca->ca_dmat;
csc->ct = ct;
csc->sc_tag = ca->ca_tag;
csc->sc_pc = ca->ca_pc;
csc->sc_intrline = ca->ca_intrline;
/*
* Map control/status registers.
*/
if (Cardbus_mapreg_map(ct, RL_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0,
&sc->rl_btag, &sc->rl_bhandle, &adr, &csc->sc_mapsize) == 0) {
csc->sc_cben = CARDBUS_MEM_ENABLE;
csc->sc_csr |= PCI_COMMAND_MEM_ENABLE;
csc->sc_bar_reg = RL_PCI_LOMEM;
csc->sc_bar_val = adr | PCI_MAPREG_TYPE_MEM;
} else {
printf(": can't map mem space\n");
return;
}
/* Enable power */
Cardbus_function_enable(ct);
/* Get chip out of powersave mode (if applicable), initialize
* config registers */
re_cardbus_setup(sc);
/* Allocate interrupt */
csc->sc_ih = cardbus_intr_establish(cc, cf, csc->sc_intrline,
IPL_NET, re_intr, sc, sc->sc_dev.dv_xname);
if (csc->sc_ih == NULL) {
printf(": couldn't establish interrupt at %d",
ca->ca_intrline);
Cardbus_function_disable(csc->ct);
return;
}
snprintf(intrstr, sizeof(intrstr), "irq %d", ca->ca_intrline);
/* Call bus-independent (common) attach routine */
if (re_attach(sc, intrstr)) {
cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, csc->sc_ih);
Cardbus_mapreg_unmap(ct, csc->sc_bar_reg, sc->rl_btag,
sc->rl_bhandle, csc->sc_mapsize);
}
}
void
ral_cardbus_attach(struct device *parent, struct device *self, void *aux)
{
struct ral_cardbus_softc *csc = (struct ral_cardbus_softc *)self;
struct rt2560_softc *sc = &csc->sc_sc;
struct cardbus_attach_args *ca = aux;
cardbus_devfunc_t ct = ca->ca_ct;
bus_addr_t base;
int error;
if (PCI_VENDOR(ca->ca_id) == PCI_VENDOR_RALINK) {
switch (PCI_PRODUCT(ca->ca_id)) {
case PCI_PRODUCT_RALINK_RT2560:
csc->sc_opns = &ral_rt2560_opns;
break;
case PCI_PRODUCT_RALINK_RT2561:
case PCI_PRODUCT_RALINK_RT2561S:
case PCI_PRODUCT_RALINK_RT2661:
csc->sc_opns = &ral_rt2661_opns;
break;
default:
csc->sc_opns = &ral_rt2860_opns;
break;
}
} else {
/* all other vendors are RT2860 only */
csc->sc_opns = &ral_rt2860_opns;
}
sc->sc_dmat = ca->ca_dmat;
csc->sc_ct = ct;
csc->sc_tag = ca->ca_tag;
csc->sc_intrline = ca->ca_intrline;
csc->sc_pc = ca->ca_pc;
/* power management hooks */
sc->sc_enable = ral_cardbus_enable;
sc->sc_disable = ral_cardbus_disable;
/* map control/status registers */
error = Cardbus_mapreg_map(ct, CARDBUS_BASE0_REG,
PCI_MAPREG_TYPE_MEM, 0, &sc->sc_st, &sc->sc_sh, &base,
&csc->sc_mapsize);
if (error != 0) {
printf(": can't map mem space\n");
return;
}
csc->sc_bar_val = base | PCI_MAPREG_TYPE_MEM;
/* set up the PCI configuration registers */
ral_cardbus_setup(csc);
printf(": irq %d", csc->sc_intrline);
(*csc->sc_opns->attach)(sc, PCI_PRODUCT(ca->ca_id));
Cardbus_function_disable(ct);
}
void
ath_cardbus_attach(device_t parent, device_t self, void *aux)
{
struct ath_cardbus_softc *csc = device_private(self);
struct ath_softc *sc = &csc->sc_ath;
struct cardbus_attach_args *ca = aux;
cardbus_devfunc_t ct = ca->ca_ct;
bus_addr_t adr;
sc->sc_dev = self;
sc->sc_dmat = ca->ca_dmat;
csc->sc_ct = ct;
csc->sc_tag = ca->ca_tag;
aprint_normal("\n");
/*
* Map the device.
*/
if (Cardbus_mapreg_map(ct, ATH_PCI_MMBA, PCI_MAPREG_TYPE_MEM, 0,
&csc->sc_iot, &csc->sc_ioh, &adr, &csc->sc_mapsize) == 0) {
#if rbus
#else
(*ct->ct_cf->cardbus_mem_open)(cc, 0, adr, adr+csc->sc_mapsize);
#endif
csc->sc_bar_val = adr | PCI_MAPREG_TYPE_MEM;
} else {
aprint_error_dev(self, "unable to map device registers\n");
return;
}
sc->sc_st = HALTAG(csc->sc_iot);
sc->sc_sh = HALHANDLE(csc->sc_ioh);
/*
* Set up the PCI configuration registers.
*/
ath_cardbus_setup(csc);
/* Remember which interrupt line. */
csc->sc_intrline = ca->ca_intrline;
ATH_LOCK_INIT(sc);
/*
* Finish off the attach.
*/
if (ath_attach(PCI_PRODUCT(ca->ca_id), sc) != 0)
return;
if (!pmf_device_register(self, ath_cardbus_suspend, ath_cardbus_resume))
aprint_error_dev(self, "couldn't establish power handler\n");
else {
pmf_class_network_register(self, &sc->sc_if);
pmf_device_suspend_self(self);
}
}
void
com_cardbus_attach(struct device *parent, struct device *self, void *aux)
{
struct com_softc *sc = (struct com_softc*)self;
struct com_cardbus_softc *csc = (struct com_cardbus_softc*)self;
struct cardbus_attach_args *ca = aux;
csc->cc_ct = ca->ca_ct;
csc->cc_tag = Cardbus_make_tag(csc->cc_ct);
if (com_cardbus_gofigure(ca, csc) != 0)
return;
if (Cardbus_mapreg_map(ca->ca_ct, csc->cc_reg, csc->cc_type, 0,
&sc->sc_iot, &sc->sc_ioh, &csc->cc_addr, &csc->cc_size) != 0) {
printf("failed to map memory");
return;
}
csc->cc_base = csc->cc_addr;
csc->cc_csr = CARDBUS_COMMAND_MASTER_ENABLE;
if (csc->cc_type == CARDBUS_MAPREG_TYPE_IO) {
csc->cc_base |= CARDBUS_MAPREG_TYPE_IO;
csc->cc_csr |= CARDBUS_COMMAND_IO_ENABLE;
csc->cc_cben = CARDBUS_IO_ENABLE;
} else {
csc->cc_csr |= CARDBUS_COMMAND_MEM_ENABLE;
csc->cc_cben = CARDBUS_MEM_ENABLE;
}
sc->sc_iobase = csc->cc_addr;
sc->sc_frequency = COM_FREQ;
sc->enable = com_cardbus_enable;
sc->disable = com_cardbus_disable;
sc->enabled = 0;
if (ca->ca_cis.cis1_info[0] && ca->ca_cis.cis1_info[1]) {
printf(": %s %s\n", ca->ca_cis.cis1_info[0],
ca->ca_cis.cis1_info[1]);
printf("%s", DEVNAME(csc));
}
if (com_cardbus_enable(sc))
printf(": function enable failed\n");
sc->enabled = 1;
sc->sc_hwflags = 0;
sc->sc_swflags = 0;
if (csc->cc_bug & BUG_BROADCOM)
sc->sc_fifolen = 15;
com_attach_subr(sc);
}
void
ral_cardbus_attach(struct device *parent, struct device *self,
void *aux)
{
struct ral_cardbus_softc *csc = (struct ral_cardbus_softc *)self;
struct rt2560_softc *sc = &csc->sc_sc;
struct cardbus_attach_args *ca = aux;
cardbus_devfunc_t ct = ca->ca_ct;
char devinfo[256];
bus_addr_t base;
int error, revision;
pci_devinfo(ca->ca_id, ca->ca_class, 0, devinfo, sizeof(devinfo));
revision = PCI_REVISION(ca->ca_class);
aprint_normal(": %s (rev. 0x%02x)\n", devinfo, revision);
csc->sc_opns =
(CARDBUS_PRODUCT(ca->ca_id) == PCI_PRODUCT_RALINK_RT2560) ?
&ral_rt2560_opns : &ral_rt2661_opns;
sc->sc_dmat = ca->ca_dmat;
csc->sc_ct = ct;
csc->sc_tag = ca->ca_tag;
csc->sc_intrline = ca->ca_intrline;
/* power management hooks */
sc->sc_enable = ral_cardbus_enable;
sc->sc_disable = ral_cardbus_disable;
/* map control/status registers */
error = Cardbus_mapreg_map(ct, CARDBUS_BASE0_REG,
CARDBUS_MAPREG_TYPE_MEM, 0, &sc->sc_st, &sc->sc_sh, &base,
&csc->sc_mapsize);
if (error != 0) {
printf(": could not map memory space\n");
return;
}
#if rbus
#else
(*cf->cardbus_mem_open)(cc, 0, base, base + csc->sc_mapsize);
#endif
csc->sc_bar_val = base | CARDBUS_MAPREG_TYPE_MEM;
/* set up the PCI configuration registers */
ral_cardbus_setup(csc);
(*csc->sc_opns->attach)(sc, CARDBUS_PRODUCT(ca->ca_id));
Cardbus_function_disable(ct);
}
void
pgt_cardbus_attach(struct device *parent, struct device *self, void *aux)
{
struct pgt_cardbus_softc *csc = (struct pgt_cardbus_softc *)self;
struct pgt_softc *sc = &csc->sc_pgt;
struct cardbus_attach_args *ca = aux;
cardbus_devfunc_t ct = ca->ca_ct;
bus_addr_t base;
int error;
sc->sc_dmat = ca->ca_dmat;
csc->sc_ct = ct;
csc->sc_tag = ca->ca_tag;
csc->sc_intrline = ca->ca_intrline;
csc->sc_pc = ca->ca_pc;
/* power management hooks */
sc->sc_enable = pgt_cardbus_enable;
sc->sc_disable = pgt_cardbus_disable;
sc->sc_power = pgt_cardbus_power;
/* remember chipset */
if (PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_INTERSIL_ISL3877)
sc->sc_flags |= SC_ISL3877;
/* map control / status registers */
error = Cardbus_mapreg_map(ct, CARDBUS_BASE0_REG,
PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0,
&sc->sc_iotag, &sc->sc_iohandle, &base, &csc->sc_mapsize);
if (error != 0) {
printf(": can't map mem space\n");
return;
}
csc->sc_bar0_val = base | PCI_MAPREG_TYPE_MEM;
/* disable all interrupts */
bus_space_write_4(sc->sc_iotag, sc->sc_iohandle, PGT_REG_INT_EN, 0);
(void)bus_space_read_4(sc->sc_iotag, sc->sc_iohandle, PGT_REG_INT_EN);
DELAY(PGT_WRITEIO_DELAY);
/* set up the PCI configuration registers */
pgt_cardbus_setup(csc);
printf(": irq %d\n", csc->sc_intrline);
if (rootvp == NULL)
mountroothook_establish(pgt_attach, sc);
else
pgt_attach(sc);
}
void
ral_cardbus_attach(device_t parent, device_t self, void *aux)
{
struct ral_cardbus_softc *csc = device_private(self);
struct rt2560_softc *sc = &csc->sc_sc;
struct cardbus_attach_args *ca = aux;
cardbus_devfunc_t ct = ca->ca_ct;
char devinfo[256];
bus_addr_t base;
int error, revision;
pci_devinfo(ca->ca_id, ca->ca_class, 0, devinfo, sizeof(devinfo));
revision = PCI_REVISION(ca->ca_class);
aprint_normal(": %s (rev. 0x%02x)\n", devinfo, revision);
csc->sc_opns =
(PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_RALINK_RT2560) ?
&ral_rt2560_opns : &ral_rt2661_opns;
sc->sc_dev = self;
sc->sc_dmat = ca->ca_dmat;
csc->sc_ct = ct;
csc->sc_tag = ca->ca_tag;
/* power management hooks */
sc->sc_enable = ral_cardbus_enable;
sc->sc_disable = ral_cardbus_disable;
/* map control/status registers */
error = Cardbus_mapreg_map(ct, PCI_BAR0,
PCI_MAPREG_TYPE_MEM, 0, &sc->sc_st, &sc->sc_sh, &base,
&csc->sc_mapsize);
if (error != 0) {
aprint_error(": could not map memory space\n");
return;
}
csc->sc_bar_val = base | PCI_MAPREG_TYPE_MEM;
/* set up the PCI configuration registers */
ral_cardbus_setup(csc);
(*csc->sc_opns->attach)(sc, PCI_PRODUCT(ca->ca_id));
Cardbus_function_disable(ct);
}
void
athn_cardbus_attach(struct device *parent, struct device *self, void *aux)
{
struct athn_cardbus_softc *csc = (struct athn_cardbus_softc *)self;
struct athn_softc *sc = &csc->sc_sc;
struct cardbus_attach_args *ca = aux;
cardbus_devfunc_t ct = ca->ca_ct;
bus_addr_t base;
int error;
sc->sc_dmat = ca->ca_dmat;
csc->sc_ct = ct;
csc->sc_tag = ca->ca_tag;
csc->sc_intrline = ca->ca_intrline;
csc->sc_pc = ca->ca_pc;
/* Power management hooks. */
sc->sc_enable = athn_cardbus_enable;
sc->sc_disable = athn_cardbus_disable;
sc->sc_power = athn_cardbus_power;
sc->ops.read = athn_cardbus_read;
sc->ops.write = athn_cardbus_write;
sc->ops.write_barrier = athn_cardbus_write_barrier;
/* Map control/status registers. */
error = Cardbus_mapreg_map(ct, CARDBUS_BASE0_REG,
PCI_MAPREG_TYPE_MEM, 0, &csc->sc_st, &csc->sc_sh, &base,
&csc->sc_mapsize);
if (error != 0) {
printf(": can't map mem space\n");
return;
}
csc->sc_bar_val = base | PCI_MAPREG_TYPE_MEM;
/* Set up the PCI configuration registers. */
athn_cardbus_setup(csc);
printf(": irq %d\n", csc->sc_intrline);
athn_attach(sc);
Cardbus_function_disable(ct);
}
void
rtw_cardbus_attach(struct device *parent, struct device *self, void *aux)
{
struct rtw_cardbus_softc *csc = (void *)self;
struct rtw_softc *sc = &csc->sc_rtw;
struct rtw_regs *regs = &sc->sc_regs;
struct cardbus_attach_args *ca = aux;
cardbus_devfunc_t ct = ca->ca_ct;
bus_addr_t adr;
int rev;
sc->sc_dmat = ca->ca_dmat;
csc->sc_ct = ct;
csc->sc_tag = ca->ca_tag;
csc->sc_pc = ca->ca_pc;
/*
* Power management hooks.
*/
sc->sc_enable = rtw_cardbus_enable;
sc->sc_disable = rtw_cardbus_disable;
sc->sc_power = rtw_cardbus_power;
sc->sc_intr_ack = rtw_cardbus_intr_ack;
/* Get revision info. */
rev = PCI_REVISION(ca->ca_class);
RTW_DPRINTF(RTW_DEBUG_ATTACH,
("%s: pass %d.%d signature %08x\n", sc->sc_dev.dv_xname,
(rev >> 4) & 0xf, rev & 0xf,
pci_conf_read(ca->ca_pc, csc->sc_tag, 0x80)));
/*
* Map the device.
*/
csc->sc_csr = PCI_COMMAND_MASTER_ENABLE;
if (Cardbus_mapreg_map(ct, RTW_PCI_MMBA,
PCI_MAPREG_TYPE_MEM, 0, ®s->r_bt, ®s->r_bh, &adr,
&csc->sc_mapsize) == 0) {
RTW_DPRINTF(RTW_DEBUG_ATTACH,
("%s: %s mapped %lu bytes mem space\n",
sc->sc_dev.dv_xname, __func__, (long)csc->sc_mapsize));
csc->sc_cben = CARDBUS_MEM_ENABLE;
csc->sc_csr |= PCI_COMMAND_MEM_ENABLE;
csc->sc_bar_reg = RTW_PCI_MMBA;
csc->sc_bar_val = adr | PCI_MAPREG_TYPE_MEM;
} else if (Cardbus_mapreg_map(ct, RTW_PCI_IOBA,
PCI_MAPREG_TYPE_IO, 0, ®s->r_bt, ®s->r_bh, &adr,
&csc->sc_mapsize) == 0) {
RTW_DPRINTF(RTW_DEBUG_ATTACH,
("%s: %s mapped %lu bytes I/O space\n",
sc->sc_dev.dv_xname, __func__, (long)csc->sc_mapsize));
csc->sc_cben = CARDBUS_IO_ENABLE;
csc->sc_csr |= PCI_COMMAND_IO_ENABLE;
csc->sc_bar_reg = RTW_PCI_IOBA;
csc->sc_bar_val = adr | PCI_MAPREG_TYPE_IO;
} else {
printf("%s: unable to map device registers\n",
sc->sc_dev.dv_xname);
return;
}
/*
* Bring the chip out of powersave mode and initialize the
* configuration registers.
*/
rtw_cardbus_setup(csc);
/* Remember which interrupt line. */
csc->sc_intrline = ca->ca_intrline;
printf(": irq %d\n", csc->sc_intrline);
/*
* Finish off the attach.
*/
rtw_attach(sc);
rtw_cardbus_funcregen(regs, 1);
RTW_WRITE(regs, RTW_FEMR, RTW_FEMR_INTR);
RTW_WRITE(regs, RTW_FER, RTW_FER_INTR);
/*
* Power down the socket.
*/
Cardbus_function_disable(csc->sc_ct);
}
void
uhci_cardbus_attach(struct device *parent, struct device *self, void *aux)
{
struct uhci_cardbus_softc *sc = (struct uhci_cardbus_softc *)self;
struct cardbus_attach_args *ca = aux;
cardbus_devfunc_t ct = ca->ca_ct;
cardbus_chipset_tag_t cc = ct->ct_cc;
cardbus_function_tag_t cf = ct->ct_cf;
cardbusreg_t csr;
char devinfo[256];
usbd_status r;
const char *vendor;
const char *devname = sc->sc.sc_bus.bdev.dv_xname;
cardbus_devinfo(ca->ca_id, ca->ca_class, 0, devinfo, sizeof(devinfo));
printf(" %s", devinfo);
/* Map I/O registers */
if (Cardbus_mapreg_map(ct, PCI_CBIO, CARDBUS_MAPREG_TYPE_IO, 0,
&sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) {
printf("%s: can't map io space\n", devname);
return;
}
/* Disable interrupts, so we don't get any spurious ones. */
bus_space_write_2(sc->sc.iot, sc->sc.ioh, UHCI_INTR, 0);
sc->sc_cc = cc;
sc->sc_cf = cf;
sc->sc_ct = ct;
sc->sc.sc_bus.dmatag = ca->ca_dmat;
(ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_IO_ENABLE);
(ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE);
/* Enable the device. */
csr = cardbus_conf_read(cc, cf, ca->ca_tag,
CARDBUS_COMMAND_STATUS_REG);
cardbus_conf_write(cc, cf, ca->ca_tag, CARDBUS_COMMAND_STATUS_REG,
csr | CARDBUS_COMMAND_MASTER_ENABLE
| CARDBUS_COMMAND_IO_ENABLE);
sc->sc_ih = cardbus_intr_establish(cc, cf, ca->ca_intrline,
IPL_USB, uhci_intr, sc, devname);
if (sc->sc_ih == NULL) {
printf("%s: couldn't establish interrupt\n", devname);
return;
}
printf(": irq %d\n", ca->ca_intrline);
/* Set LEGSUP register to its default value. */
cardbus_conf_write(cc, cf, ca->ca_tag, PCI_LEGSUP,
PCI_LEGSUP_USBPIRQDEN);
switch(cardbus_conf_read(cc, cf, ca->ca_tag, PCI_USBREV) & PCI_USBREV_MASK) {
case PCI_USBREV_PRE_1_0:
sc->sc.sc_bus.usbrev = USBREV_PRE_1_0;
break;
case PCI_USBREV_1_0:
sc->sc.sc_bus.usbrev = USBREV_1_0;
break;
case PCI_USBREV_1_1:
sc->sc.sc_bus.usbrev = USBREV_1_1;
break;
default:
sc->sc.sc_bus.usbrev = USBREV_UNKNOWN;
break;
}
uhci_run(&sc->sc, 0); /* stop the controller */
/* disable interrupts */
bus_space_barrier(sc->sc.iot, sc->sc.ioh, 0, sc->sc.sc_size,
BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE);
bus_space_write_2(sc->sc.iot, sc->sc.ioh, UHCI_INTR, 0);
/* Figure out vendor for root hub descriptor. */
vendor = cardbus_findvendor(ca->ca_id);
sc->sc.sc_id_vendor = CARDBUS_VENDOR(ca->ca_id);
if (vendor)
strlcpy(sc->sc.sc_vendor, vendor, sizeof (sc->sc.sc_vendor));
else
snprintf(sc->sc.sc_vendor, sizeof(sc->sc.sc_vendor),
"vendor 0x%04x", CARDBUS_VENDOR(ca->ca_id));
r = uhci_init(&sc->sc);
if (r != USBD_NORMAL_COMPLETION) {
printf("%s: init failed, error=%d\n", devname, r);
bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size);
return;
}
/* Attach usb device. */
sc->sc.sc_child = config_found((void *)sc, &sc->sc.sc_bus,
usbctlprint);
}
void
dc_cardbus_attach(struct device *parent, struct device *self, void *aux)
{
struct dc_cardbus_softc *csc = (struct dc_cardbus_softc *)self;
struct dc_softc *sc = &csc->sc_dc;
struct cardbus_attach_args *ca = aux;
struct cardbus_devfunc *ct = ca->ca_ct;
cardbus_chipset_tag_t cc = ct->ct_cc;
pci_chipset_tag_t pc = ca->ca_pc;
cardbus_function_tag_t cf = ct->ct_cf;
pcireg_t reg;
bus_addr_t addr;
sc->sc_dmat = ca->ca_dmat;
csc->sc_ct = ct;
csc->sc_tag = ca->ca_tag;
csc->sc_pc = ca->ca_pc;
Cardbus_function_enable(ct);
if (Cardbus_mapreg_map(ct, PCI_CBIO,
PCI_MAPREG_TYPE_IO, 0, &sc->dc_btag, &sc->dc_bhandle, &addr,
&csc->sc_mapsize) == 0) {
csc->sc_actype = CARDBUS_IO_ENABLE;
} else if (Cardbus_mapreg_map(ct, PCI_CBMEM,
PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
&sc->dc_btag, &sc->dc_bhandle, &addr, &csc->sc_mapsize) == 0) {
csc->sc_actype = CARDBUS_MEM_ENABLE;
} else {
printf(": can't map device registers\n");
return;
}
csc->sc_intrline = ca->ca_intrline;
sc->dc_cachesize = pci_conf_read(csc->sc_pc, ca->ca_tag, DC_PCI_CFLT)
& 0xFF;
dc_cardbus_setup(csc);
/* Get the eeprom width */
if ((PCI_VENDOR(ca->ca_id) == PCI_VENDOR_XIRCOM &&
PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_XIRCOM_X3201_3_21143))
; /* XIRCOM has non-standard eeprom */
else
dc_eeprom_width(sc);
switch (PCI_VENDOR(ca->ca_id)) {
case PCI_VENDOR_DEC:
if (PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_DEC_21142) {
sc->dc_type = DC_TYPE_21143;
sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
sc->dc_flags |= DC_REDUCED_MII_POLL;
dc_read_srom(sc, sc->dc_romwidth);
dc_parse_21143_srom(sc);
}
break;
case PCI_VENDOR_XIRCOM:
if (PCI_PRODUCT(ca->ca_id) ==
PCI_PRODUCT_XIRCOM_X3201_3_21143) {
sc->dc_type = DC_TYPE_XIRCOM;
sc->dc_flags |= DC_TX_INTR_ALWAYS|DC_TX_COALESCE |
DC_TX_ALIGN;
sc->dc_pmode = DC_PMODE_MII;
}
break;
case PCI_VENDOR_ADMTEK:
case PCI_VENDOR_ACCTON:
case PCI_VENDOR_ABOCOM:
case PCI_VENDOR_DLINK:
case PCI_VENDOR_LINKSYS:
case PCI_VENDOR_HAWKING:
case PCI_VENDOR_MICROSOFT:
if (PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_ADMTEK_AN985 ||
PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_ACCTON_EN2242 ||
PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_ABOCOM_FE2500 ||
PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_ABOCOM_FE2500MX ||
PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_ABOCOM_PCM200 ||
PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_DLINK_DRP32TXD ||
PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_LINKSYS_PCMPC200 ||
PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_LINKSYS_PCM200 ||
PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_HAWKING_PN672TX ||
PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_MICROSOFT_MN120) {
sc->dc_type = DC_TYPE_AN983;
sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_ADMTEK_WAR |
DC_64BIT_HASH;
sc->dc_pmode = DC_PMODE_MII;
/* Don't read SROM for - auto-loaded on reset */
}
break;
default:
printf(": unknown device\n");
return;
}
/*
* set latency timer, do we really need this?
*/
reg = pci_conf_read(pc, ca->ca_tag, PCI_BHLC_REG);
if (PCI_LATTIMER(reg) < 0x20) {
reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
reg |= (0x20 << PCI_LATTIMER_SHIFT);
pci_conf_write(pc, ca->ca_tag, PCI_BHLC_REG, reg);
}
sc->sc_ih = cardbus_intr_establish(cc, cf, ca->ca_intrline, IPL_NET,
dc_intr, csc, sc->sc_dev.dv_xname);
if (sc->sc_ih == NULL) {
printf(": can't establish interrupt at %d\n",
ca->ca_intrline);
return;
}
printf(": irq %d", ca->ca_intrline);
dc_reset(sc);
sc->dc_revision = PCI_REVISION(ca->ca_class);
dc_attach(sc);
}
static void
njata_cardbus_attach(device_t parent, device_t self, void *aux)
{
struct cardbus_attach_args *ca = aux;
struct njata32_cardbus_softc *csc = device_private(self);
struct njata32_softc *sc = &csc->sc_njata32;
const struct njata32_cardbus_product *prod;
cardbus_devfunc_t ct = ca->ca_ct;
pcireg_t reg;
int csr;
uint8_t latency = 0x20;
sc->sc_wdcdev.sc_atac.atac_dev = self;
if ((prod = njata_cardbus_lookup(ca)) == NULL)
panic("njata_cardbus_attach");
aprint_normal(": Workbit NinjaATA-32 IDE controller\n");
csc->sc_ct = ct;
csc->sc_tag = ca->ca_tag;
/*
* Map the device.
*/
csr = PCI_COMMAND_MASTER_ENABLE;
/*
* Map registers.
* Try memory map first, and then try I/O.
*/
if ((prod->p_flags & NJATA32_FL_IOMAP_ONLY) == 0 &&
Cardbus_mapreg_map(csc->sc_ct, NJATA32_CARDBUS_BASEADDR_MEM,
PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
&NJATA32_REGT(sc), &csc->sc_regmaph, NULL, &csc->sc_regmap_size)
== 0) {
if (bus_space_subregion(NJATA32_REGT(sc), csc->sc_regmaph,
NJATA32_MEMOFFSET_REG, NJATA32_REGSIZE, &NJATA32_REGH(sc))
!= 0) {
/* failed -- undo map and try I/O */
Cardbus_mapreg_unmap(csc->sc_ct,
NJATA32_CARDBUS_BASEADDR_MEM, NJATA32_REGT(sc),
csc->sc_regmaph, csc->sc_regmap_size);
goto try_io;
}
#ifdef NJATA32_DEBUG
aprint_normal("%s: memory space mapped, size %u\n",
NJATA32NAME(sc), (unsigned)csc->sc_regmap_size);
#endif
csr |= PCI_COMMAND_MEM_ENABLE;
sc->sc_flags = NJATA32_MEM_MAPPED;
} else {
try_io:
if (Cardbus_mapreg_map(csc->sc_ct, NJATA32_CARDBUS_BASEADDR_IO,
PCI_MAPREG_TYPE_IO, 0, &NJATA32_REGT(sc),
&NJATA32_REGH(sc), NULL, &csc->sc_regmap_size) == 0) {
#ifdef NJATA32_DEBUG
aprint_normal("%s: io space mapped, size %u\n",
NJATA32NAME(sc), (unsigned)csc->sc_regmap_size);
#endif
csr |= PCI_COMMAND_IO_ENABLE;
sc->sc_flags = NJATA32_IO_MAPPED;
} else {
aprint_error("%s: unable to map device registers\n",
NJATA32NAME(sc));
return;
}
}
/* Enable the appropriate bits in the PCI CSR. */
reg = Cardbus_conf_read(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG);
reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
reg |= csr;
Cardbus_conf_write(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG, reg);
/*
* Make sure the latency timer is set to some reasonable
* value.
*/
reg = Cardbus_conf_read(ct, ca->ca_tag, PCI_BHLC_REG);
if (PCI_LATTIMER(reg) < latency) {
reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
reg |= (latency << PCI_LATTIMER_SHIFT);
Cardbus_conf_write(ct, ca->ca_tag, PCI_BHLC_REG, reg);
}
sc->sc_dmat = ca->ca_dmat;
/*
* Establish the interrupt.
*/
sc->sc_ih = Cardbus_intr_establish(ct, IPL_BIO, njata32_intr, sc);
if (sc->sc_ih == NULL) {
aprint_error("%s: unable to establish interrupt\n",
NJATA32NAME(sc));
return;
}
/* attach */
njata32_attach(sc);
}
void
ahc_cardbus_attach(device_t parent, device_t self, void *aux)
{
struct cardbus_attach_args *ca = aux;
struct ahc_cardbus_softc *csc = device_private(self);
struct ahc_softc *ahc = &csc->sc_ahc;
cardbus_devfunc_t ct = ca->ca_ct;
bus_space_tag_t bst;
bus_space_handle_t bsh;
pcireg_t reg;
u_int sxfrctl1 = 0;
u_char sblkctl;
ahc->sc_dev = self;
csc->sc_ct = ct;
csc->sc_tag = ca->ca_tag;
printf(": Adaptec ADP-1480 SCSI\n");
/*
* Map the device.
*/
csc->sc_csr = PCI_COMMAND_MASTER_ENABLE;
if (Cardbus_mapreg_map(csc->sc_ct, AHC_CARDBUS_MMBA,
PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
&bst, &bsh, NULL, &csc->sc_size) == 0) {
csc->sc_bar = AHC_CARDBUS_MMBA;
csc->sc_csr |= PCI_COMMAND_MEM_ENABLE;
} else if (Cardbus_mapreg_map(csc->sc_ct, AHC_CARDBUS_IOBA,
PCI_MAPREG_TYPE_IO, 0, &bst, &bsh, NULL, &csc->sc_size) == 0) {
csc->sc_bar = AHC_CARDBUS_IOBA;
csc->sc_csr |= PCI_COMMAND_IO_ENABLE;
} else {
csc->sc_bar = 0;
aprint_error("%s: unable to map device registers\n",
ahc_name(ahc));
return;
}
/* Enable the appropriate bits in the PCI CSR. */
reg = Cardbus_conf_read(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG);
reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
reg |= csc->sc_csr;
Cardbus_conf_write(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG, reg);
/*
* Make sure the latency timer is set to some reasonable
* value.
*/
reg = Cardbus_conf_read(ct, ca->ca_tag, PCI_BHLC_REG);
if (PCI_LATTIMER(reg) < 0x20) {
reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
reg |= (0x20 << PCI_LATTIMER_SHIFT);
Cardbus_conf_write(ct, ca->ca_tag, PCI_BHLC_REG, reg);
}
ahc_set_name(ahc, device_xname(ahc->sc_dev));
ahc->parent_dmat = ca->ca_dmat;
ahc->tag = bst;
ahc->bsh = bsh;
/*
* ADP-1480 is always an AIC-7860.
*/
ahc->chip = AHC_AIC7860 | AHC_PCI;
ahc->features = AHC_AIC7860_FE|AHC_REMOVABLE;
ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
if (PCI_REVISION(ca->ca_class) >= 1)
ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
if (ahc_softc_init(ahc) != 0)
return;
/*
* On all CardBus adapters, we allow SCB paging.
*/
ahc->flags = AHC_PAGESCBS;
ahc->channel = 'A';
ahc_intr_enable(ahc, FALSE);
ahc_reset(ahc);
/*
* Establish the interrupt.
*/
ahc->ih = Cardbus_intr_establish(ct, IPL_BIO, ahc_intr, ahc);
if (ahc->ih == NULL) {
aprint_error("%s: unable to establish interrupt\n",
ahc_name(ahc));
return;
}
ahc->seep_config = malloc(sizeof(*ahc->seep_config),
M_DEVBUF, M_NOWAIT);
if (ahc->seep_config == NULL)
return;
ahc_check_extport(ahc, &sxfrctl1);
/*
* Take the LED out of diagnostic mode.
*/
sblkctl = ahc_inb(ahc, SBLKCTL);
ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON)));
/*
* I don't know where this is set in the SEEPROM or by the
* BIOS, so we default to 100%.
*/
ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100);
if (ahc->flags & AHC_USEDEFAULTS) {
int our_id;
/*
* Assume only one connector and always turn
* on termination.
*/
our_id = AHC_CARDBUS_DEFAULT_SCSI_ID;
sxfrctl1 = STPWEN;
ahc_outb(ahc, SCSICONF, our_id | ENSPCHK | RESET_SCSI);
ahc->our_id = our_id;
}
printf("%s: aic7860", ahc_name(ahc));
/*
* Record our termination setting for the
* generic initialization routine.
*/
if ((sxfrctl1 & STPWEN) != 0)
ahc->flags |= AHC_TERM_ENB_A;
if (ahc_init(ahc)) {
ahc_free(ahc);
return;
}
ahc_attach(ahc);
}
static void
njs_cardbus_attach(struct device *parent, struct device *self, void *aux)
{
struct cardbus_attach_args *ca = aux;
struct njsc32_cardbus_softc *csc = (void *) self;
struct njsc32_softc *sc = &csc->sc_njsc32;
const struct njsc32_cardbus_product *prod;
cardbus_devfunc_t ct = ca->ca_ct;
cardbus_chipset_tag_t cc = ct->ct_cc;
cardbus_function_tag_t cf = ct->ct_cf;
pcireg_t reg;
int csr;
u_int8_t latency = 0x20;
if ((prod = njs_cardbus_lookup(ca)) == NULL)
panic("njs_cardbus_attach");
printf(": Workbit NinjaSCSI-32 SCSI adapter\n");
sc->sc_model = prod->p_model;
sc->sc_clk = prod->p_clk;
csc->sc_ct = ct;
csc->sc_tag = ca->ca_tag;
csc->sc_intrline = ca->ca_intrline;
/*
* Map the device.
*/
csr = PCI_COMMAND_MASTER_ENABLE;
/*
* Map registers.
* Try memory map first, and then try I/O.
*/
if (Cardbus_mapreg_map(csc->sc_ct, NJSC32_CARDBUS_BASEADDR_MEM,
PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
&sc->sc_regt, &csc->sc_regmaph, NULL, &csc->sc_regmap_size) == 0) {
if (bus_space_subregion(sc->sc_regt, csc->sc_regmaph,
NJSC32_MEMOFFSET_REG, NJSC32_REGSIZE, &sc->sc_regh) != 0) {
/* failed -- undo map and try I/O */
Cardbus_mapreg_unmap(csc->sc_ct,
NJSC32_CARDBUS_BASEADDR_MEM,
sc->sc_regt, csc->sc_regmaph, csc->sc_regmap_size);
goto try_io;
}
#ifdef NJSC32_DEBUG
printf("%s: memory space mapped\n", sc->sc_dev.dv_xname);
#endif
csr |= PCI_COMMAND_MEM_ENABLE;
sc->sc_flags = NJSC32_MEM_MAPPED;
(*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_MEM_ENABLE);
} else {
try_io:
if (Cardbus_mapreg_map(csc->sc_ct, NJSC32_CARDBUS_BASEADDR_IO,
PCI_MAPREG_TYPE_IO, 0, &sc->sc_regt, &sc->sc_regh,
NULL, &csc->sc_regmap_size) == 0) {
#ifdef NJSC32_DEBUG
printf("%s: io space mapped\n", sc->sc_dev.dv_xname);
#endif
csr |= PCI_COMMAND_IO_ENABLE;
sc->sc_flags = NJSC32_IO_MAPPED;
(*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_IO_ENABLE);
} else {
printf("%s: unable to map device registers\n",
sc->sc_dev.dv_xname);
return;
}
}
/* Make sure the right access type is on the CardBus bridge. */
(*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE);
/* Enable the appropriate bits in the PCI CSR. */
reg = cardbus_conf_read(cc, cf, ca->ca_tag, PCI_COMMAND_STATUS_REG);
reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
reg |= csr;
cardbus_conf_write(cc, cf, ca->ca_tag, PCI_COMMAND_STATUS_REG, reg);
/*
* Make sure the latency timer is set to some reasonable
* value.
*/
reg = cardbus_conf_read(cc, cf, ca->ca_tag, CARDBUS_BHLC_REG);
if (CARDBUS_LATTIMER(reg) < latency) {
reg &= ~(CARDBUS_LATTIMER_MASK << CARDBUS_LATTIMER_SHIFT);
reg |= (latency << CARDBUS_LATTIMER_SHIFT);
cardbus_conf_write(cc, cf, ca->ca_tag, CARDBUS_BHLC_REG, reg);
}
sc->sc_dmat = ca->ca_dmat;
/*
* Establish the interrupt.
*/
sc->sc_ih = cardbus_intr_establish(cc, cf, ca->ca_intrline, IPL_BIO,
njsc32_intr, sc);
if (sc->sc_ih == NULL) {
printf("%s: unable to establish interrupt at %d\n",
sc->sc_dev.dv_xname, ca->ca_intrline);
return;
}
printf("%s: interrupting at %d\n",
sc->sc_dev.dv_xname, ca->ca_intrline);
/* CardBus device cannot supply termination power. */
sc->sc_flags |= NJSC32_CANNOT_SUPPLY_TERMPWR;
/* attach */
njsc32_attach(sc);
}
static void
uhci_cardbus_attach(device_t parent, device_t self,
void *aux)
{
struct uhci_cardbus_softc *sc = device_private(self);
struct cardbus_attach_args *ca = (struct cardbus_attach_args *)aux;
cardbus_devfunc_t ct = ca->ca_ct;
cardbus_chipset_tag_t cc = ct->ct_cc;
cardbus_function_tag_t cf = ct->ct_cf;
pcitag_t tag = ca->ca_tag;
pcireg_t csr;
const char *vendor;
const char *devname = device_xname(self);
char devinfo[256];
usbd_status r;
sc->sc.sc_dev = self;
sc->sc.sc_bus.hci_private = sc;
pci_devinfo(ca->ca_id, ca->ca_class, 0, devinfo, sizeof(devinfo));
printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(ca->ca_class));
/* Map I/O registers */
if (Cardbus_mapreg_map(ct, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0,
&sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) {
printf("%s: can't map i/o space\n", devname);
return;
}
sc->sc_cc = cc;
sc->sc_cf = cf;
sc->sc_ct = ct;
sc->sc_tag = tag;
sc->sc.sc_bus.dmatag = ca->ca_dmat;
/* Enable the device. */
csr = Cardbus_conf_read(ct, tag, PCI_COMMAND_STATUS_REG);
Cardbus_conf_write(ct, tag, PCI_COMMAND_STATUS_REG,
csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE);
/* Disable interrupts, so we don't get any spurious ones. */
bus_space_write_2(sc->sc.iot, sc->sc.ioh, UHCI_INTR, 0);
/* Map and establish the interrupt. */
sc->sc_ih = Cardbus_intr_establish(ct, IPL_USB, uhci_intr, sc);
if (sc->sc_ih == NULL) {
printf("%s: couldn't establish interrupt\n", devname);
return;
}
/* Set LEGSUP register to its default value. */
Cardbus_conf_write(ct, tag, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN);
switch(Cardbus_conf_read(ct, tag, PCI_USBREV) & PCI_USBREV_MASK) {
case PCI_USBREV_PRE_1_0:
sc->sc.sc_bus.usbrev = USBREV_PRE_1_0;
break;
case PCI_USBREV_1_0:
sc->sc.sc_bus.usbrev = USBREV_1_0;
break;
case PCI_USBREV_1_1:
sc->sc.sc_bus.usbrev = USBREV_1_1;
break;
default:
sc->sc.sc_bus.usbrev = USBREV_UNKNOWN;
break;
}
/* Figure out vendor for root hub descriptor. */
vendor = pci_findvendor(ca->ca_id);
sc->sc.sc_id_vendor = PCI_VENDOR(ca->ca_id);
if (vendor)
strlcpy(sc->sc.sc_vendor, vendor, sizeof(sc->sc.sc_vendor));
else
snprintf(sc->sc.sc_vendor, sizeof(sc->sc.sc_vendor),
"vendor 0x%04x", PCI_VENDOR(ca->ca_id));
r = uhci_init(&sc->sc);
if (r != USBD_NORMAL_COMPLETION) {
printf("%s: init failed, error=%d\n", devname, r);
/* Avoid spurious interrupts. */
Cardbus_intr_disestablish(ct, sc->sc_ih);
sc->sc_ih = NULL;
return;
}
#if NEHCI_CARDBUS > 0
usb_cardbus_add(&sc->sc_cardbus, ca, self);
#endif
/* Attach usb device. */
sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint);
}
void
puc_cardbus_attach(struct device *parent, struct device *self, void *aux)
{
struct puc_cardbus_softc *csc = (struct puc_cardbus_softc *)self;
struct puc_softc *sc = &csc->sc_psc;
struct cardbus_attach_args *ca = aux;
struct cardbus_devfunc *ct = ca->ca_ct;
cardbus_chipset_tag_t cc = ct->ct_cc;
pci_chipset_tag_t pc = ca->ca_pc;
cardbus_function_tag_t cf = ct->ct_cf;
struct puc_attach_args paa;
pcireg_t reg;
int i;
Cardbus_function_enable(ct);
csc->ct = ct;
reg = pci_conf_read(pc, ca->ca_tag, PCI_SUBSYS_ID_REG);
sc->sc_desc = puc_find_description(PCI_VENDOR(ca->ca_id),
PCI_PRODUCT(ca->ca_id), PCI_VENDOR(reg), PCI_PRODUCT(reg));
puc_print_ports(sc->sc_desc);
/* the fifth one is some memory we dunno */
for (i = 0; i < PUC_NBARS; i++) {
pcireg_t type;
int bar;
sc->sc_bar_mappings[i].mapped = 0;
bar = PCI_MAPREG_START + 4 * i;
if (!pci_mapreg_probe(pc, ca->ca_tag, bar, &type))
continue;
if (!(sc->sc_bar_mappings[i].mapped = !Cardbus_mapreg_map(ct,
bar, type, 0,
&sc->sc_bar_mappings[i].t, &sc->sc_bar_mappings[i].h,
&sc->sc_bar_mappings[i].a, &sc->sc_bar_mappings[i].s)))
printf("%s: couldn't map BAR at offset 0x%lx\n",
sc->sc_dev.dv_xname, (long)bar);
sc->sc_bar_mappings[i].type = type;
}
csc->intrline = ca->ca_intrline;
if (pci_get_capability(pc, ca->ca_tag, PCI_CAP_PWRMGMT, ®,
0)) {
reg = pci_conf_read(pc, ca->ca_tag, reg + 4) & 3;
if (reg) {
printf("%s: awakening from state D%d\n",
sc->sc_dev.dv_xname, reg);
pci_conf_write(pc, ca->ca_tag, reg + 4, 0);
}
}
(*cf->cardbus_ctrl)(cc, CARDBUS_MEM_ENABLE);
(*cf->cardbus_ctrl)(cc, CARDBUS_IO_ENABLE);
(*cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE);
paa.puc = sc;
paa.hwtype = COM_UART_OX16C950; /* XXX */
paa.intr_string = &puc_cardbus_intr_string;
paa.intr_establish = &puc_cardbus_intr_establish;
puc_common_attach(sc, &paa);
}
void
ehci_cardbus_attach(struct device *parent, struct device *self, void *aux)
{
struct ehci_cardbus_softc *sc = (struct ehci_cardbus_softc *)self;
struct cardbus_attach_args *ca = aux;
cardbus_devfunc_t ct = ca->ca_ct;
cardbus_chipset_tag_t cc = ct->ct_cc;
pci_chipset_tag_t pc = ca->ca_pc;
cardbus_function_tag_t cf = ct->ct_cf;
pcireg_t csr;
usbd_status r;
const char *vendor;
const char *devname = sc->sc.sc_bus.bdev.dv_xname;
/* Map I/O registers */
if (Cardbus_mapreg_map(ct, CARDBUS_CBMEM, PCI_MAPREG_TYPE_MEM, 0,
&sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) {
printf(": can't map mem space\n");
return;
}
sc->sc_cc = cc;
sc->sc_cf = cf;
sc->sc_ct = ct;
sc->sc.sc_bus.dmatag = ca->ca_dmat;
(ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_MEM_ENABLE);
(ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE);
/* Enable the device. */
csr = pci_conf_read(pc, ca->ca_tag,
PCI_COMMAND_STATUS_REG);
pci_conf_write(pc, ca->ca_tag, PCI_COMMAND_STATUS_REG,
csr | PCI_COMMAND_MASTER_ENABLE
| PCI_COMMAND_MEM_ENABLE);
/* Disable interrupts, so we don't get any spurious ones. */
sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH);
EOWRITE2(&sc->sc, EHCI_USBINTR, 0);
sc->sc_ih = cardbus_intr_establish(cc, cf, ca->ca_intrline,
IPL_USB, ehci_intr, sc, devname);
if (sc->sc_ih == NULL) {
printf(": unable to establish interrupt\n");
return;
}
printf(": irq %d\n", ca->ca_intrline);
/* Figure out vendor for root hub descriptor. */
vendor = cardbus_findvendor(ca->ca_id);
sc->sc.sc_id_vendor = PCI_VENDOR(ca->ca_id);
if (vendor)
strlcpy(sc->sc.sc_vendor, vendor, sizeof(sc->sc.sc_vendor));
else
snprintf(sc->sc.sc_vendor, sizeof(sc->sc.sc_vendor),
"vendor 0x%04x", PCI_VENDOR(ca->ca_id));
r = ehci_init(&sc->sc);
if (r != USBD_NORMAL_COMPLETION) {
printf("%s: init failed, error=%d\n", devname, r);
/* Avoid spurious interrupts. */
cardbus_intr_disestablish(sc->sc_cc, sc->sc_cf, sc->sc_ih);
sc->sc_ih = NULL;
return;
}
/* Attach usb device. */
config_found(self, &sc->sc.sc_bus, usbctlprint);
}
void
ex_cardbus_attach(device_t parent, device_t self, void *aux)
{
struct ex_cardbus_softc *csc = device_private(self);
struct ex_softc *sc = &csc->sc_softc;
struct cardbus_attach_args *ca = aux;
cardbus_devfunc_t ct = ca->ca_ct;
#if rbus
#else
cardbus_chipset_tag_t cc = ct->ct_cc;
#endif
const struct ex_cardbus_product *ecp;
bus_addr_t adr, adr1;
sc->sc_dev = self;
sc->ex_bustype = EX_BUS_CARDBUS;
sc->sc_dmat = ca->ca_dmat;
csc->sc_ct = ca->ca_ct;
csc->sc_intrline = ca->ca_intrline;
csc->sc_tag = ca->ca_tag;
ecp = ex_cardbus_lookup(ca);
if (ecp == NULL) {
printf("\n");
panic("ex_cardbus_attach: impossible");
}
aprint_normal(": 3Com %s\n", ecp->ecp_name);
sc->ex_conf = ecp->ecp_flags;
csc->sc_cardtype = ecp->ecp_cardtype;
csc->sc_csr = ecp->ecp_csr;
if (Cardbus_mapreg_map(ct, CARDBUS_BASE0_REG, CARDBUS_MAPREG_TYPE_IO, 0,
&sc->sc_iot, &sc->sc_ioh, &adr, &csc->sc_mapsize) == 0) {
#if rbus
#else
(*ct->ct_cf->cardbus_io_open)(cc, 0, adr, adr + csc->sc_mapsize);
#endif
csc->sc_bar_reg = CARDBUS_BASE0_REG;
csc->sc_bar_val = adr | CARDBUS_MAPREG_TYPE_IO;
if (csc->sc_cardtype == EX_CB_CYCLONE) {
/* Map CardBus function status window. */
if (Cardbus_mapreg_map(ct,
CARDBUS_3C575BTX_FUNCSTAT_PCIREG,
CARDBUS_MAPREG_TYPE_MEM, 0,
&csc->sc_funct, &csc->sc_funch,
&adr1, &csc->sc_funcsize) == 0) {
csc->sc_bar_reg1 =
CARDBUS_3C575BTX_FUNCSTAT_PCIREG;
csc->sc_bar_val1 =
adr1 | CARDBUS_MAPREG_TYPE_MEM;
} else {
aprint_error_dev(self, "unable to map function "
"status window\n");
return;
}
/* Setup interrupt acknowledge hook */
sc->intr_ack = ex_cardbus_intr_ack;
}
}
else {
aprint_naive(": can't map i/o space\n");
return;
}
/* Power management hooks. */
sc->enable = ex_cardbus_enable;
sc->disable = ex_cardbus_disable;
/*
* Handle power management nonsense and
* initialize the configuration registers.
*/
ex_cardbus_setup(csc);
ex_config(sc);
if (csc->sc_cardtype == EX_CB_CYCLONE)
bus_space_write_4(csc->sc_funct, csc->sc_funch,
EX_CB_INTR, EX_CB_INTR_ACK);
Cardbus_function_disable(csc->sc_ct);
}
void
atw_cardbus_attach(struct device *parent, struct device *self, void *aux)
{
struct atw_cardbus_softc *csc = (void *)self;
struct atw_softc *sc = &csc->sc_atw;
struct cardbus_attach_args *ca = aux;
cardbus_devfunc_t ct = ca->ca_ct;
bus_addr_t adr;
sc->sc_dmat = ca->ca_dmat;
csc->sc_ct = ct;
csc->sc_tag = ca->ca_tag;
/*
* Power management hooks.
*/
sc->sc_enable = atw_cardbus_enable;
sc->sc_disable = atw_cardbus_disable;
sc->sc_power = atw_cardbus_power;
/* Get revision info. */
sc->sc_rev = PCI_REVISION(ca->ca_class);
#if 0
printf(": signature %08x\n%s",
cardbus_conf_read(ct->ct_cc, ct->ct_cf, csc->sc_tag, 0x80),
sc->sc_dev.dv_xname);
#endif
/*
* Map the device.
*/
csc->sc_csr = CARDBUS_COMMAND_MASTER_ENABLE;
if (Cardbus_mapreg_map(ct, ATW_PCI_MMBA,
CARDBUS_MAPREG_TYPE_MEM, 0, &sc->sc_st, &sc->sc_sh, &adr,
&csc->sc_mapsize) == 0) {
#if 0
printf(": atw_cardbus_attach mapped %d bytes mem space\n%s",
csc->sc_mapsize, sc->sc_dev.dv_xname);
#endif
csc->sc_cben = CARDBUS_MEM_ENABLE;
csc->sc_csr |= CARDBUS_COMMAND_MEM_ENABLE;
csc->sc_bar_reg = ATW_PCI_MMBA;
csc->sc_bar_val = adr | CARDBUS_MAPREG_TYPE_MEM;
} else if (Cardbus_mapreg_map(ct, ATW_PCI_IOBA,
CARDBUS_MAPREG_TYPE_IO, 0, &sc->sc_st, &sc->sc_sh, &adr,
&csc->sc_mapsize) == 0) {
#if 0
printf(": atw_cardbus_attach mapped %d bytes I/O space\n%s",
csc->sc_mapsize, sc->sc_dev.dv_xname);
#endif
csc->sc_cben = CARDBUS_IO_ENABLE;
csc->sc_csr |= CARDBUS_COMMAND_IO_ENABLE;
csc->sc_bar_reg = ATW_PCI_IOBA;
csc->sc_bar_val = adr | CARDBUS_MAPREG_TYPE_IO;
} else {
printf(": unable to map device registers\n");
return;
}
/*
* Bring the chip out of powersave mode and initialize the
* configuration registers.
*/
atw_cardbus_setup(csc);
/* Remember which interrupt line. */
csc->sc_intrline = ca->ca_intrline;
printf(": revision %d.%d: irq %d\n",
(sc->sc_rev >> 4) & 0xf, sc->sc_rev & 0xf, csc->sc_intrline);
#if 0
/*
* The CardBus cards will make it to store-and-forward mode as
* soon as you put them under any kind of load, so just start
* out there.
*/
sc->sc_txthresh = 3; /* TBD name constant */
#endif
/*
* Finish off the attach.
*/
atw_attach(sc);
ATW_WRITE(sc, ATW_FER, ATW_FER_INTR);
/*
* Power down the socket.
*/
Cardbus_function_disable(csc->sc_ct);
}
void
adv_cardbus_attach(struct device *parent, struct device *self,
void *aux)
{
struct cardbus_attach_args *ca = aux;
struct adv_cardbus_softc *csc = device_private(self);
struct asc_softc *sc = &csc->sc_adv;
cardbus_devfunc_t ct = ca->ca_ct;
cardbus_chipset_tag_t cc = ct->ct_cc;
cardbus_function_tag_t cf = ct->ct_cf;
bus_space_tag_t iot;
bus_space_handle_t ioh;
pcireg_t reg;
u_int8_t latency = 0x20;
sc->sc_flags = 0;
if (PCI_VENDOR(ca->ca_id) == PCI_VENDOR_ADVSYS) {
switch (PCI_PRODUCT(ca->ca_id)) {
case PCI_PRODUCT_ADVSYS_1200A:
printf(": AdvanSys ASC1200A SCSI adapter\n");
latency = 0;
break;
case PCI_PRODUCT_ADVSYS_1200B:
printf(": AdvanSys ASC1200B SCSI adapter\n");
latency = 0;
break;
case PCI_PRODUCT_ADVSYS_ULTRA:
switch (PCI_REVISION(ca->ca_class)) {
case ASC_PCI_REVISION_3050:
printf(": AdvanSys ABP-9xxUA SCSI adapter\n");
break;
case ASC_PCI_REVISION_3150:
printf(": AdvanSys ABP-9xxU SCSI adapter\n");
break;
}
break;
default:
printf(": unknown model!\n");
return;
}
}
csc->sc_ct = ct;
csc->sc_tag = ca->ca_tag;
csc->sc_intrline = ca->ca_intrline;
csc->sc_cbenable = 0;
/*
* Map the device.
*/
csc->sc_csr = PCI_COMMAND_MASTER_ENABLE;
#ifdef ADV_CARDBUS_ALLOW_MEMIO
if (Cardbus_mapreg_map(csc->sc_ct, ADV_CARDBUS_MMBA,
PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
&iot, &ioh, NULL, &csc->sc_size) == 0) {
#ifdef ADV_CARDBUS_DEBUG
printf("%s: memio enabled\n", DEVNAME(sc));
#endif
csc->sc_cbenable = CARDBUS_MEM_ENABLE;
csc->sc_csr |= PCI_COMMAND_MEM_ENABLE;
} else
#endif
if (Cardbus_mapreg_map(csc->sc_ct, ADV_CARDBUS_IOBA,
PCI_MAPREG_TYPE_IO, 0, &iot, &ioh, NULL, &csc->sc_size) == 0) {
#ifdef ADV_CARDBUS_DEBUG
printf("%s: io enabled\n", DEVNAME(sc));
#endif
csc->sc_cbenable = CARDBUS_IO_ENABLE;
csc->sc_csr |= PCI_COMMAND_IO_ENABLE;
} else {
aprint_error_dev(&sc->sc_dev, "unable to map device registers\n");
return;
}
/* Make sure the right access type is on the CardBus bridge. */
(*ct->ct_cf->cardbus_ctrl)(cc, csc->sc_cbenable);
(*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE);
/* Enable the appropriate bits in the PCI CSR. */
reg = cardbus_conf_read(cc, cf, ca->ca_tag, PCI_COMMAND_STATUS_REG);
reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
reg |= csc->sc_csr;
cardbus_conf_write(cc, cf, ca->ca_tag, PCI_COMMAND_STATUS_REG, reg);
/*
* Make sure the latency timer is set to some reasonable
* value.
*/
reg = cardbus_conf_read(cc, cf, ca->ca_tag, PCI_BHLC_REG);
if (PCI_LATTIMER(reg) < latency) {
reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
reg |= (latency << PCI_LATTIMER_SHIFT);
cardbus_conf_write(cc, cf, ca->ca_tag, PCI_BHLC_REG, reg);
}
ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT);
ASC_SET_CHIP_STATUS(iot, ioh, 0);
sc->sc_iot = iot;
sc->sc_ioh = ioh;
sc->sc_dmat = ca->ca_dmat;
sc->pci_device_id = ca->ca_id;
sc->bus_type = ASC_IS_PCI;
sc->chip_version = ASC_GET_CHIP_VER_NO(iot, ioh);
/*
* Initialize the board
*/
if (adv_init(sc)) {
printf("adv_init failed\n");
return;
}
/*
* Establish the interrupt.
*/
sc->sc_ih = cardbus_intr_establish(cc, cf, ca->ca_intrline, IPL_BIO,
adv_intr, sc);
if (sc->sc_ih == NULL) {
aprint_error_dev(&sc->sc_dev,
"unable to establish interrupt\n");
return;
}
/*
* Attach.
*/
adv_attach(sc);
}
void
re_cardbus_attach(device_t parent, device_t self, void *aux)
{
struct re_cardbus_softc *csc = device_private(self);
struct rtk_softc *sc = &csc->sc_rtk;
struct cardbus_attach_args *ca = aux;
cardbus_devfunc_t ct = ca->ca_ct;
const struct rtk_type *t;
bus_addr_t adr;
sc->sc_dev = self;
sc->sc_dmat = ca->ca_dmat;
csc->sc_ct = ct;
csc->sc_tag = ca->ca_tag;
csc->sc_intrline = ca->ca_intrline;
t = re_cardbus_lookup(ca);
if (t == NULL) {
aprint_error("\n");
panic("%s: impossible", __func__);
}
aprint_normal(": %s\n", t->rtk_name);
/*
* Power management hooks.
*/
sc->sc_enable = re_cardbus_enable;
sc->sc_disable = re_cardbus_disable;
/*
* Map control/status registers.
*/
csc->sc_csr = CARDBUS_COMMAND_MASTER_ENABLE;
#ifdef RTK_USEIOSPACE
if (Cardbus_mapreg_map(ct, RTK_PCI_LOIO, CARDBUS_MAPREG_TYPE_IO, 0,
&sc->rtk_btag, &sc->rtk_bhandle, &adr, &csc->sc_mapsize) == 0) {
#if rbus
#else
(*ct->ct_cf->cardbus_io_open)(cc, 0, adr, adr+csc->sc_mapsize);
#endif
csc->sc_cben = CARDBUS_IO_ENABLE;
csc->sc_csr |= CARDBUS_COMMAND_IO_ENABLE;
csc->sc_bar_reg = RTK_PCI_LOIO;
csc->sc_bar_val = adr | CARDBUS_MAPREG_TYPE_IO;
}
#else
if (Cardbus_mapreg_map(ct, RTK_PCI_LOMEM, CARDBUS_MAPREG_TYPE_MEM, 0,
&sc->rtk_btag, &sc->rtk_bhandle, &adr, &csc->sc_mapsize) == 0) {
#if rbus
#else
(*ct->ct_cf->cardbus_mem_open)(cc, 0, adr, adr+csc->sc_mapsize);
#endif
csc->sc_cben = CARDBUS_MEM_ENABLE;
csc->sc_csr |= CARDBUS_COMMAND_MEM_ENABLE;
csc->sc_bar_reg = RTK_PCI_LOMEM;
csc->sc_bar_val = adr | CARDBUS_MAPREG_TYPE_MEM;
}
#endif
else {
aprint_error_dev(self, "unable to map deviceregisters\n");
return;
}
/*
* Handle power management nonsense and initialize the
* configuration registers.
*/
re_cardbus_setup(csc);
sc->sc_dmat = ca->ca_dmat;
re_attach(sc);
if (!pmf_device_register(self, NULL, NULL))
aprint_error_dev(self, "couldn't establish power handler\n");
else
pmf_class_network_register(self, &sc->ethercom.ec_if);
/*
* Power down the socket.
*/
Cardbus_function_disable(csc->sc_ct);
}
void
ohci_cardbus_attach(device_t parent, device_t self, void *aux)
{
struct ohci_cardbus_softc *sc = device_private(self);
struct cardbus_attach_args *ca = aux;
cardbus_devfunc_t ct = ca->ca_ct;
cardbus_chipset_tag_t cc = ct->ct_cc;
cardbus_function_tag_t cf = ct->ct_cf;
pcireg_t csr;
char devinfo[256];
usbd_status r;
const char *vendor;
const char *devname = device_xname(self);
sc->sc.sc_dev = self;
sc->sc.sc_bus.hci_private = sc;
pci_devinfo(ca->ca_id, ca->ca_class, 0, devinfo, sizeof(devinfo));
printf(": %s (rev. 0x%02x)\n", devinfo,
PCI_REVISION(ca->ca_class));
/* Map I/O registers */
if (Cardbus_mapreg_map(ct, PCI_CBMEM, PCI_MAPREG_TYPE_MEM, 0,
&sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) {
printf("%s: can't map mem space\n", devname);
return;
}
sc->sc_cc = cc;
sc->sc_cf = cf;
sc->sc_ct = ct;
sc->sc.sc_bus.dmatag = ca->ca_dmat;
/* Enable the device. */
csr = Cardbus_conf_read(ct, ca->ca_tag,
PCI_COMMAND_STATUS_REG);
Cardbus_conf_write(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG,
csr | PCI_COMMAND_MASTER_ENABLE
| PCI_COMMAND_MEM_ENABLE);
/* Disable interrupts, so we don't can any spurious ones. */
bus_space_write_4(sc->sc.iot, sc->sc.ioh, OHCI_INTERRUPT_DISABLE,
OHCI_ALL_INTRS);
sc->sc_ih = Cardbus_intr_establish(ct, IPL_USB, ohci_intr, sc);
if (sc->sc_ih == NULL) {
printf("%s: couldn't establish interrupt\n", devname);
return;
}
/* Figure out vendor for root hub descriptor. */
vendor = pci_findvendor(ca->ca_id);
sc->sc.sc_id_vendor = PCI_VENDOR(ca->ca_id);
if (vendor)
strlcpy(sc->sc.sc_vendor, vendor, sizeof(sc->sc.sc_vendor));
else
snprintf(sc->sc.sc_vendor, sizeof(sc->sc.sc_vendor),
"vendor 0x%04x", PCI_VENDOR(ca->ca_id));
r = ohci_init(&sc->sc);
if (r != USBD_NORMAL_COMPLETION) {
printf("%s: init failed, error=%d\n", devname, r);
/* Avoid spurious interrupts. */
Cardbus_intr_disestablish(ct, sc->sc_ih);
sc->sc_ih = 0;
return;
}
#if NEHCI_CARDBUS > 0
usb_cardbus_add(&sc->sc_cardbus, ca, self);
#endif
if (!pmf_device_register1(self, ohci_suspend, ohci_resume,
ohci_shutdown))
aprint_error_dev(self, "couldn't establish power handler\n");
/* Attach usb device. */
sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint);
}
