/* Initialize the SDIO card */
int SDIO_Card_Init(LPC_SDMMC_T *pSDMMC, uint32_t freq)
{
int ret;
uint32_t val;
/* Set Clock to 400KHz */
Chip_SDIF_SetClock(pSDMMC, Chip_Clock_GetBaseClocktHz(CLK_BASE_SDIO), freq);
Chip_SDIF_SetCardType(pSDMMC, 0);
sdioif->wait_evt(pSDMMC, SDIO_WAIT_DELAY, (void *) 100); /* Wait for card to wake up */
if (sdioif->flag & SDIO_POWER_INIT) {
/* Write to the Reset Bit */
ret = SDIO_Write_Direct(pSDMMC, SDIO_AREA_CIA, 0x06, 0x08);
if (ret) return ret;
}
/* Set Voltage level to 3v3 */
ret = SDIO_Card_SetVoltage(pSDMMC);
if (ret) return ret;
/* Set the RCA */
ret = SDIO_CARD_SetRCA(pSDMMC);
if (ret) return ret;
/* ==== check card capability ==== */
val = 0x02;
ret = SDIO_WriteRead_Direct(pSDMMC, SDIO_AREA_CIA, 0x13, &val);
if (ret) return ret;
/* FIXME: Verify */
/* FIFO threshold settings for DMA, DMA burst of 4, FIFO watermark at 16 */
pSDMMC->FIFOTH = MCI_FIFOTH_DMA_MTS_1 | MCI_FIFOTH_RX_WM(0) | MCI_FIFOTH_TX_WM(1);
/* Enable internal DMA, burst size of 4, fixed burst */
pSDMMC->BMOD = MCI_BMOD_DE | MCI_BMOD_PBL1 | MCI_BMOD_DSL(0);
/* High Speed Support? */
if ((val & 0x03) == 3) {
return SDIO_Card_SetMode(pSDMMC, SDIO_CLK_HISPEED, 1);
}
ret = SDIO_Read_Direct(pSDMMC, SDIO_AREA_CIA, 0x08, &val);
if (ret) return ret;
/* Full Speed Support? */
if (val & SDIO_CCCR_LSC) {
return SDIO_Card_SetMode(pSDMMC, SDIO_CLK_FULLSPEED, 1);
}
/* Low Speed Card */
return SDIO_Card_SetMode(pSDMMC, SDIO_CLK_LOWSPEED, val & SDIO_CCCR_4BLS);
}
/* Set the Clock speed and mode [1/4 bit] of the card */
static int SDIO_Card_SetMode(LPC_SDMMC_T *pSDMMC, uint32_t clk, int mode_4bit)
{
int ret;
uint32_t val;
Chip_SDIF_SetClock(pSDMMC, Chip_Clock_GetBaseClocktHz(CLK_BASE_SDIO), clk);
if (!mode_4bit)
return 0;
val = 0x02;
ret = SDIO_WriteRead_Direct(pSDMMC, SDIO_AREA_CIA, 0x07, &val);
if (ret) return ret;
if (val & 0x02) {
Chip_SDIF_SetCardType(pSDMMC, MCI_CTYPE_4BIT);
}
return 0;
}
/**
* @brief Main entry point
* @return Nothing
*/
int main(void)
{
bool bool_status;
uint32_t mainpll_freq, clkin_frq, dive_value, baseclk_frq, perclk_frq;
CHIP_CGU_CLKIN_T clk_in, base_input;
bool autoblocken;
bool powerdn;
int i;
volatile int k = 1;
SystemCoreClockUpdate();
Board_Init();
/* Print the Demo Information */
DEBUGOUT(menu);
/* Main PLL should be locked, Check if Main PLL is locked */
DEBUGOUT("=========================================== \r\n");
DEBUGOUT("PLL functions \r\n");
DEBUGOUT("Main PLL : ");
bool_status = Chip_Clock_MainPLLLocked();
if (bool_status == true) {
DEBUGOUT("Locked\r\n");
}
else {
DEBUGOUT("Not Locked\r\n");
return 1;
}
/* Read Main PLL frequency in Hz */
mainpll_freq = Chip_Clock_GetMainPLLHz();
if (mainpll_freq == 0) {
DEBUGOUT("Error in reading Main PLL frequency \r\n");
return 2;
}
DEBUGOUT("Main PLL Frequency in Hz : %d \r\n", mainpll_freq);
DEBUGOUT("=========================================== \r\n");
DEBUGOUT("=========================================== \r\n");
DEBUGOUT("Clock Divider functions \r\n");
/*
* Divider E divider is used for SPIFI, source is set to
* Main PLL in SysInit code.
* Read Divider E source & verify it
*/
clk_in = Chip_Clock_GetDividerSource(CLK_IDIV_E);
if (clk_in != CLKIN_MAINPLL) {
DEBUGOUT("Divider E source wrong %d \r\n", clk_in);
return 3;
}
DEBUGOUT("Divider E source set to Main PLL \r\n");
/*
* Divider E divider is used for SPIFI, divider value should be
* between 3 and 5 set in SysInit code.
* Read Divider E divider value & verify it
*/
dive_value = Chip_Clock_GetDividerDivisor(CLK_IDIV_E);
if ( (dive_value < 3) && (dive_value > 5)) {
DEBUGOUT("Divider E divider wrong %d \r\n", dive_value);
return 4;
}
DEBUGOUT("Divider E divider value: %d \r\n", dive_value);
DEBUGOUT("=========================================== \r\n");
/*
* Read the frequencies of the input clock sources,
* print it on UART prompt
*/
DEBUGOUT("=========================================== \r\n");
DEBUGOUT("Input clock frequencies \r\n");
DEBUGOUT("=========================================== \r\n");
for ( i = 0; i < (sizeof(clkin_info) / sizeof(CLKIN_NAME_T)); i++) {
clkin_frq = Chip_Clock_GetClockInputHz(clkin_info[i].clk_in);
DEBUGOUT(" %s Frequency : %d Hz \r\n", clkin_info[i].clkin_name, clkin_frq);
}
DEBUGOUT("=========================================== \r\n");
/*
* Read the base clock settings & print on UART
*/
DEBUGOUT("=========================================== \r\n");
DEBUGOUT("Base Clock Setting Information \r\n");
DEBUGOUT("=========================================== \r\n");
for ( i = 0; i < (sizeof(baseclk_info) / sizeof(BASECLK_INFO_T)); i++) {
/* Read Base clock info, only if base clock is enabled */
bool_status = Chip_Clock_IsBaseClockEnabled(baseclk_info[i].clock);
if ( bool_status == true) {
Chip_Clock_GetBaseClockOpts(baseclk_info[i].clock, &base_input,
&autoblocken, &powerdn);
/* Read Frequency of the base clock */
baseclk_frq = Chip_Clock_GetBaseClocktHz(baseclk_info[i].clock);
/* Print details on UART */
DEBUGOUT("%s Input Clk: %d Base Clk Frq : %d Hz Auto block: %d Power down: %d \r\n",
baseclk_info[i].clock_name, base_input, baseclk_frq, autoblocken, powerdn);
}
}
DEBUGOUT("=========================================== \r\n");
/*
* Read the peripheral clock rate & print on UART
*/
DEBUGOUT("=========================================== \r\n");
DEBUGOUT("Peripheral Clock Rates \r\n");
DEBUGOUT("=========================================== \r\n");
for ( i = 0; i < (sizeof(ccu_clk_info) / sizeof(CCUCLK_INFO_T)); i++) {
/* Read Frequency of the peripheral clock */
perclk_frq = Chip_Clock_GetRate(ccu_clk_info[i].per_clk);
/* Print the per clock only if it is enabled */
if (perclk_frq) {
/* Print details on UART */
DEBUGOUT("%s Per Frq : %d Hz \r\n", ccu_clk_info[i].clock_name,
perclk_frq);
}
}
DEBUGOUT("=========================================== \r\n");
while (k) ;
return 0;
}
