/* Initialise the SCT Pins */
void SCT_PinsConfigure(void)
{
#ifdef BOARD_HITEX_EVA_18504350
/* Enable signals on MC connector X19 */
Chip_SCU_PinMuxSet(0xD, 9, (SCU_MODE_MODE_INACT | SCU_MODE_FUNC4)); /* PD_9: GPIO 6.23, MCSEL */
Chip_GPIO_WriteDirBit(LPC_GPIO_PORT, MCSEL_PORT, MCSEL_BIT, true);
Chip_GPIO_WritePortBit(LPC_GPIO_PORT, MCSEL_PORT, MCSEL_BIT, false);
/* Pin configuration for SCT */
/* PD_7: SCTIN_5 used for the CROSS_REQUEST input (button) */
Chip_SCU_PinMuxSet(0xD, 7, (SCU_MODE_MODE_REPEATER | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC1));
/* PD_10: SCTIN_1, used for SCT clock input */
/* Connect JP13 pin 1 with connector X19 pin2 */
Chip_SCU_PinMuxSet(0xD, 10, (SCU_MODE_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC1));
Chip_SCU_PinMuxSet(0xE, 6, (SCU_MODE_MODE_PULLUP | SCU_MODE_FUNC1)); /* PE_6: SCTOUT_2 connected to RGB green */
Chip_SCU_PinMuxSet(0xE, 5, (SCU_MODE_MODE_PULLUP | SCU_MODE_FUNC1)); /* PE_5: SCTOUT_3 connected to RGB red */
Chip_SCU_PinMuxSet(0xE, 8, (SCU_MODE_MODE_PULLUP | SCU_MODE_FUNC1)); /* P4_4: SCTOUT_4 connected to RGB blue */
Chip_SCU_PinMuxSet(0xE, 7, (SCU_MODE_MODE_PULLUP | SCU_MODE_FUNC1)); /* P4_3: SCTOUT_5 */
Chip_SCU_PinMuxSet(0xD, 3, (SCU_MODE_MODE_PULLUP | SCU_MODE_FUNC1)); /* PD_3: SCTOUT_6 */
/* Global configuration of the SCT */
/* use external clock, rising edge, on CTIN1 */
/* For Hitex4350, external clock is IRC clock /16 = 12 MHz / 16 = 750 KHz */
/* For Hitex1850, external clock is IRC clock /16 = 12 MHz / 16 = 750 KHz */
Chip_SCT_Config(LPC_SCT, (SCT_CONFIG_16BIT_COUNTER | (0x2 << 1) | (0x2 << 3)));
#elif defined(BOARD_KEIL_MCB_18574357)
/* PD_10: SCTIN_2, used for SCT clock input */
/* Connect PF_8 pin to CLK3 */
Chip_SCU_PinMuxSet(0xF, 8, (SCU_MODE_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2));
Chip_SCU_PinMuxSet(0xD, 11, (SCU_MODE_MODE_PULLUP | SCU_MODE_FUNC6)); /* PD_11: SCTOUT_14 connected to LED1 */
Chip_SCU_PinMuxSet(0xD, 12, (SCU_MODE_MODE_PULLUP | SCU_MODE_FUNC6)); /* PD_12: SCTOUT_10 connected to LED2 */
Chip_SCU_PinMuxSet(0xD, 13, (SCU_MODE_MODE_PULLUP | SCU_MODE_FUNC6)); /* PD_13: SCTOUT_13 connected to LED3 */
Chip_SCU_PinMuxSet(0xD, 14, (SCU_MODE_MODE_PULLUP | SCU_MODE_FUNC6)); /* PD_14: SCTOUT_11 connected to LED4 */
Chip_SCU_PinMuxSet(0xD, 15, (SCU_MODE_MODE_PULLUP | SCU_MODE_FUNC6)); /* PD_15: SCTOUT_8 connected to LED5 */
/* Global configuration of the SCT */
/* use external clock, rising edge, on CTIN2 */
/* For Keil4357, external clock is IRC clock /16 = 12 MHz / 16 = 750 KHz */
/* For Keil1857, external clock is IRC clock /16 = 12 MHz / 16 = 750 KHz */
Chip_SCT_Config(LPC_SCT, (SCT_CONFIG_16BIT_COUNTER | (0x2 << 1) | (0x4 << 3)));
#else
#error Board not supported!
#endif
}
/**
* @brief main routine for blinky example
* @return Function should not exit.
*/
int main(void)
{
SystemCoreClockUpdate();
Board_Init();
Board_LED_Set(0, false);
#if 0
/* Enable SysTick Timer */
SysTick_Config(SystemCoreClock / TICKRATE_HZ);
/* Bail out after timeout */
while (sysTick <= TIMEOUT_TICKS) {
__WFI();
}
#else
/* Enable SysTick Timer */
SysTick_Config(SystemCoreClock / TICKRATE_HZ);
/* Custom Initialization */
Chip_SCT_Init(LPC_SCT);
/* Configure the SCT as a 32bit counter using the bus clock */
Chip_SCT_Config(LPC_SCT, (0xf << 9) | SCT_CONFIG_32BIT_COUNTER | SCT_CONFIG_CLKMODE_BUSCLK);
/* The match/capture REGMODE defaults to match mode */
/* Set the match count for match register 0 */
Chip_SCT_SetMatchCount(LPC_SCT, SCT_MATCH_0, SystemCoreClock / TICKRATE_HZ);
/* Set the match reload value */
Chip_SCT_SetMatchReload(LPC_SCT, SCT_MATCH_0, SystemCoreClock / TICKRATE_HZ);
LPC_SCT->EVENT[0].CTRL = 0x5000;
LPC_SCT->EVENT[0].STATE = 0x1;
LPC_SCT->LIMIT = 0x1;
/* Enable an Interrupt on the Match Event */
Chip_SCT_EnableEventInt(LPC_SCT, SCT_EVT_0);
/* Enable the IRQ for the SCT */
NVIC_EnableIRQ(SCT_IRQn);
LPC_SCT->CTRL_U &= ~(1 << 2); /* unhalt the SCT by clearing bit 2 of the unified CTRL register */
while (1) {
__WFI();
}
#endif
return 0;
}
/* Set the PWM frequency */
void Chip_SCTPWM_SetRate(LPC_SCT_T *pSCT, uint32_t freq)
{
uint32_t rate;
rate = Chip_Clock_GetSystemClockRate() / freq;;
/* Stop the SCT before configuration */
Chip_SCTPWM_Stop(pSCT);
/* Set MATCH0 for max limit */
pSCT->REGMODE_U = 0;
Chip_SCT_SetMatchCount(pSCT, SCT_MATCH_0, 0);
Chip_SCT_SetMatchReload(pSCT, SCT_MATCH_0, rate);
pSCT->EV[0].CTRL = 1 << 12;
pSCT->EV[0].STATE = 1;
/* Set SCT Counter to count 32-bits and reset to 0 after reaching MATCH0 */
Chip_SCT_Config(pSCT, SCT_CONFIG_32BIT_COUNTER | SCT_CONFIG_AUTOLIMIT_L);
}
int execute_SCT_match_test( LPC_SCT_T *pSCT, CounterWidth counter_width, CHIP_SCT_MATCH_REG_T match_register,
uint32_t match_count, SCTClock sct_clock, SCTInputEdge sct_input_edge) {
uint32_t cfg = 0, evt_ctrl = 0;
int i;
/* Custom Initialization */
Chip_SCT_Init(pSCT);
switch (counter_width) {
case kCounterWidth16Bits:
cfg |= SCT_CONFIG_16BIT_COUNTER;
break;
case kCounterWidth32Bits:
cfg |= SCT_CONFIG_32BIT_COUNTER;
break;
}
switch (sct_clock) {
case kSystemClock:
cfg |= SCT_CONFIG_CLKMODE_SYSCLK;
break;
case kPrescaledSystemClock:
cfg |= SCT_CONFIG_CLKMODE_PRESCALED_SYSCLK;
break;
case kSCTInput:
cfg |= SCT_CONFIG_CLKMODE_SCT_INPUT;
break;
case kPrescaledSCTInput:
cfg |= SCT_CONFIG_CLKMODE_PRESCALED_SCT_INPUT;
break;
}
if ((sct_clock == kSCTInput) || (sct_clock == kPrescaledSCTInput)) {
switch (sct_input_edge) {
case kRisingInput0:
cfg |= SCT_CONFIG_CKSEL_RISING_IN_0;
break;
case kFallingInput0:
cfg |= SCT_CONFIG_CKSEL_FALLING_IN_0;
break;
case kRisingInput1:
cfg |= SCT_CONFIG_CKSEL_RISING_IN_1;
break;
case kFallingInput1:
cfg |= SCT_CONFIG_CKSEL_FALLING_IN_1;
break;
case kRisingInput2:
cfg |= SCT_CONFIG_CKSEL_RISING_IN_2;
break;
case kFallingInput2:
cfg |= SCT_CONFIG_CKSEL_FALLING_IN_2;
break;
case kRisingInput3:
cfg |= SCT_CONFIG_CKSEL_RISING_IN_3;
break;
case kFallingInput3:
cfg |= SCT_CONFIG_CKSEL_FALLING_IN_3;
break;
case kRisingInput4:
cfg |= SCT_CONFIG_CKSEL_RISING_IN_4;
break;
case kFallingInput4:
cfg |= SCT_CONFIG_CKSEL_FALLING_IN_4;
break;
case kRisingInput5:
cfg |= SCT_CONFIG_CKSEL_RISING_IN_5;
break;
case kFallingInput5:
cfg |= SCT_CONFIG_CKSEL_FALLING_IN_5;
break;
case kRisingInput6:
cfg |= SCT_CONFIG_CKSEL_RISING_IN_6;
break;
case kFallingInput6:
cfg |= SCT_CONFIG_CKSEL_FALLING_IN_6;
break;
case kRisingInput7:
cfg |= SCT_CONFIG_CKSEL_RISING_IN_7;
break;
case kFallingInput7:
cfg |= SCT_CONFIG_CKSEL_FALLING_IN_7;
break;
}
}
Chip_SCT_Config(pSCT, cfg);
/* The match/capture REGMODE defaults to match mode */
/* Set the match count */
Chip_SCT_SetMatchCount(pSCT, match_register, match_count);
/* Set the match reload value */
Chip_SCT_SetMatchReload(pSCT, match_register, match_count);
/* Setup so that a match in the match_register when in State 0 causes Event 0.
* Setup so Event 0 causes a Limit condition
*/
evt_ctrl |= SCT_EV_CTRL_MATCHSEL(match_register) | SCT_EV_CTRL_HEVENT_L |
SCT_EV_CTRL_COMBMODE_MATCH;
Chip_SCT_EventControl(pSCT, 0, evt_ctrl);
Chip_SCT_EventStateMask(pSCT, 0, (1UL << 0));
Chip_SCT_Limit(pSCT, (1UL << 0));
/* Setup to toggle all outputs on match */
for (i = 0; i < CONFIG_SCT_nOU; i++) {
LPC_SCT->OUT[i].SET = (1UL << 0);
LPC_SCT->OUT[i].CLR = (1UL << 0);
Chip_SCT_SetConflictResolution(LPC_SCT, i, 0x3);
}
/* Enable an Interrupt on the Match Event */
Chip_SCT_EnableEventInt(pSCT, SCT_EVT_0);
/* Enable the IRQ for the SCT */
NVIC_EnableIRQ(SCT_IRQn);
/* Start the counter */
if (counter_width == kCounterWidth32Bits) {
Chip_SCT_ClearControl(pSCT, SCT_CTRL_HALT_L);
}
else {
// TODO deal with 16 bit counter mode
}
return 0;
}
