static void spi_interrupt_transceive(spi_device_t* device) { Chip_SSP_DATA_SETUP_T* setup = &device->xf_setup; Chip_SSP_Int_Disable(device->ssp_device); /* Disable all interrupt */ Chip_SSP_Int_RWFrames8Bits(device->ssp_device, setup); if ((setup->rx_cnt != setup->length) || (setup->tx_cnt != setup->length)) { Chip_SSP_Int_Enable(device->ssp_device); /* enable all interrupts */ } else { portBASE_TYPE woken = pdFALSE; xSemaphoreGiveFromISR(device->sem_ready, &woken); portYIELD_FROM_ISR(woken); } }
int32_t cmd_draw_circle( LPC_SSP_T *spi, struct cmd_circle *circle ) { uint8_t cmd = CANVAS_CMD_CIRCLE; /* disable sending DUMMY pattern to FIFO */ Chip_SSP_Int_Disable(spi); /* send command */ Chip_SSP_WriteFrames_Blocking(spi, &cmd, sizeof(cmd)); /* send circle struct */ Chip_SSP_WriteFrames_Blocking(spi, (uint8_t*)circle, sizeof(*circle)); /* enable sending DUMMY pattern to FIFO */ Chip_SSP_Int_Enable(spi); return 0; }
int32_t cmd_clear_screen( LPC_SSP_T *spi, struct cmd_clearscreen *screen ) { uint8_t cmd = CANVAS_CMD_CLEAR; /* disable sending DUMMY pattern to FIFO */ Chip_SSP_Int_Disable(spi); /* send command */ Chip_SSP_WriteFrames_Blocking(spi, &cmd, sizeof(cmd)); /* send data */ Chip_SSP_WriteFrames_Blocking(spi, (uint8_t*)screen, sizeof(*screen)); /* enable sending DUMMY pattern to FIFO */ Chip_SSP_Int_Enable(spi); return 0; }
/** * @brief SSP interrupt handler sub-routine * @return Nothing */ void SSPIRQHANDLER(void) { Chip_SSP_Int_Disable(LPC_SSP); /* Disable all interrupt */ if (SSP_DATA_BYTES(ssp_format.bits) == 1) { Chip_SSP_Int_RWFrames8Bits(LPC_SSP, &xf_setup); } else { Chip_SSP_Int_RWFrames16Bits(LPC_SSP, &xf_setup); } if ((xf_setup.rx_cnt != xf_setup.length) || (xf_setup.tx_cnt != xf_setup.length)) { Chip_SSP_Int_Enable(LPC_SSP); /* enable all interrupts */ } else { isXferCompleted = 1; } }
int32_t cmd_get_dimension( LPC_SSP_T *spi, struct ack_dimension *dimension ) { uint8_t cmd = CANVAS_CMD_GETDIMENSION; uint8_t ack; /* disable sending DUMMY pattern to FIFO */ Chip_SSP_Int_Disable(spi); /* send command */ Chip_SSP_WriteFrames_Blocking(spi, &cmd, sizeof(cmd)); /* wait for acknowledge */ do { Chip_SSP_ReadFrames_Blocking(spi, (uint8_t*)&ack, sizeof(ack)); } while (ack != CANVAS_ACK_DIMENSION); /* now we can read data */ Chip_SSP_ReadFrames_Blocking(spi, (uint8_t*)dimension, sizeof(*dimension)); /* enable sending DUMMY pattern to FIFO */ Chip_SSP_Int_Enable(spi); return 0; }
static void ssp_irq_handler( LPC_SSP_T * ssp_id ) { BaseType_t xHigherPriorityTaskWoken = pdFALSE; Chip_SSP_DATA_SETUP_T * xf_setup; uint8_t ssp_cfg_index; if ((ssp_id == LPC_SSP0) && (active_SSP0 != 0xFF)) { ssp_cfg_index = active_SSP0; } else if (ssp_id == LPC_SSP1) { /* The only component in SPI1 is the Flash memory */ ssp_cfg_index = FLASH_SPI; } xf_setup = &ssp_cfg[ssp_cfg_index].xf_setup; /* Disable SSP interrupts */ Chip_SSP_Int_Disable(ssp_id); if (ssp_cfg[ssp_cfg_index].frame_size <= 8) { Chip_SSP_Int_RWFrames8Bits(ssp_id, xf_setup); } else { Chip_SSP_Int_RWFrames16Bits(ssp_id, xf_setup); } if ((xf_setup->rx_cnt != xf_setup->length) || (xf_setup->tx_cnt != xf_setup->length)) { /* Enable ssp interrupts, we're going to read/write more data */ Chip_SSP_Int_Enable(ssp_id); } else { /* Transfer is completed, notify the caller task */ vTaskNotifyGiveFromISR(ssp_cfg[ssp_cfg_index].caller_task, &xHigherPriorityTaskWoken); /* Deassert SSEL pin */ ssp_ssel_control(ssp_cfg_index, DEASSERT); } portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); }