/* Shutdown ADC */
void Chip_ADC_DeInit(LPC_ADC_T *pADC)
{
pADC->INTEN = 0;
pADC->CTRL = 0;
/* Stop ADC clock and then power down ADC */
if (pADC == LPC_ADC0) {
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_ADC0);
Chip_SYSCTL_PowerDown(SYSCTL_POWERDOWN_ADC0_PD);
}
else {
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_ADC1);
Chip_SYSCTL_PowerDown(SYSCTL_POWERDOWN_ADC1_PD);
}
}
/* Shutdown ADC */
void Chip_ADC_DeInit(LPC_ADC_T *pADC)
{
pADC->INTEN = 0x00000100;
pADC->CR = 0;
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_ADC);
Chip_SYSCTL_PowerDown(SYSCTL_POWERDOWN_ADC_PD);
}
/* Set up and initialize hardware prior to call to main */
void Chip_SetupIrcClocking(void)
{
/* IRC should be powered up */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_IRC_PD);
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_IRCOUT_PD);
/* Set system PLL input to main oscillator */
Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_IRC);
/* Power down PLL to change the PLL divider ratio */
Chip_SYSCTL_PowerDown(SYSCTL_POWERDOWN_SYSPLL_PD);
/* Setup PLL for main oscillator rate (FCLKIN = 12MHz) * 6 = 72MHz
MSEL = 5 (this is pre-decremented), PSEL = 1 (for P = 2)
FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 6 = 72MHz
FCCO = FCLKOUT * 2 * P = 72MHz * 2 * 2 = 288MHz (within FCCO range) */
Chip_Clock_SetupSystemPLL(5, 1);
/* Powerup system PLL */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSPLL_PD);
/* Wait for PLL to lock */
while (!Chip_Clock_IsSystemPLLLocked()) {}
/* Set system clock divider to 1 */
Chip_Clock_SetSysClockDiv(1);
/* Setup FLASH access to 3 clocks */
Chip_FMC_SetFLASHAccess(FLASHTIM_72MHZ_CPU);
/* Set main clock source to the system PLL. This will drive 48MHz
for the main clock and 48MHz for the system clock */
Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_PLLOUT);
}
/* Shutdown ADC */
void Chip_ADC_DeInit(LPC_ADC_T *pADC)
{
pADC->INTEN = 0;
pADC->CTRL = 0;
/* Stop ADC clock and then power down ADC */
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_ADC);
Chip_SYSCTL_PowerDown(SYSCTL_SLPWAKE_ADC_PD);
}
/**
* @brief main routine for CLKOUT example
* @return Function should not exit.
*/
int main(void)
{
CHIP_SYSCTL_CLKOUTSRC_T clkoutClks;
SystemCoreClockUpdate();
Board_Init();
Board_LED_Set(0, false);
/* Enable and setup SysTick Timer at a 100Hz rate */
SysTick_Config(Chip_Clock_GetSysTickClockRate() / 100);
/* Enable the power to the WDT */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_WDTOSC_PD);
/* Setup SCT PLL */
Chip_SYSCTL_PowerDown(SYSCTL_POWERDOWN_SCTPLL_PD);
Chip_Clock_SetSCTPLLSource(SYSCTL_PLLCLKSRC_MAINOSC);
Chip_Clock_SetupSCTPLL(5, 2);
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SCTPLL_PD);
/* Wait for PLL to lock */
while (!Chip_Clock_IsSCTPLLLocked()) {}
/* Enable RTC Oscillator */
Chip_Clock_EnableRTCOsc();
/* Enable SWM clocking prior to switch matrix operations */
Chip_SWM_Init();
Chip_GPIO_Init(LPC_GPIO);
/* Setup pin as CLKOUT */
Chip_SWM_MovablePortPinAssign(SWM_CLK_OUT_O, CLKOUT_PORT, CLKOUT_PIN);
/* Configure as a digital pin with no pullups/pulldowns */
Chip_IOCON_PinMuxSet(LPC_IOCON, CLKOUT_PORT, CLKOUT_PIN,
(IOCON_MODE_INACT | IOCON_DIGMODE_EN));
/* Cycle through all clock sources for the CLKOUT pin */
while (1) {
for (clkoutClks = SYSCTL_CLKOUTSRC_IRC;
clkoutClks <= SYSCTL_CLKOUTSRC_RTC32K; clkoutClks++) {
/* Setup CLKOUT pin for specific clock with a divider of 1 */
Chip_Clock_SetCLKOUTSource(clkoutClks, 1);
/* Wait 5 seconds */
ticks100 = 0;
while (ticks100 < 500) {
__WFI();
}
}
}
/* Disable CLKOUT pin by setting divider to 0 */
Chip_Clock_SetCLKOUTSource(SYSCTL_CLKOUTSRC_MAINSYSCLK, 0);
return 0;
}
/* De-initializes the ACMP */
void Chip_ACMP_Deinit(LPC_CMP_T *pACMP)
{
IP_ACMP_Deinit(pACMP);
/* Disable the clock to the register interface */
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_ACOMP);
/* Enable the power to the analog comparator */
Chip_SYSCTL_PowerDown(SYSCTL_SLPWAKE_ACMP_PD);
}
/* De-initializes the ACMP */
void Chip_ACMP_Deinit(LPC_CMP_T *pACMP)
{
IP_ACMP_Deinit(pACMP);
/* Disable ACMP clock */
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_ACOMP);
/* Enable the power to the analog comparator */
Chip_SYSCTL_PowerDown(SYSCTL_POWERDOWN_ACOMP_PD);
}
/* Setup system clocking */
STATIC void SystemSetupClocking(void)
{
volatile int i;
/* Powerup main oscillator */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSOSC_PD);
/* Wait 200us for OSC to be stablized, no status
indication, dummy wait. */
for (i = 0; i < 0x100; i++) {}
/* Set system PLL input to main oscillator */
Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_MAINOSC);
/* Power down PLL to change the PLL divider ratio */
Chip_SYSCTL_PowerDown(SYSCTL_POWERDOWN_SYSPLL_PD);
/* Setup PLL for main oscillator rate (FCLKIN = 12MHz) * 4 = 48MHz
MSEL = 3 (this is pre-decremented), PSEL = 1 (for P = 2)
FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 4 = 48MHz
FCCO = FCLKOUT * 2 * P = 48MHz * 2 * 2 = 192MHz (within FCCO range) */
Chip_Clock_SetupSystemPLL(3, 1);
/* Powerup system PLL */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSPLL_PD);
/* Wait for PLL to lock */
while (!Chip_Clock_IsSystemPLLLocked()) {}
/* Set system clock divider to 1 */
Chip_Clock_SetSysClockDiv(1);
/* Setup FLASH access to 3 clocks */
Chip_FMC_SetFLASHAccess(FLASHTIM_50MHZ_CPU);
/* Set main clock source to the system PLL. This will drive 48MHz
for the main clock and 48MHz for the system clock */
Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_PLLOUT);
/* Set USB PLL input to main oscillator */
Chip_Clock_SetUSBPLLSource(SYSCTL_PLLCLKSRC_MAINOSC);
/* Setup USB PLL (FCLKIN = 12MHz) * 4 = 48MHz
MSEL = 3 (this is pre-decremented), PSEL = 1 (for P = 2)
FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 4 = 48MHz
FCCO = FCLKOUT * 2 * P = 48MHz * 2 * 2 = 192MHz (within FCCO range) */
Chip_Clock_SetupUSBPLL(3, 1);
/* Powerup USB PLL */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_USBPLL_PD);
/* Wait for PLL to lock */
while (!Chip_Clock_IsUSBPLLLocked()) {}
}
/* Clock and PLL initialization based on the external oscillator */
void Chip_SetupXtalClocking(void)
{
volatile int i;
#if defined(USE_ROM_API)
uint32_t cmd[4], resp[2];
#endif
/* Powerup main oscillator */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSOSC_PD);
/* Wait for at least 580uS for osc to stabilize */
for (i = 0; i < 2500; i++) {}
/* Set system PLL input to main oscillator */
Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_MAINOSC);
/* Setup FLASH access to 2 clocks */
Chip_FMC_SetFLASHAccess(FLASHTIM_2CLK_CPU);
#if defined(USE_ROM_API)
/* Use ROM API for setting up PLL */
cmd[0] = Chip_Clock_GetMainOscRate() / 1000; /* in KHz */
cmd[1] = 48000000 / 1000; /* 48MHz system clock rate */
cmd[2] = CPU_FREQ_EQU;
cmd[3] = 48000000 / 10000; /* Timeout */
LPC_PWRD_API->set_pll(cmd, resp);
/* Dead loop on fail */
while (resp[0] != PLL_CMD_SUCCESS) {}
#else
/* Power down PLL to change the PLL divider ratio */
Chip_SYSCTL_PowerDown(SYSCTL_POWERDOWN_SYSPLL_PD);
/* Setup PLL for main oscillator rate (FCLKIN = 12MHz) * 4 = 48MHz
MSEL = 3 (this is pre-decremented), PSEL = 1 (for P = 2)
FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 4 = 48MHz
FCCO = FCLKOUT * 2 * P = 48MHz * 2 * 2 = 192MHz (within FCCO range) */
Chip_Clock_SetupSystemPLL(3, 1);
/* Powerup system PLL */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSPLL_PD);
/* Wait for PLL to lock */
while (!Chip_Clock_IsSystemPLLLocked()) {}
/* Set system clock divider to 1 */
Chip_Clock_SetSysClockDiv(1);
/* Set main clock source to the system PLL. This will drive 48MHz
for the main clock and 48MHz for the system clock */
Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_PLLOUT);
#endif
}
/* Setup system clocking */
STATIC void Board_SetupXtalClocking(void)
{
#if USE_CLKIN_IN
uint32_t i;
#endif
/* A library"pmu_library.lib) has been created to facilitate the power management
operation. The user needs to enter the desired frequency the application wants to
run, the set_voltage() will set the internal voltage regulators automatically. */
set_voltage( SYSCTL_IRC_FREQ * PLL_MULTIPLIER );
/* Select the PLL input in the IRC */
#if USE_CLKIN_IN
/* IOCON clock left on, this is needed is CLKIN is used. */
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_IOCON);
Chip_IOCON_PinMuxSet(LPC_IOCON, 0, 22, IOCON_MODE_PULLUP | IOCON_FUNC1 | IOCON_DIGITAL_EN | IOCON_INPFILT_OFF);
/* Delay to wait until CLKIN stablized */
for ( i = 0; i < 500; i++ ) {}
Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_CLKIN);
/* Wait State setting TBD */
/* Setup FLASH access to 2 clocks (up to 20MHz) */
Chip_FMC_SetFLASHAccess(FLASHTIM_72MHZ_CPU);
#else
Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_IRC);
/* Wait State setting TBD */
/* Setup FLASH access to 5 clocks (up to 72MHz) */
Chip_FMC_SetFLASHAccess(FLASHTIM_72MHZ_CPU);
#endif
/* Power down PLL to change the PLL divider ratio */
Chip_SYSCTL_PowerDown(PDRUNCFG_PD_SYS_PLL0);
/* First parameter is the multiplier, the second parameter is the input frequency in MHz */
#if USE_CLKIN_IN
Chip_Clock_SetupSystemPLL(PLL_MULTIPLIER, ExtRateIn);
#else
Chip_Clock_SetupSystemPLL(PLL_MULTIPLIER, SYSCTL_IRC_FREQ);
#endif
/* Turn on the PLL by clearing the power down bit */
Chip_SYSCTL_PowerUp(PDRUNCFG_PD_SYS_PLL0);
/* Wait for PLL to lock */
while (!Chip_Clock_IsSystemPLLLocked()) {}
/* Set system clock divider to 1 */
Chip_Clock_SetSysClockDiv(1);
/* Set main clock source to the system PLL. This will drive 24MHz
for the main clock and 24MHz for the system clock */
Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_PLLOUT);
}
/* Set up and initialize hardware prior to call to main */
void Chip_SystemInit(void)
{
#ifdef SUPPORT_NXP_MAIN_OSC
volatile uint32_t i;
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSOSC_PD);
Chip_Clock_SetPLLBypass(0, 0);
for (i = 0; i < 200; i++) __NOP();
Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_MAINOSC);
#else
/* IRC should be powered up */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_IRC_PD);
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_IRCOUT_PD);
/* Set system PLL input to main oscillator */
Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_IRC);
#endif
/* Power down PLL to change the PLL divider ratio */
Chip_SYSCTL_PowerDown(SYSCTL_POWERDOWN_SYSPLL_PD);
#ifdef SUPPORT_NXP_MAIN_OSC
Chip_Clock_SetupSystemPLL(3, 2);
#else
/* Setup PLL for main oscillator rate (FCLKIN = 12MHz) * 4 = 48MHz
MSEL = 3 (this is pre-decremented), PSEL = 1 (for P = 2)
FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 4 = 48MHz
FCCO = FCLKOUT * 2 * P = 48MHz * 2 * 2 = 192MHz (within FCCO range) */
Chip_Clock_SetupSystemPLL(3, 1);
#endif
/* Powerup system PLL */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSPLL_PD);
/* Wait for PLL to lock */
while (!Chip_Clock_IsSystemPLLLocked()) {}
/* Set system clock divider to 1 */
Chip_Clock_SetSysClockDiv(1);
/* Setup FLASH access to 3 clocks */
Chip_FMC_SetFLASHAccess(FLASHTIM_50MHZ_CPU);
/* Set main clock source to the system PLL. This will drive 48MHz
for the main clock and 48MHz for the system clock */
Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_PLLOUT);
/* Enable IOCON clock */
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_IOCON);
}
/* Clock and PLL initialization based on the internal oscillator */
void Chip_SetupIrcClocking(void)
{
#if defined(USE_ROM_API)
uint32_t cmd[4], resp[2];
#endif
/* Turn on the IRC by clearing the power down bit */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_IRC_PD);
/* Select the PLL input in the IRC */
Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_IRC);
/* Setup FLASH access */
Chip_FMC_SetFLASHAccess(FLASHTIM_2CLK_CPU);
#if defined(USE_ROM_API)
/* Use ROM API for setting up PLL */
cmd[0] = Chip_Clock_GetIntOscRate() / 1000; /* in KHz */
cmd[1] = 48000000 / 1000; /* 48MHz system clock rate */
cmd[2] = CPU_FREQ_EQU;
cmd[3] = 48000000 / 10000; /* Timeout */
LPC_PWRD_API->set_pll(cmd, resp);
/* Dead loop on fail */
while (resp[0] != PLL_CMD_SUCCESS) {}
#else
/* Power down PLL to change the PLL divider ratio */
Chip_SYSCTL_PowerDown(SYSCTL_POWERDOWN_SYSPLL_PD);
/* Configure the PLL M and P dividers */
/* Setup PLL for main oscillator rate (FCLKIN = 12MHz) * 4 = 48MHz
MSEL = 3 (this is pre-decremented), PSEL = 1 (for P = 2)
FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 4 = 48MHz
FCCO = FCLKOUT * 2 * P = 48MHz * 2 * 2 = 192MHz (within FCCO range) */
Chip_Clock_SetupSystemPLL(3, 1);
/* Turn on the PLL by clearing the power down bit */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSPLL_PD);
/* Wait for PLL to lock */
while (!Chip_Clock_IsSystemPLLLocked()) {}
/* Set system clock divider to 1 */
Chip_Clock_SetSysClockDiv(1);
/* Set main clock source to the system PLL. This will drive 24MHz
for the main clock and 24MHz for the system clock */
Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_PLLOUT);
#endif
}
/* Shutdown DAC peripheral */
void Chip_DAC_DeInit(LPC_DAC_T *pDAC)
{
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_DAC);
Chip_SYSCTL_PowerDown(SYSCTL_POWERDOWN_DAC_PD);
}