/*******************************************************************************
* Function Name: SPIM_Init
********************************************************************************
*
* Summary:
* Inits/Restores default SPIM configuration provided with customizer.
*
* Parameters:
* None.
*
* Return:
* None.
*
* Side Effects:
* When this function is called it initializes all of the necessary parameters
* for execution. i.e. setting the initial interrupt mask, configuring the
* interrupt service routine, configuring the bit-counter parameters and
* clearing the FIFO and Status Register.
*
* Reentrant:
* No.
*
*******************************************************************************/
void SPIM_Init(void)
{
/* Initialize the Bit counter */
SPIM_COUNTER_PERIOD_REG = SPIM_BITCTR_INIT;
/* ISR initialization */
#if(SPIM_InternalTxInterruptEnabled)
CyIntDisable(SPIM_TX_ISR_NUMBER);
/* Set the ISR to point to the SPIM_isr Interrupt. */
CyIntSetVector(SPIM_TX_ISR_NUMBER, SPIM_TX_ISR);
/* Set the priority. */
CyIntSetPriority(SPIM_TX_ISR_NUMBER, SPIM_TX_ISR_PRIORITY);
#endif /* SPIM_InternalTxInterruptEnabled */
#if(SPIM_InternalRxInterruptEnabled)
CyIntDisable(SPIM_RX_ISR_NUMBER);
/* Set the ISR to point to the SPIM_isr Interrupt. */
CyIntSetVector(SPIM_RX_ISR_NUMBER, SPIM_RX_ISR);
/* Set the priority. */
CyIntSetPriority(SPIM_RX_ISR_NUMBER, SPIM_RX_ISR_PRIORITY);
#endif /* SPIM_InternalRxInterruptEnabled */
/* Clear any stray data from the RX and TX FIFO */
SPIM_ClearFIFO();
#if(SPIM_RXBUFFERSIZE > 4u)
SPIM_rxBufferRead = 0u;
SPIM_rxBufferWrite = 0u;
#endif /* SPIM_RXBUFFERSIZE > 4u */
#if(SPIM_TXBUFFERSIZE > 4u)
SPIM_txBufferRead = 0u;
SPIM_txBufferWrite = 0u;
#endif /* SPIM_TXBUFFERSIZE > 4u */
(void) SPIM_ReadTxStatus(); /* Clear any pending status bits */
(void) SPIM_ReadRxStatus(); /* Clear any pending status bits */
/* Configure the Initial interrupt mask */
#if (SPIM_TXBUFFERSIZE > 4u)
SPIM_TX_STATUS_MASK_REG = SPIM_TX_INIT_INTERRUPTS_MASK &
~SPIM_STS_TX_FIFO_NOT_FULL;
#else /* SPIM_TXBUFFERSIZE < 4u */
SPIM_TX_STATUS_MASK_REG = SPIM_TX_INIT_INTERRUPTS_MASK;
#endif /* SPIM_TXBUFFERSIZE > 4u */
SPIM_RX_STATUS_MASK_REG = SPIM_RX_INIT_INTERRUPTS_MASK;
}
/*******************************************************************************
* Function Name: SCB_1_UartInit
****************************************************************************//**
*
* Configures the SCB for the UART operation.
*
*******************************************************************************/
void SCB_1_UartInit(void)
{
/* Configure UART interface */
SCB_1_CTRL_REG = SCB_1_UART_DEFAULT_CTRL;
/* Configure sub-mode: UART, SmartCard or IrDA */
SCB_1_UART_CTRL_REG = SCB_1_UART_DEFAULT_UART_CTRL;
/* Configure RX direction */
SCB_1_UART_RX_CTRL_REG = SCB_1_UART_DEFAULT_UART_RX_CTRL;
SCB_1_RX_CTRL_REG = SCB_1_UART_DEFAULT_RX_CTRL;
SCB_1_RX_FIFO_CTRL_REG = SCB_1_UART_DEFAULT_RX_FIFO_CTRL;
SCB_1_RX_MATCH_REG = SCB_1_UART_DEFAULT_RX_MATCH_REG;
/* Configure TX direction */
SCB_1_UART_TX_CTRL_REG = SCB_1_UART_DEFAULT_UART_TX_CTRL;
SCB_1_TX_CTRL_REG = SCB_1_UART_DEFAULT_TX_CTRL;
SCB_1_TX_FIFO_CTRL_REG = SCB_1_UART_DEFAULT_TX_FIFO_CTRL;
#if !(SCB_1_CY_SCBIP_V0 || SCB_1_CY_SCBIP_V1)
SCB_1_UART_FLOW_CTRL_REG = SCB_1_UART_DEFAULT_FLOW_CTRL;
#endif /* !(SCB_1_CY_SCBIP_V0 || SCB_1_CY_SCBIP_V1) */
/* Configure interrupt with UART handler but do not enable it */
#if(SCB_1_SCB_IRQ_INTERNAL)
CyIntDisable (SCB_1_ISR_NUMBER);
CyIntSetPriority(SCB_1_ISR_NUMBER, SCB_1_ISR_PRIORITY);
(void) CyIntSetVector(SCB_1_ISR_NUMBER, &SCB_1_SPI_UART_ISR);
#endif /* (SCB_1_SCB_IRQ_INTERNAL) */
/* Configure WAKE interrupt */
#if(SCB_1_UART_RX_WAKEUP_IRQ)
CyIntDisable (SCB_1_RX_WAKE_ISR_NUMBER);
CyIntSetPriority(SCB_1_RX_WAKE_ISR_NUMBER, SCB_1_RX_WAKE_ISR_PRIORITY);
(void) CyIntSetVector(SCB_1_RX_WAKE_ISR_NUMBER, &SCB_1_UART_WAKEUP_ISR);
#endif /* (SCB_1_UART_RX_WAKEUP_IRQ) */
/* Configure interrupt sources */
SCB_1_INTR_I2C_EC_MASK_REG = SCB_1_UART_DEFAULT_INTR_I2C_EC_MASK;
SCB_1_INTR_SPI_EC_MASK_REG = SCB_1_UART_DEFAULT_INTR_SPI_EC_MASK;
SCB_1_INTR_SLAVE_MASK_REG = SCB_1_UART_DEFAULT_INTR_SLAVE_MASK;
SCB_1_INTR_MASTER_MASK_REG = SCB_1_UART_DEFAULT_INTR_MASTER_MASK;
SCB_1_INTR_RX_MASK_REG = SCB_1_UART_DEFAULT_INTR_RX_MASK;
SCB_1_INTR_TX_MASK_REG = SCB_1_UART_DEFAULT_INTR_TX_MASK;
/* Configure TX interrupt sources to restore. */
SCB_1_IntrTxMask = LO16(SCB_1_INTR_TX_MASK_REG);
#if(SCB_1_INTERNAL_RX_SW_BUFFER_CONST)
SCB_1_rxBufferHead = 0u;
SCB_1_rxBufferTail = 0u;
SCB_1_rxBufferOverflow = 0u;
#endif /* (SCB_1_INTERNAL_RX_SW_BUFFER_CONST) */
#if(SCB_1_INTERNAL_TX_SW_BUFFER_CONST)
SCB_1_txBufferHead = 0u;
SCB_1_txBufferTail = 0u;
#endif /* (SCB_1_INTERNAL_TX_SW_BUFFER_CONST) */
}
/*******************************************************************************
* Function Name: UART_BCP_UartInit
********************************************************************************
*
* Summary:
* Configures the SCB for the UART operation.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void UART_BCP_UartInit(void)
{
/* Configure UART interface */
UART_BCP_CTRL_REG = UART_BCP_UART_DEFAULT_CTRL;
/* Configure sub-mode: UART, SmartCard or IrDA */
UART_BCP_UART_CTRL_REG = UART_BCP_UART_DEFAULT_UART_CTRL;
/* Configure RX direction */
UART_BCP_UART_RX_CTRL_REG = UART_BCP_UART_DEFAULT_UART_RX_CTRL;
UART_BCP_RX_CTRL_REG = UART_BCP_UART_DEFAULT_RX_CTRL;
UART_BCP_RX_FIFO_CTRL_REG = UART_BCP_UART_DEFAULT_RX_FIFO_CTRL;
UART_BCP_RX_MATCH_REG = UART_BCP_UART_DEFAULT_RX_MATCH_REG;
/* Configure TX direction */
UART_BCP_UART_TX_CTRL_REG = UART_BCP_UART_DEFAULT_UART_TX_CTRL;
UART_BCP_TX_CTRL_REG = UART_BCP_UART_DEFAULT_TX_CTRL;
UART_BCP_TX_FIFO_CTRL_REG = UART_BCP_UART_DEFAULT_TX_FIFO_CTRL;
#if !(UART_BCP_CY_SCBIP_V0 || UART_BCP_CY_SCBIP_V1)
UART_BCP_UART_FLOW_CTRL_REG = UART_BCP_UART_DEFAULT_FLOW_CTRL;
#endif /* !(UART_BCP_CY_SCBIP_V0 || UART_BCP_CY_SCBIP_V1) */
/* Configure interrupt with UART handler but do not enable it */
#if(UART_BCP_SCB_IRQ_INTERNAL)
CyIntDisable (UART_BCP_ISR_NUMBER);
CyIntSetPriority(UART_BCP_ISR_NUMBER, UART_BCP_ISR_PRIORITY);
(void) CyIntSetVector(UART_BCP_ISR_NUMBER, &UART_BCP_SPI_UART_ISR);
#endif /* (UART_BCP_SCB_IRQ_INTERNAL) */
/* Configure WAKE interrupt */
#if(UART_BCP_UART_RX_WAKEUP_IRQ)
CyIntDisable (UART_BCP_RX_WAKE_ISR_NUMBER);
CyIntSetPriority(UART_BCP_RX_WAKE_ISR_NUMBER, UART_BCP_RX_WAKE_ISR_PRIORITY);
(void) CyIntSetVector(UART_BCP_RX_WAKE_ISR_NUMBER, &UART_BCP_UART_WAKEUP_ISR);
#endif /* (UART_BCP_UART_RX_WAKEUP_IRQ) */
/* Configure interrupt sources */
UART_BCP_INTR_I2C_EC_MASK_REG = UART_BCP_UART_DEFAULT_INTR_I2C_EC_MASK;
UART_BCP_INTR_SPI_EC_MASK_REG = UART_BCP_UART_DEFAULT_INTR_SPI_EC_MASK;
UART_BCP_INTR_SLAVE_MASK_REG = UART_BCP_UART_DEFAULT_INTR_SLAVE_MASK;
UART_BCP_INTR_MASTER_MASK_REG = UART_BCP_UART_DEFAULT_INTR_MASTER_MASK;
UART_BCP_INTR_RX_MASK_REG = UART_BCP_UART_DEFAULT_INTR_RX_MASK;
UART_BCP_INTR_TX_MASK_REG = UART_BCP_UART_DEFAULT_INTR_TX_MASK;
#if(UART_BCP_INTERNAL_RX_SW_BUFFER_CONST)
UART_BCP_rxBufferHead = 0u;
UART_BCP_rxBufferTail = 0u;
UART_BCP_rxBufferOverflow = 0u;
#endif /* (UART_BCP_INTERNAL_RX_SW_BUFFER_CONST) */
#if(UART_BCP_INTERNAL_TX_SW_BUFFER_CONST)
UART_BCP_txBufferHead = 0u;
UART_BCP_txBufferTail = 0u;
#endif /* (UART_BCP_INTERNAL_TX_SW_BUFFER_CONST) */
}
CY_CFG_SECTION
static void ClockSetup(void)
{
/* Enable HALF_EN before trimming for the flash accelerator. */
CY_SET_REG32((void CYXDATA *)(CYREG_CLK_SELECT), (CY_GET_REG32((void *)CYREG_CLK_SELECT) | 0x00040000u));
/* Setup and trim IMO based on desired frequency. */
CySysClkWriteImoFreq(24u);
/* Disable HALF_EN since it is not required at this IMO frequency. */
CY_SET_REG32((void CYXDATA *)(CYREG_CLK_SELECT), (CY_GET_REG32((void *)CYREG_CLK_SELECT) & 0xFFFBFFFFu));
/* CYDEV_CLK_ILO_CONFIG Starting address: CYDEV_CLK_ILO_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_ILO_CONFIG), 0x80000006u);
/* CYDEV_CLK_SELECT00 Starting address: CYDEV_CLK_SELECT00 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT03), 0x00000020u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT08), 0x00000010u);
/* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG), 0x80000000u);
/* CYDEV_CLK_DIVIDER_A00 Starting address: CYDEV_CLK_DIVIDER_A00 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_DIVIDER_A00), 0x80000001u);
/* CYDEV_CLK_DIVIDER_B00 Starting address: CYDEV_CLK_DIVIDER_B00 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_DIVIDER_B00), 0x800000CFu);
(void)CyIntSetVector(9u, &CySysWdtIsr);
CyIntEnable(9u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x00000000u);
}
/*****************************************************************************
* Function Name: _Watchdog_Init()
******************************************************************************
* Summary:
* Initialize the watchdog.
*
* Parameters:
* None.
*
* Return:
* None.
*
* Note:
*
*****************************************************************************/
void _Watchdog_Init(void)
{
// Unlock the WDT registers for modification.
CySysWdtUnlock();
// Write Mode for Counters as Interrupt on Match.
CySysWdtWriteMode(CY_SYS_WDT_COUNTER0, CY_SYS_WDT_MODE_INT);
CySysWdtWriteMode(CY_SYS_WDT_COUNTER1, CY_SYS_WDT_MODE_INT);
// Set Clear on Match for Counters.
CySysWdtWriteClearOnMatch(CY_SYS_WDT_COUNTER0, TRUE);
CySysWdtWriteClearOnMatch(CY_SYS_WDT_COUNTER1, TRUE);
// Set Watchdog interrupt to lower priority.
CyIntSetPriority(WATCHDOG_INT_VEC_NUM, WATCHDOG_INT_VEC_PRIORITY);
// Enable Watchdog Interrupt using Interrupt number.
CyIntEnable(WATCHDOG_INT_VEC_NUM);
// Write the match value in Counters.
CySysWdtWriteMatch(CY_SYS_WDT_COUNTER0, WATCHDOG_COUNTER0_PERIOD);
CySysWdtWriteMatch(CY_SYS_WDT_COUNTER1, WATCHDOG_COUNTER1_PERIOD);
// Enable Counters.
CySysWdtEnable(CY_SYS_WDT_COUNTER0_MASK);
CySysWdtEnable(CY_SYS_WDT_COUNTER1_MASK);
// Lock Watchdog to prevent further changes.
CySysWdtLock();
// Set the Watchdog Interrupt vector to the address of Interrupt routine
// _Watchdog_Handler.
CyIntSetVector(WATCHDOG_INT_VEC_NUM, &_Watchdog_Handler);
}
/*******************************************************************************
* Function Name: EzI2C_SaveConfig
********************************************************************************
*
* Summary:
* The Enable wakeup from Sleep Mode selection influences this function
* implementation:
* Unchecked: Stores the component non-retention configuration registers.
* Checked: Enables backup regulator of the I2C hardware. If a transaction
* intended for component executes during this function call,
* it waits until the current transaction is completed and
* I2C hardware is ready to go to sleep mode. All subsequent
* I2C traffic is NAKed until the device is put to sleep mode.
*
* Parameters:
* None.
*
* Return:
* None.
*
* Global variables:
* EzI2C_backup - The non-retention registers are saved to.
*
* Reentrant:
* No.
*
*******************************************************************************/
void EzI2C_SaveConfig(void)
{
#if (EzI2C_WAKEUP_ENABLED)
uint8 interruptState;
#endif /* (EzI2C_WAKEUP_ENABLED) */
/* Store component configuration into backup structure */
EzI2C_backup.cfg = EzI2C_CFG_REG;
EzI2C_backup.xcfg = EzI2C_XCFG_REG;
EzI2C_backup.adr = EzI2C_ADDR_REG;
EzI2C_backup.clkDiv1 = EzI2C_CLKDIV1_REG;
EzI2C_backup.clkDiv2 = EzI2C_CLKDIV2_REG;
#if (EzI2C_WAKEUP_ENABLED)
/* Enable I2C backup regulator */
interruptState = CyEnterCriticalSection();
EzI2C_PWRSYS_CR1_REG |= EzI2C_PWRSYS_CR1_I2C_BACKUP;
CyExitCriticalSection(interruptState);
/* Wait for completion of the current transaction. The following
* transactions have to be NACKed until the device enters the low power mode.
* After a wakeup, the force NACK bit is cleared automatically.
*/
EzI2C_XCFG_REG |= EzI2C_XCFG_FORCE_NACK;
while (0u == (EzI2C_XCFG_REG & EzI2C_XCFG_SLEEP_READY))
{
}
/* Setup wakeup interrupt */
EzI2C_DisableInt();
EzI2C_wakeupSource = 0u; /* Clear wakeup event */
(void) CyIntSetVector(EzI2C_ISR_NUMBER, &EzI2C_WAKEUP_ISR);
EzI2C_EnableInt();
#endif /* (EzI2C_WAKEUP_ENABLED) */
}
CY_CFG_SECTION
static void ClockSetup(void)
{
/* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */
CY_SET_REG32((void CYXDATA *)(CYREG_CPUSS_FLASH_CTL), (0x0012u));
/* Setup and trim IMO based on desired frequency. */
CySysClkWriteImoFreq(48u);
/* CYDEV_CLK_ILO_CONFIG Starting address: CYDEV_CLK_ILO_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_ILO_CONFIG), 0x80000006u);
/* Setup phase aligned clocks */
CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL0, 0x00002200u);
CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF40u);
CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL1, 0x00002200u);
CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF41u);
/* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG), 0x80000000u);
/* CYDEV_CLK_SELECT Starting address: CYDEV_CLK_SELECT */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT), 0x00040000u);
/* CYDEV_PERI_PCLK_CTL5 Starting address: CYDEV_PERI_PCLK_CTL5 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL5), 0x00000040u);
/* CYDEV_PERI_PCLK_CTL3 Starting address: CYDEV_PERI_PCLK_CTL3 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL3), 0x00000041u);
(void)CyIntSetVector(7u, &CySysWdtIsr);
CyIntEnable(7u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x00000000u);
}
CY_CFG_SECTION
static void ClockSetup(void)
{
/* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */
CY_SET_REG32((void CYXDATA *)(CYREG_CPUSS_FLASH_CTL), (0x0012u));
/* Start the WCO */
CySysClkWcoStart();
CyDelayCycles(12000000u); /* WCO may take up to 500ms to start */
(void)CySysClkWcoSetPowerMode(CY_SYS_CLK_WCO_LPM); /* Switch to the low power mode */
/* Setup and trim IMO based on desired frequency. */
CySysClkWriteImoFreq(48u);
/* CYDEV_CLK_ILO_CONFIG Starting address: CYDEV_CLK_ILO_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_ILO_CONFIG), 0x80000006u);
/* CYDEV_WDT_CONFIG Starting address: CYDEV_WDT_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x40000000u);
/* Enable fast start mode for XO */
CY_SET_REG32((void*)CYREG_BLE_BLERD_BB_XO, CY_GET_REG32((void*)CYREG_BLE_BLERD_BB_XO) | (uint32)0x02u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLERD_BB_XO_CAPTRIM), 0x00003E2Du);
/*Set XTAL(ECO) divider*/
CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLESS_XTAL_CLK_DIV_CONFIG), 0x00000000u);
/* Disable Crystal Stable Interrupt before enabling ECO */
CY_SET_REG32((void*)CYREG_BLE_BLESS_LL_DSM_CTRL, CY_GET_REG32((void*)CYREG_BLE_BLESS_LL_DSM_CTRL) & (~(uint32)0x08u));
/* Start the ECO and do not check status since it is not needed for HFCLK */
(void)CySysClkEcoStart(2000u);
CyDelayUs(1500u); /* Wait to stabalize */
/* Setup phase aligned clocks */
CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL1, 0x00BB7F00u);
CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF41u);
CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL0, 0x0001A000u);
CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF40u);
/* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG), 0x80000000u);
/* CYDEV_CLK_SELECT Starting address: CYDEV_CLK_SELECT */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT), 0x00040000u);
/* CYDEV_PERI_PCLK_CTL7 Starting address: CYDEV_PERI_PCLK_CTL7 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL7), 0x00000041u);
/* CYDEV_PERI_PCLK_CTL2 Starting address: CYDEV_PERI_PCLK_CTL2 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL2), 0x00000040u);
(void)CyIntSetVector(8u, &CySysWdtIsr);
CyIntEnable(8u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_MATCH), 0x00000020u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x40000005u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONTROL), 0x00000008u);
while ((CY_GET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONTROL)) & 0x00000008u) != 0u) { }
CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONTROL), 0x00000001u);
}
/*******************************************************************************
* Function Name: I2C_1_I2CInit
********************************************************************************
*
* Summary:
* Configures the SCB for the I2C operation.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void I2C_1_I2CInit(void)
{
/* Configure I2C interface */
I2C_1_CTRL_REG = I2C_1_I2C_DEFAULT_CTRL;
I2C_1_I2C_CTRL_REG = I2C_1_I2C_DEFAULT_I2C_CTRL;
#if(I2C_1_CY_SCBIP_V0)
/* Adjust SDA filter settings. Ticket ID#150521 */
I2C_1_SET_I2C_CFG_SDA_FILT_TRIM(I2C_1_EC_AM_I2C_CFG_SDA_FILT_TRIM);
#endif /* (I2C_1_CY_SCBIP_V0) */
/* Configure RX direction */
I2C_1_RX_CTRL_REG = I2C_1_I2C_DEFAULT_RX_CTRL;
I2C_1_RX_FIFO_CTRL_REG = I2C_1_I2C_DEFAULT_RX_FIFO_CTRL;
/* Set default address and mask */
I2C_1_RX_MATCH_REG = I2C_1_I2C_DEFAULT_RX_MATCH;
/* Configure TX direction */
I2C_1_TX_CTRL_REG = I2C_1_I2C_DEFAULT_TX_CTRL;
I2C_1_TX_FIFO_CTRL_REG = I2C_1_I2C_DEFAULT_TX_FIFO_CTRL;
/* Configure interrupt with I2C handler but do not enable it */
CyIntDisable (I2C_1_ISR_NUMBER);
CyIntSetPriority(I2C_1_ISR_NUMBER, I2C_1_ISR_PRIORITY);
#if(!I2C_1_I2C_EXTERN_INTR_HANDLER)
(void) CyIntSetVector(I2C_1_ISR_NUMBER, &I2C_1_I2C_ISR);
#endif /* (I2C_1_I2C_EXTERN_INTR_HANDLER) */
/* Configure interrupt sources */
#if(!I2C_1_CY_SCBIP_V1_I2C_ONLY)
I2C_1_INTR_SPI_EC_MASK_REG = I2C_1_I2C_DEFAULT_INTR_SPI_EC_MASK;
#endif /* (!I2C_1_CY_SCBIP_V1_I2C_ONLY) */
I2C_1_INTR_I2C_EC_MASK_REG = I2C_1_I2C_DEFAULT_INTR_I2C_EC_MASK;
I2C_1_INTR_SLAVE_MASK_REG = I2C_1_I2C_DEFAULT_INTR_SLAVE_MASK;
I2C_1_INTR_MASTER_MASK_REG = I2C_1_I2C_DEFAULT_INTR_MASTER_MASK;
I2C_1_INTR_RX_MASK_REG = I2C_1_I2C_DEFAULT_INTR_RX_MASK;
I2C_1_INTR_TX_MASK_REG = I2C_1_I2C_DEFAULT_INTR_TX_MASK;
/* Configure global variables */
I2C_1_state = I2C_1_I2C_FSM_IDLE;
#if(I2C_1_I2C_SLAVE)
/* Internal slave variable */
I2C_1_slStatus = 0u;
I2C_1_slRdBufIndex = 0u;
I2C_1_slWrBufIndex = 0u;
I2C_1_slOverFlowCount = 0u;
#endif /* (I2C_1_I2C_SLAVE) */
#if(I2C_1_I2C_MASTER)
/* Internal master variable */
I2C_1_mstrStatus = 0u;
I2C_1_mstrRdBufIndex = 0u;
I2C_1_mstrWrBufIndex = 0u;
#endif /* (I2C_1_I2C_MASTER) */
}
CY_CFG_SECTION
static void ClockSetup(void)
{
/* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */
CY_SET_REG32((void CYXDATA *)(CYREG_CPUSS_FLASH_CTL), (0x0012u));
/* Start the WCO */
CySysClkWcoStart();
(void)CySysClkWcoSetPowerMode(CY_SYS_CLK_WCO_LPM); /* Switch to the low power mode */
/* Setup and trim IMO based on desired frequency. */
CySysClkWriteImoFreq(24u);
/* CYDEV_CLK_ILO_CONFIG Starting address: CYDEV_CLK_ILO_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_ILO_CONFIG), 0x80000006u);
/* Enable fast start mode for XO */
CY_SET_REG32((void*)CYREG_BLE_BLERD_BB_XO, CY_GET_REG32((void*)CYREG_BLE_BLERD_BB_XO) | (uint32)0x02u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLERD_BB_XO_CAPTRIM), 0x00003E2Du);
/* Disable Crystal Stable Interrupt before enabling ECO */
CY_SET_REG32((void*)CYREG_BLE_BLESS_LL_DSM_CTRL, CY_GET_REG32((void*)CYREG_BLE_BLESS_LL_DSM_CTRL) & (~(uint32)0x08u));
/* Start the ECO and do not check status since it is not needed for HFCLK */
(void)CySysClkEcoStart(2000u);
CyDelayUs(1500u); /* Wait to stabalize */
/* Setup phase aligned clocks */
CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL2, 0x0001DF00u);
CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF42u);
CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL0, 0x00000E00u);
CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF40u);
CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL1, 0x00001000u);
CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF41u);
/* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG), 0x80000000u);
/* CYDEV_PERI_PCLK_CTL11 Starting address: CYDEV_PERI_PCLK_CTL11 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL11), 0x00000042u);
/* CYDEV_PERI_PCLK_CTL8 Starting address: CYDEV_PERI_PCLK_CTL8 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL8), 0x00000042u);
/* CYDEV_PERI_PCLK_CTL7 Starting address: CYDEV_PERI_PCLK_CTL7 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL7), 0x00000042u);
/* CYDEV_PERI_PCLK_CTL2 Starting address: CYDEV_PERI_PCLK_CTL2 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL2), 0x00000040u);
/* CYDEV_PERI_PCLK_CTL1 Starting address: CYDEV_PERI_PCLK_CTL1 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL1), 0x00000041u);
(void)CyIntSetVector(8u, &CySysWdtIsr);
CyIntEnable(8u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x00000000u);
/* Set Flash Cycles based on newly configured 24.00MHz HFCLK. */
CY_SET_REG32((void CYXDATA *)(CYREG_CPUSS_FLASH_CTL), (0x0011u));
}
/*******************************************************************************
* Function Name: USBUART_Suspend
********************************************************************************
*
* Summary:
* This function disables the USBFS block and prepares for power down mode.
*
* Parameters:
* None.
*
* Return:
* None.
*
* Global variables:
* USBUART_backup.enable: modified.
*
* Reentrant:
* No.
*
*******************************************************************************/
void USBUART_Suspend(void)
{
uint8 enableInterrupts;
enableInterrupts = CyEnterCriticalSection();
if((CY_GET_REG8(USBUART_CR0_PTR) & USBUART_CR0_ENABLE) != 0u)
{ /* USB block is enabled */
USBUART_backup.enableState = 1u;
#if(USBUART_EP_MM != USBUART__EP_MANUAL)
USBUART_Stop_DMA(USBUART_MAX_EP); /* Stop all DMAs */
#endif /* USBUART_EP_MM != USBUART__EP_MANUAL */
/* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled */
USBUART_USBIO_CR0_REG &= (uint8)~USBUART_USBIO_CR0_TEN;
CyDelayUs(0u); /*~50ns delay */
/* Disable the USBIO by asserting PM.USB_CR0.fsusbio_pd_n(Inverted) and pd_pullup_hv(Inverted) high. */
USBUART_PM_USB_CR0_REG &=
(uint8)~(USBUART_PM_USB_CR0_PD_N | USBUART_PM_USB_CR0_PD_PULLUP_N);
/* Disable the SIE */
USBUART_CR0_REG &= (uint8)~USBUART_CR0_ENABLE;
CyDelayUs(0u); /* ~50ns delay */
/* Store mode and Disable VRegulator*/
USBUART_backup.mode = USBUART_CR1_REG & USBUART_CR1_REG_ENABLE;
USBUART_CR1_REG &= (uint8)~USBUART_CR1_REG_ENABLE;
CyDelayUs(1u); /* 0.5 us min delay */
/* Disable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/
USBUART_PM_USB_CR0_REG &= (uint8)~USBUART_PM_USB_CR0_REF_EN;
/* Switch DP and DM terminals to GPIO mode and disconnect 1.5k pullup*/
USBUART_USBIO_CR1_REG |= USBUART_USBIO_CR1_IOMODE;
/* Disable USB in ACT PM */
USBUART_PM_ACT_CFG_REG &= (uint8)~USBUART_PM_ACT_EN_FSUSB;
/* Disable USB block for Standby Power Mode */
USBUART_PM_STBY_CFG_REG &= (uint8)~USBUART_PM_STBY_EN_FSUSB;
CyDelayUs(1u); /* min 0.5us delay required */
}
else
{
USBUART_backup.enableState = 0u;
}
CyExitCriticalSection(enableInterrupts);
/* Set the DP Interrupt for wake-up from sleep mode. */
#if(USBUART_DP_ISR_REMOVE == 0u)
(void) CyIntSetVector(USBUART_DP_INTC_VECT_NUM, &USBUART_DP_ISR);
CyIntSetPriority(USBUART_DP_INTC_VECT_NUM, USBUART_DP_INTC_PRIOR);
CyIntClearPending(USBUART_DP_INTC_VECT_NUM);
CyIntEnable(USBUART_DP_INTC_VECT_NUM);
#endif /* (USBUART_DP_ISR_REMOVE == 0u) */
}
/*******************************************************************************
* Function Name: I2COLED_RestoreConfig
********************************************************************************
*
* Summary:
* The Enable wakeup from Sleep Mode selection influences this function
* implementation:
* Unchecked: Restores the component non-retention configuration registers
* to the state they were in before I2C_Sleep() or I2C_SaveConfig()
* was called.
* Checked: Disables the backup regulator of the I2C hardware. Sets up the
* regular component interrupt handler and generates the component
* interrupt if it was wake up source to release the bus and
* continue in-coming I2C transaction.
*
* Parameters:
* None.
*
* Return:
* None.
*
* Global Variables:
* I2COLED_backup - The global variable used to save the component
* configuration and non-retention registers before
* exiting the sleep mode.
*
* Reentrant:
* No.
*
* Side Effects:
* Calling this function before I2COLED_SaveConfig() or
* I2COLED_Sleep() will lead to unpredictable results.
*
*******************************************************************************/
void I2COLED_RestoreConfig(void)
{
#if (I2COLED_FF_IMPLEMENTED)
uint8 intState;
if (I2COLED_CHECK_PWRSYS_I2C_BACKUP)
/* Low power mode was Sleep - backup regulator is enabled */
{
/* Enable backup regulator in active mode */
intState = CyEnterCriticalSection();
I2COLED_PWRSYS_CR1_REG &= (uint8) ~I2COLED_PWRSYS_CR1_I2C_REG_BACKUP;
CyExitCriticalSection(intState);
/* Restore master */
I2COLED_CFG_REG = I2COLED_backup.cfg;
}
else
/* Low power mode was Hibernate - backup regulator is disabled. All registers are cleared */
{
#if (I2COLED_WAKEUP_ENABLED)
/* Disable power to block before register restore */
intState = CyEnterCriticalSection();
I2COLED_ACT_PWRMGR_REG &= (uint8) ~I2COLED_ACT_PWR_EN;
I2COLED_STBY_PWRMGR_REG &= (uint8) ~I2COLED_STBY_PWR_EN;
CyExitCriticalSection(intState);
/* Enable component in I2C_Wakeup() after register restore */
I2COLED_backup.enableState = I2COLED_ENABLE;
#endif /* (I2COLED_WAKEUP_ENABLED) */
/* Restore component registers after Hibernate */
I2COLED_XCFG_REG = I2COLED_backup.xcfg;
I2COLED_CFG_REG = I2COLED_backup.cfg;
I2COLED_ADDR_REG = I2COLED_backup.addr;
I2COLED_CLKDIV1_REG = I2COLED_backup.clkDiv1;
I2COLED_CLKDIV2_REG = I2COLED_backup.clkDiv2;
}
#if (I2COLED_WAKEUP_ENABLED)
I2COLED_DisableInt();
(void) CyIntSetVector(I2COLED_ISR_NUMBER, &I2COLED_ISR);
if (0u != I2COLED_wakeupSource)
{
/* Generate interrupt to process incoming transaction */
I2COLED_SetPendingInt();
}
I2COLED_EnableInt();
#endif /* (I2COLED_WAKEUP_ENABLED) */
#else
I2COLED_CFG_REG = I2COLED_backup.control;
#endif /* (I2COLED_FF_IMPLEMENTED) */
#if (I2COLED_TIMEOUT_ENABLED)
I2COLED_TimeoutRestoreConfig();
#endif /* (I2COLED_TIMEOUT_ENABLED) */
}
/*******************************************************************************
* Function Name: SPI_Init
********************************************************************************
*
* Summary:
* Inits/Restores default SPIM configuration provided with customizer.
*
* Parameters:
* None.
*
* Return:
* None.
*
* Side Effects:
* When this function is called it initializes all of the necessary parameters
* for execution. i.e. setting the initial interrupt mask, configuring the
* interrupt service routine, configuring the bit-counter parameters and
* clearing the FIFO and Status Register.
*
* Reentrant:
* No.
*
*******************************************************************************/
void SPI_Init(void)
{
/* Initialize the Bit counter */
SPI_COUNTER_PERIOD_REG = SPI_BITCTR_INIT;
/* Init TX ISR */
#if(0u != SPI_INTERNAL_TX_INT_ENABLED)
CyIntDisable (SPI_TX_ISR_NUMBER);
CyIntSetPriority (SPI_TX_ISR_NUMBER, SPI_TX_ISR_PRIORITY);
(void) CyIntSetVector(SPI_TX_ISR_NUMBER, &SPI_TX_ISR);
#endif /* (0u != SPI_INTERNAL_TX_INT_ENABLED) */
/* Init RX ISR */
#if(0u != SPI_INTERNAL_RX_INT_ENABLED)
CyIntDisable (SPI_RX_ISR_NUMBER);
CyIntSetPriority (SPI_RX_ISR_NUMBER, SPI_RX_ISR_PRIORITY);
(void) CyIntSetVector(SPI_RX_ISR_NUMBER, &SPI_RX_ISR);
#endif /* (0u != SPI_INTERNAL_RX_INT_ENABLED) */
/* Clear any stray data from the RX and TX FIFO */
SPI_ClearFIFO();
#if(SPI_RX_SOFTWARE_BUF_ENABLED)
SPI_rxBufferFull = 0u;
SPI_rxBufferRead = 0u;
SPI_rxBufferWrite = 0u;
#endif /* (SPI_RX_SOFTWARE_BUF_ENABLED) */
#if(SPI_TX_SOFTWARE_BUF_ENABLED)
SPI_txBufferFull = 0u;
SPI_txBufferRead = 0u;
SPI_txBufferWrite = 0u;
#endif /* (SPI_TX_SOFTWARE_BUF_ENABLED) */
(void) SPI_ReadTxStatus(); /* Clear Tx status and swStatusTx */
(void) SPI_ReadRxStatus(); /* Clear Rx status and swStatusRx */
/* Configure TX and RX interrupt mask */
SPI_TX_STATUS_MASK_REG = SPI_TX_INIT_INTERRUPTS_MASK;
SPI_RX_STATUS_MASK_REG = SPI_RX_INIT_INTERRUPTS_MASK;
}
/*******************************************************************************
* Function Name: I2COLED_SaveConfig
********************************************************************************
*
* Summary:
* The Enable wakeup from Sleep Mode selection influences this function
* implementation:
* Unchecked: Stores the component non-retention configuration registers.
* Checked: Disables the master, if it was enabled before, and enables
* backup regulator of the I2C hardware. If a transaction intended
* for component executes during this function call, it waits until
* the current transaction is completed and I2C hardware is ready
* to enter sleep mode. All subsequent I2C traffic is NAKed until
* the device is put into sleep mode.
*
* Parameters:
* None.
*
* Return:
* None.
*
* Global Variables:
* I2COLED_backup - The global variable used to save the component
* configuration and non-retention registers before
* entering the sleep mode.
*
* Reentrant:
* No.
*
*******************************************************************************/
void I2COLED_SaveConfig(void)
{
#if (I2COLED_FF_IMPLEMENTED)
#if (I2COLED_WAKEUP_ENABLED)
uint8 intState;
#endif /* (I2COLED_WAKEUP_ENABLED) */
/* Store registers before enter low power mode */
I2COLED_backup.cfg = I2COLED_CFG_REG;
I2COLED_backup.xcfg = I2COLED_XCFG_REG;
I2COLED_backup.addr = I2COLED_ADDR_REG;
I2COLED_backup.clkDiv1 = I2COLED_CLKDIV1_REG;
I2COLED_backup.clkDiv2 = I2COLED_CLKDIV2_REG;
#if (I2COLED_WAKEUP_ENABLED)
/* Disable master */
I2COLED_CFG_REG &= (uint8) ~I2COLED_ENABLE_MASTER;
/* Enable backup regulator to keep block powered in low power mode */
intState = CyEnterCriticalSection();
I2COLED_PWRSYS_CR1_REG |= I2COLED_PWRSYS_CR1_I2C_REG_BACKUP;
CyExitCriticalSection(intState);
/* 1) Set force NACK to ignore I2C transactions;
* 2) Wait unti I2C is ready go to Sleep; !!
* 3) These bits are cleared on wake up.
*/
/* Wait when block is ready for sleep */
I2COLED_XCFG_REG |= I2COLED_XCFG_FORCE_NACK;
while (0u == (I2COLED_XCFG_REG & I2COLED_XCFG_RDY_TO_SLEEP))
{
}
/* Setup wakeup interrupt */
I2COLED_DisableInt();
(void) CyIntSetVector(I2COLED_ISR_NUMBER, &I2COLED_WAKEUP_ISR);
I2COLED_wakeupSource = 0u;
I2COLED_EnableInt();
#endif /* (I2COLED_WAKEUP_ENABLED) */
#else
/* Store only address match bit */
I2COLED_backup.control = (I2COLED_CFG_REG & I2COLED_CTRL_ANY_ADDRESS_MASK);
#endif /* (I2COLED_FF_IMPLEMENTED) */
#if (I2COLED_TIMEOUT_ENABLED)
I2COLED_TimeoutSaveConfig();
#endif /* (I2COLED_TIMEOUT_ENABLED) */
}
/*******************************************************************************
* Function Name: quaddec_right_Init
********************************************************************************
*
* Summary:
* Inits/Restores default QuadDec configuration provided with customizer.
*
* Parameters:
* None.
*
* Return:
* None.
*
*******************************************************************************/
void quaddec_right_Init(void)
{
#if (quaddec_right_COUNTER_SIZE == 32u)
/* Disable Interrupt. */
CyIntDisable(quaddec_right_ISR_NUMBER);
/* Set the ISR to point to the quaddec_right_isr Interrupt. */
CyIntSetVector(quaddec_right_ISR_NUMBER, quaddec_right_ISR);
/* Set the priority. */
CyIntSetPriority(quaddec_right_ISR_NUMBER, quaddec_right_ISR_PRIORITY);
#endif /* quaddec_right_COUNTER_SIZE == 32u */
}
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
if (!enable)
CY_SET_REG8(obj->inttypeReg, 0x0);
else if (event == IRQ_RISE)
CY_SET_REG8(obj->inttypeReg, 0x01);
else if (event == IRQ_FALL)
CY_SET_REG8(obj->inttypeReg, 0x02);
else if (event == (IRQ_FALL | IRQ_RISE))
CY_SET_REG8(obj->inttypeReg, 0x03);
else
debug("Did not set any interrupt handler type!\r\n");
obj->intTypeValue = CY_GET_REG8(obj->inttypeReg);
CyIntSetVector(obj->irqLine, handle_interrupt_in);
CyIntEnable(obj->irqLine);
}
/*******************************************************************************
* Function Name: EzI2C_RestoreConfig
********************************************************************************
*
* Summary:
* The Enable wakeup from Sleep Mode selection influences this function
* implementation:
* Unchecked: Restores the component non-retention configuration registers
* to the state they were in before I2C_Sleep() or I2C_SaveConfig()
* was called.
* Checked: Disables the backup regulator of the I2C hardware. Sets up the
* regular component interrupt handler and generates the component
* interrupt if it was wake up source to release the bus and
* continue in-coming I2C transaction.
*
* Parameters:
* None.
*
* Return:
* None.
*
* Global variables:
* EzI2C_backup - the non-retention registers are restored from.
*
* Reentrant:
* No.
*
* Side Effects:
* Calling this function before EzI2C_SaveConfig() or
* EzI2C_Sleep() may produce unexpected behavior.
*
*******************************************************************************/
void EzI2C_RestoreConfig(void)
{
uint8 intState;
if (0u != (EzI2C_PWRSYS_CR1_I2C_BACKUP & EzI2C_PWRSYS_CR1_REG))
/* Exit from Sleep */
{
/* Disable I2C backup regulator */
intState = CyEnterCriticalSection();
EzI2C_PWRSYS_CR1_REG &= (uint8) ~EzI2C_PWRSYS_CR1_I2C_BACKUP;
CyExitCriticalSection(intState);
}
else /* Exit from Hibernate (bit is cleared) or wakeup disabled */
{
#if (EzI2C_WAKEUP_ENABLED)
/* Disable power to I2C block before register restore */
intState = CyEnterCriticalSection();
EzI2C_PM_ACT_CFG_REG &= (uint8) ~EzI2C_ACT_PWR_EN;
EzI2C_PM_STBY_CFG_REG &= (uint8) ~EzI2C_STBY_PWR_EN;
CyExitCriticalSection(intState);
/* Enable component after restore complete */
EzI2C_backup.enableState = EzI2C_ENABLED;
#endif /* (EzI2C_WAKEUP_ENABLED) */
/* Restore component registers: Hibernate disable power */
EzI2C_CFG_REG = EzI2C_backup.cfg;
EzI2C_XCFG_REG = EzI2C_backup.xcfg;
EzI2C_ADDR_REG = EzI2C_backup.adr;
EzI2C_CLKDIV1_REG = EzI2C_backup.clkDiv1;
EzI2C_CLKDIV2_REG = EzI2C_backup.clkDiv2;
}
#if (EzI2C_WAKEUP_ENABLED)
/* Set I2C interrupt to be pending if component is source of wake up */
EzI2C_DisableInt();
(void) CyIntSetVector(EzI2C_ISR_NUMBER, &EzI2C_ISR);
if (0u != EzI2C_wakeupSource)
{
/* Generate interrupt to release I2C bus */
(void) CyIntSetPending(EzI2C_ISR_NUMBER);
}
EzI2C_EnableInt();
#endif /* (EzI2C_WAKEUP_ENABLED) */
}
/*******************************************************************************
* Function Name: SPI_SpiInit
********************************************************************************
*
* Summary:
* Configures the SCB for the SPI operation.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SPI_SpiInit(void)
{
/* Configure SPI interface */
SPI_CTRL_REG = SPI_SPI_DEFAULT_CTRL;
SPI_SPI_CTRL_REG = SPI_SPI_DEFAULT_SPI_CTRL;
/* Configure TX and RX direction */
SPI_RX_CTRL_REG = SPI_SPI_DEFAULT_RX_CTRL;
SPI_RX_FIFO_CTRL_REG = SPI_SPI_DEFAULT_RX_FIFO_CTRL;
/* Configure TX and RX direction */
SPI_TX_CTRL_REG = SPI_SPI_DEFAULT_TX_CTRL;
SPI_TX_FIFO_CTRL_REG = SPI_SPI_DEFAULT_TX_FIFO_CTRL;
/* Configure interrupt with SPI handler but do not enable it */
#if(SPI_SCB_IRQ_INTERNAL)
CyIntDisable (SPI_ISR_NUMBER);
CyIntSetPriority(SPI_ISR_NUMBER, SPI_ISR_PRIORITY);
(void) CyIntSetVector(SPI_ISR_NUMBER, &SPI_SPI_UART_ISR);
#endif /* (SPI_SCB_IRQ_INTERNAL) */
/* Configure interrupt sources */
SPI_INTR_I2C_EC_MASK_REG = SPI_SPI_DEFAULT_INTR_I2C_EC_MASK;
SPI_INTR_SPI_EC_MASK_REG = SPI_SPI_DEFAULT_INTR_SPI_EC_MASK;
SPI_INTR_SLAVE_MASK_REG = SPI_SPI_DEFAULT_INTR_SLAVE_MASK;
SPI_INTR_MASTER_MASK_REG = SPI_SPI_DEFAULT_INTR_MASTER_MASK;
SPI_INTR_RX_MASK_REG = SPI_SPI_DEFAULT_INTR_RX_MASK;
SPI_INTR_TX_MASK_REG = SPI_SPI_DEFAULT_INTR_TX_MASK;
/* Set active SS0 for master */
#if (SPI_SPI_MASTER_CONST)
SPI_SpiSetActiveSlaveSelect(SPI_SPI_SLAVE_SELECT0);
#endif /* (SPI_SPI_MASTER_CONST) */
#if(SPI_INTERNAL_RX_SW_BUFFER_CONST)
SPI_rxBufferHead = 0u;
SPI_rxBufferTail = 0u;
SPI_rxBufferOverflow = 0u;
#endif /* (SPI_INTERNAL_RX_SW_BUFFER_CONST) */
#if(SPI_INTERNAL_TX_SW_BUFFER_CONST)
SPI_txBufferHead = 0u;
SPI_txBufferTail = 0u;
#endif /* (SPI_INTERNAL_TX_SW_BUFFER_CONST) */
}
CY_CFG_SECTION
static void ClockSetup(void)
{
/* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */
CY_SET_REG32((void CYXDATA *)(CYREG_CPUSS_FLASH_CTL), (0x0011u));
/* Update IMO to new clock speed. */
CySysClkWriteImoFreq(24u);
/* Setup phase aligned clocks */
/* CYDEV_CLK_SELECT Starting address: CYDEV_CLK_SELECT */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT), 0x00000004u);
(void)CyIntSetVector(4u, &CySysWdtIsr);
CyIntEnable(4u);
/* Set Flash Cycles based on newly configured 12.00MHz HFCLK. */
CY_SET_REG32((void CYXDATA *)(CYREG_CPUSS_FLASH_CTL), (0x0000u));
}
/*******************************************************************************
* Function Name: TPS_ADC_SAR_Init
********************************************************************************
*
* Summary:
* Initialize component's parameters to the parameters set by user in the
* customizer of the component placed onto schematic. Usually called in
* TPS_ADC_SAR_Start().
*
* Parameters:
* None.
*
* Return:
* None.
*
* Global variables:
* The TPS_ADC_SAR_offset variable is initialized to 0.
*
*******************************************************************************/
void TPS_ADC_SAR_Init(void)
{
/* This is only valid if there is an internal clock */
#if(TPS_ADC_SAR_DEFAULT_INTERNAL_CLK)
TPS_ADC_SAR_theACLK_SetMode(CYCLK_DUTY);
#endif /* End TPS_ADC_SAR_DEFAULT_INTERNAL_CLK */
#if(TPS_ADC_SAR_IRQ_REMOVE == 0u)
/* Start and set interrupt vector */
CyIntSetPriority(TPS_ADC_SAR_INTC_NUMBER, TPS_ADC_SAR_INTC_PRIOR_NUMBER);
(void)CyIntSetVector(TPS_ADC_SAR_INTC_NUMBER, &TPS_ADC_SAR_ISR);
#endif /* End TPS_ADC_SAR_IRQ_REMOVE */
/* Enable IRQ mode*/
TPS_ADC_SAR_SAR_CSR1_REG |= TPS_ADC_SAR_SAR_IRQ_MASK_EN | TPS_ADC_SAR_SAR_IRQ_MODE_EDGE;
/*Set SAR ADC resolution ADC */
TPS_ADC_SAR_SetResolution(TPS_ADC_SAR_DEFAULT_RESOLUTION);
TPS_ADC_SAR_offset = 0;
}
/*******************************************************************************
* Function Name: InitializeSystem
********************************************************************************
* Summary:
* Start the components and initialize system
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
void InitializeSystem(void)
{
/* Enable global interrupt mask */
CyGlobalIntEnable;
/* Start BLE component and register the CustomEventHandler function. This
* function exposes the events from BLE component for application use */
CyBle_Start(CustomEventHandler);
/* Set Drive mode of output pins from HiZ to Strong */
RED_SetDriveMode(RED_DM_STRONG);
GREEN_SetDriveMode(GREEN_DM_STRONG);
BLUE_SetDriveMode(BLUE_DM_STRONG);
/* Start the Button ISR to allow wakeup from sleep */
isr_button_StartEx(MyISR);
/* Set the Watchdog Interrupt vector to the address of Interrupt routine
* WDT_INT_Handler. This routine counts the 3 seconds for LED ON state during
* connection. */
CyIntSetVector(WATCHDOG_INT_VEC_NUM, &WDT_INT_Handler);
}
//firmware initialization
void initialize(void)
{
//debug pin toggle
P4_0_Debug_Write(0xff);
//debug pin toggle
P4_0_Debug_Write(0x00);
//debug pin toggle
P4_0_Debug_Write(0xff);
//debug pin toggle
P4_0_Debug_Write(0x00);
//enable interrupts
CyGlobalIntEnable; /* Uncomment this line to enable global interrupts. */
//start watchdog
/* Setup WDT ISR */
CyIntSetVector(9, isr_wdt);
CyIntEnable(9);
/* Setup first WDT counter to generate interrupt on match 0x4FFF */
CySysWdtWriteMode(CY_SYS_WDT_COUNTER0,CY_SYS_WDT_MODE_INT);
CySysWdtWriteMatch(CY_SYS_WDT_COUNTER0,0x4FFF);
CySysWdtWriteClearOnMatch(CY_SYS_WDT_COUNTER0, 1u);
/* Enable WDT timers 0 and 1 cascade */
CySysWdtWriteCascade(CY_SYS_WDT_CASCADE_01);
/* Set WDT reset after counter 1 reach 0x0002 */
CySysWdtWriteMatch(CY_SYS_WDT_COUNTER1,0x0002);
CySysWdtWriteMode(CY_SYS_WDT_COUNTER1,CY_SYS_WDT_MODE_RESET);
CySysWdtWriteClearOnMatch(CY_SYS_WDT_COUNTER1, 1u);
/* Enable WDT counters 0 and 1 */
//#if(WATCHDOG_ENABLED)
CySysWdtEnable(CY_SYS_WDT_COUNTER0_MASK | CY_SYS_WDT_COUNTER1_MASK);
//#endif
//start components
sensors_Start();
motors_Start();
control_Start();
}
/*****************************************************************************
* Function Name: WatchdogTimer_Start()
******************************************************************************
* Summary:
* Initializes the watchdog timer.
*
* Parameters:
* wdtPeriodMs - The watchdog timer period to set, in milliseconds.
*
* Return:
* None
*
* Theory:
* Writes to the SRSS registers to start the low frequency clock and configure
* the watchdog timer. The watchdog timer is configured for 16-bit timing,
* and to generate an interrupt on match, plus an overflow on the third
* unserviced interrupt. The interrupt vector is pointed to a custom ISR in
* this file.
*
* Side Effects:
* None
*
* Note:
*
*****************************************************************************/
void WatchdogTimer_Start(uint32 wdtPeriodMs)
{
watchdogTimestamp = 0;
CyIntSetVector(WDT_INTERRUPT_NUM, &WatchdogTimer_Isr);
WatchdogTimer_Unlock();
/* Set the WDT period */
watchdogPeriodMs = wdtPeriodMs;
nextTicks = watchdogPeriodMs * WATCHDOG_TICKS_PER_MS;
UPDATE_WDT_MATCH(nextTicks);
#if (CY_PSOC4_4200)
/* For PSoC4A - Start ILO */
CY_SET_REG32(CYREG_CLK_ILO_CONFIG, CY_GET_REG32(CYREG_CLK_ILO_CONFIG) | CLK_ILO_CONFIG_ILO_ENABLE);
#elif (CY_PSOC4_4200BL)
/*
* For PSoC 4 BLE - Assume that WCO is started as part of CyBoot
* since WCO is selected as LFCLK source in the CYDWR.
*/
#endif /* #if (CY_PSOC4_4200) */
/* Enable WDT interrupt for the NVIC */
CyIntEnable(WDT_INTERRUPT_NUM);
/* Set WDT_CONFIG register */
CY_SET_REG32(CYREG_WDT_CONFIG, CY_GET_REG32(CYREG_WDT_CONFIG) | WDT_CONFIG_WDT_MODE0_INT);
/* Set WDT_CONTROL register */
CY_SET_REG32(CYREG_WDT_CONTROL, WDT_CONTROL_WDT_ENABLE0);
/* Wait for the WDT enable to complete */
while((CY_GET_REG32(CYREG_WDT_CONTROL) & WDT_CONTROL_WDT_ENABLED0) == 0);
WatchdogTimer_Lock();
}
/*******************************************************************************
* Function Name: EzI2C_Init
********************************************************************************
*
* Summary:
* Initializes or restores the component according to the Configure dialog
* settings. It is not necessary to call EZI2C_Init() because the EZI2C_Start()
* API calls this function, which is the preferred method to begin component
* operation.
*
* Parameters:
* None.
*
* Return:
* None.
*
* Global variables:
* EzI2C_initVar - It is used to indicate the initial configuration
* of this component. The variable is initialized to zero and set to 1
* the first time EzI2C_Start() is called. This allows component !
* initialization without re-initialization in all subsequent calls
* to the EzI2C_Start() routine.
*
* EzI2C_curStatus - Stores the current status of the component.
*
* EzI2C_curState- Stores the current state of an I2C state machine.
*
* EzI2C_rwOffsetS1 - The global variable which stores an offset for read
* and write operations, is set at each write sequence of the first slave
* address is reset if EzI2C_initVar is 0, by
* EzI2C_initVar function call.
*
* EzI2C_rwIndexS1 - The global variable which stores a pointer to the
* next value to be read or written for the first slave address is reset if
* EzI2C_initVar is 0, by EzI2C_initVar function call.
*
* EzI2C_wrProtectS1 - The global variable which stores an offset where data
* is read only for the first slave address is reset if
* EzI2C_initVar is 0, by EzI2C_initVar function call.
*
* EzI2C_rwOffsetS2 - The global variable, which stores an offset for read
* and write operations, is set at each write sequence of the second slave
* device is reset if EzI2C_initVar is 0, by EzI2C_initVar
* function call.
*
* EzI2C_rwIndexS2 - The global variable which stores a pointer to the
* next value to be read or written for the second slave address is reset if
* EzI2C_initVar is 0, by EzI2C_initVar function call.
*
* EzI2C_wrProtectS2 - The global variable which stores an offset where data
* is read only for the second slave address is reset if
* EzI2C_initVar is 0, by EzI2C_initVar function call.
*
* Reentrant:
* No.
*
*******************************************************************************/
void EzI2C_Init(void)
{
/* Configure fixed function block */
EzI2C_CFG_REG = EzI2C_DEFAULT_CFG;
EzI2C_XCFG_REG = EzI2C_DEFAULT_XCFG;
EzI2C_ADDR_REG = EzI2C_DEFAULT_ADDR;
EzI2C_CLKDIV1_REG = EzI2C_DEFAULT_CLKDIV1;
EzI2C_CLKDIV2_REG = EzI2C_DEFAULT_CLKDIV2;
#if (EzI2C_TWO_ADDRESSES == EzI2C_ADDRESSES)
/* Set address variables */
EzI2C_SetAddress1(EzI2C_DEFAULT_ADDR1);
EzI2C_SetAddress2(EzI2C_DEFAULT_ADDR2);
#endif /* #if (EzI2C_TWO_ADDRESSES == EzI2C_ADDRESSES) */
/* Configure interrupt */
CyIntDisable (EzI2C_ISR_NUMBER);
CyIntSetPriority (EzI2C_ISR_NUMBER, EzI2C_ISR_PRIORITY);
(void) CyIntSetVector(EzI2C_ISR_NUMBER, &EzI2C_ISR);
/* Reset state and status to default */
EzI2C_curState = EzI2C_SM_IDLE;
EzI2C_curStatus = 0u;
/* Reset all buffer 1 indexes (primary address) */
EzI2C_rwOffsetS1 = 0u;
EzI2C_rwIndexS1 = 0u;
EzI2C_wrProtectS1 = 0u;
#if (EzI2C_ADDRESSES == EzI2C_TWO_ADDRESSES)
/* Reset all buffer 2 indexes (secondary address) */
EzI2C_rwOffsetS2 = 0u;
EzI2C_rwIndexS2 = 0u;
EzI2C_wrProtectS2 = 0u;
#endif /* (EzI2C_ADDRESSES == EzI2C_TWO_ADDRESSES) */
}
/*******************************************************************************
* Function Name: main
********************************************************************************
*
* Summary:
* At the beginning of the main function, the GPIO interrupt is set up and
* enabled. After that, initial priority for the GPIO interrupt is changed from
* 1 to 3 (DEFAULT_PRIORITY). The custom interrupt (nested) is configured
* (sets up, sets priority) and enabled. In GPIOIsrHandler, the isr_GPIO
* pending interrupt clears, the green LED turns on, the nested software
* interrupt causes after approximately 1 second delay, green LED turns off.
*
* Parameters:
* None.
*
* Return:
* None.
*
*******************************************************************************/
int main()
{
/* Set initial state (off) for LED */
LED_Isr_Write(LIGHT_OFF);
LED_Nested_Write(LIGHT_OFF);
/* Sets up the GPIO interrupt and enables it */
isr_GPIO_StartEx(GPIOIsrHandler);
/* Changes initial priority for the GPIO interrupt */
isr_GPIO_SetPriority(DEFAULT_PRIORITY);
/* Sets up the nested interrupt, sets priority and enables it */
CyIntSetVector(NESTED_ISR,NestedIsrHandler);
CyIntSetPriority(NESTED_ISR,HIGHER_PRIORITY);
CyIntEnable(NESTED_ISR);
/* Enable global interrupts */
CyGlobalIntEnable;
for(;;)
{
}
}
/*******************************************************************************
* Function Name: Sensirion_I2C_Init
********************************************************************************
*
* Summary:
* Initializes I2C registers with initial values provided from customizer.
*
* Parameters:
* None
*
* Return:
* None
*
* Global variables:
* None
*
* Reentrant:
* No
*
*******************************************************************************/
void Sensirion_I2C_Init(void)
{
#if(Sensirion_I2C_FF_IMPLEMENTED)
Sensirion_I2C_CFG_REG = Sensirion_I2C_DEFAULT_CFG;
Sensirion_I2C_XCFG_REG = Sensirion_I2C_DEFAULT_XCFG;
#if(CY_PSOC5A)
Sensirion_I2C_CLKDIV_REG = LO8(Sensirion_I2C_DEFAULT_DIVIDE_FACTOR);
#else
Sensirion_I2C_CLKDIV1_REG = LO8(Sensirion_I2C_DEFAULT_DIVIDE_FACTOR);
Sensirion_I2C_CLKDIV2_REG = HI8(Sensirion_I2C_DEFAULT_DIVIDE_FACTOR);
#endif /* (CY_PSOC5A) */
#else
uint8 enableInterrupts;
Sensirion_I2C_CFG_REG = Sensirion_I2C_DEFAULT_CFG; /* control */
Sensirion_I2C_INT_MASK_REG = Sensirion_I2C_DEFAULT_INT_MASK; /* int_mask */
/* Enable interrupts from block */
enableInterrupts = CyEnterCriticalSection();
Sensirion_I2C_INT_ENABLE_REG |= Sensirion_I2C_INTR_ENABLE; /* aux_ctl */
CyExitCriticalSection(enableInterrupts);
#if(Sensirion_I2C_MODE_MASTER_ENABLED)
Sensirion_I2C_MCLK_PRD_REG = Sensirion_I2C_DEFAULT_MCLK_PRD;
Sensirion_I2C_MCLK_CMP_REG = Sensirion_I2C_DEFAULT_MCLK_CMP;
#endif /* (Sensirion_I2C_MODE_MASTER_ENABLED) */
#if(Sensirion_I2C_MODE_SLAVE_ENABLED)
Sensirion_I2C_PERIOD_REG = Sensirion_I2C_DEFAULT_PERIOD;
#endif /* (Sensirion_I2C_MODE_SLAVE_ENABLED) */
#endif /* (Sensirion_I2C_FF_IMPLEMENTED) */
#if(Sensirion_I2C_TIMEOUT_ENABLED)
Sensirion_I2C_TimeoutInit();
#endif /* (Sensirion_I2C_TIMEOUT_ENABLED) */
/* Disable Interrupt and set vector and priority */
CyIntDisable (Sensirion_I2C_ISR_NUMBER);
CyIntSetPriority(Sensirion_I2C_ISR_NUMBER, Sensirion_I2C_ISR_PRIORITY);
#if(Sensirion_I2C_INTERN_I2C_INTR_HANDLER)
(void) CyIntSetVector(Sensirion_I2C_ISR_NUMBER, &Sensirion_I2C_ISR);
#endif /* (Sensirion_I2C_INTERN_I2C_INTR_HANDLER) */
/* Put state machine in idle state */
Sensirion_I2C_state = Sensirion_I2C_SM_IDLE;
#if(Sensirion_I2C_MODE_SLAVE_ENABLED)
/* Reset status and buffers index */
Sensirion_I2C_SlaveClearReadBuf();
Sensirion_I2C_SlaveClearWriteBuf();
Sensirion_I2C_slStatus = 0u; /* Reset slave status */
/* Set default address */
Sensirion_I2C_SlaveSetAddress(Sensirion_I2C_DEFAULT_ADDR);
#endif /* (Sensirion_I2C_MODE_SLAVE_ENABLED) */
#if(Sensirion_I2C_MODE_MASTER_ENABLED)
/* Reset status and buffers index */
Sensirion_I2C_MasterClearReadBuf();
Sensirion_I2C_MasterClearWriteBuf();
(void) Sensirion_I2C_MasterClearStatus();
#endif /* (Sensirion_I2C_MODE_MASTER_ENABLED) */
}
/*******************************************************************************
* Function Name: I2C_Master_SaveConfig
********************************************************************************
*
* Summary:
* Wakeup on address match enabled: disables I2C Master(if was enabled before go
* to sleep), enables I2C backup regulator. Waits while on-going transaction be
* will completed and I2C will be ready go to sleep. All incoming transaction
* will be NACKed till power down will be asserted. The address match event
* wakes up the chip.
* Wakeup on address match disabled: saves I2C configuration and non-retention
* register values.
*
* Parameters:
* None
*
* Return:
* None
*
* Global Variables:
* I2C_Master_backup - used to save component configuration and
* none-retention registers before enter sleep mode.
*
* Reentrant:
* No
*
*******************************************************************************/
void I2C_Master_SaveConfig(void)
{
#if(I2C_Master_FF_IMPLEMENTED)
#if(I2C_Master_WAKEUP_ENABLED)
uint8 enableInterrupts;
#endif /* (I2C_Master_WAKEUP_ENABLED) */
/* Store regiters in either Sleep mode */
I2C_Master_backup.cfg = I2C_Master_CFG_REG;
I2C_Master_backup.xcfg = I2C_Master_XCFG_REG;
#if(I2C_Master_MODE_SLAVE_ENABLED)
I2C_Master_backup.addr = I2C_Master_ADDR_REG;
#endif /* (I2C_Master_MODE_SLAVE_ENABLED) */
#if(CY_PSOC5A)
I2C_Master_backup.clkDiv = I2C_Master_CLKDIV_REG;
#else
I2C_Master_backup.clkDiv1 = I2C_Master_CLKDIV1_REG;
I2C_Master_backup.clkDiv2 = I2C_Master_CLKDIV2_REG;
#endif /* (CY_PSOC5A) */
#if(I2C_Master_WAKEUP_ENABLED)
/* Need to disable Master */
I2C_Master_CFG_REG &= ((uint8) ~I2C_Master_ENABLE_MASTER);
/* Enable the I2C regulator backup */
enableInterrupts = CyEnterCriticalSection();
I2C_Master_PWRSYS_CR1_REG |= I2C_Master_PWRSYS_CR1_I2C_REG_BACKUP;
CyExitCriticalSection(enableInterrupts);
/* 1) Set force NACK to ignore I2C transactions
2) Wait while I2C will be ready go to Sleep
3) These bits are cleared on wake up */
I2C_Master_XCFG_REG |= I2C_Master_XCFG_FORCE_NACK;
while(0u == (I2C_Master_XCFG_REG & I2C_Master_XCFG_RDY_TO_SLEEP))
{
; /* Wait when block is ready to Sleep */
}
/* Setup wakeup interrupt */
I2C_Master_DisableInt();
(void) CyIntSetVector(I2C_Master_ISR_NUMBER, &I2C_Master_WAKEUP_ISR);
I2C_Master_wakeupSource = 0u;
I2C_Master_EnableInt();
#endif /* (I2C_Master_WAKEUP_ENABLED) */
#else
/* Store only address match bit */
I2C_Master_backup.control = (I2C_Master_CFG_REG & I2C_Master_CTRL_ANY_ADDRESS_MASK);
#if(CY_UDB_V0)
/* Store interrupt mask bits */
I2C_Master_backup.intMask = I2C_Master_INT_MASK_REG;
#if(I2C_Master_MODE & I2C_Master_MODE_SLAVE)
I2C_Master_backup.addr = I2C_Master_ADDR_REG;
#endif /* (I2C_Master_MODE & I2C_Master_MODE_SLAVE) */
#endif /* (CY_UDB_V0) */
#endif /* (I2C_Master_FF_IMPLEMENTED) */
#if(I2C_Master_TIMEOUT_ENABLED)
I2C_Master_TimeoutSaveConfig(); /* Save Timeout config */
#endif /* (I2C_Master_TIMEOUT_ENABLED) */
}
/*******************************************************************************
* Function Name: I2C_Master_RestoreConfig
********************************************************************************
*
* Summary:
* Wakeup on address match enabled: enables I2C Master (if was enabled before go
* to sleep), disables I2C backup regulator.
* Wakeup on address match disabled: Restores I2C configuration and
* non-retention register values.
*
* Parameters:
* None
*
* Return:
* None
*
* Global Variables:
* I2C_Master_backup - used to save component configuration and
* none-retention registers before exit sleep mode.
*
*******************************************************************************/
void I2C_Master_RestoreConfig(void)
{
#if(I2C_Master_FF_IMPLEMENTED)
uint8 enableInterrupts;
if(I2C_Master_CHECK_PWRSYS_I2C_BACKUP) /* Enabled if was in Sleep */
{
/* Disable back-up regulator */
enableInterrupts = CyEnterCriticalSection();
I2C_Master_PWRSYS_CR1_REG &= ((uint8) ~I2C_Master_PWRSYS_CR1_I2C_REG_BACKUP);
CyExitCriticalSection(enableInterrupts);
/* Re-enable Master */
I2C_Master_CFG_REG = I2C_Master_backup.cfg;
}
else /* The I2C_REG_BACKUP was cleaned by PM API: it means Hibernate or wake-up not set */
{
#if(I2C_Master_WAKEUP_ENABLED)
/* Disable power to I2C block before register restore */
enableInterrupts = CyEnterCriticalSection();
I2C_Master_ACT_PWRMGR_REG &= ((uint8) ~I2C_Master_ACT_PWR_EN);
I2C_Master_STBY_PWRMGR_REG &= ((uint8) ~I2C_Master_STBY_PWR_EN);
CyExitCriticalSection(enableInterrupts);
/* Enable component after restore complete */
I2C_Master_backup.enableState = I2C_Master_ENABLE;
#endif /* (I2C_Master_WAKEUP_ENABLED) */
/* Restore component registers: Hibernate disable power */
I2C_Master_XCFG_REG = I2C_Master_backup.xcfg;
I2C_Master_CFG_REG = I2C_Master_backup.cfg;
#if(I2C_Master_MODE_SLAVE_ENABLED)
I2C_Master_ADDR_REG = I2C_Master_backup.addr;
#endif /* (I2C_Master_MODE_SLAVE_ENABLED) */
#if(CY_PSOC5A)
I2C_Master_CLKDIV_REG = I2C_Master_backup.clkDiv;
#else
I2C_Master_CLKDIV1_REG = I2C_Master_backup.clkDiv1;
I2C_Master_CLKDIV2_REG = I2C_Master_backup.clkDiv2;
#endif /* (CY_PSOC5A) */
}
#if(I2C_Master_WAKEUP_ENABLED)
I2C_Master_DisableInt();
(void) CyIntSetVector(I2C_Master_ISR_NUMBER, &I2C_Master_ISR);
if(0u != I2C_Master_wakeupSource)
{
I2C_Master_SetPendingInt(); /* Generate interrupt to process incomming transcation */
}
I2C_Master_EnableInt();
#endif /* (I2C_Master_WAKEUP_ENABLED) */
#else
#if(CY_UDB_V0)
uint8 enableInterrupts;
I2C_Master_INT_MASK_REG |= I2C_Master_backup.intMask;
enableInterrupts = CyEnterCriticalSection();
I2C_Master_INT_ENABLE_REG |= I2C_Master_INT_ENABLE_MASK;
CyExitCriticalSection(enableInterrupts);
#if(I2C_Master_MODE_MASTER_ENABLED)
/* Restore Master Clock generator */
I2C_Master_MCLK_PRD_REG = I2C_Master_DEFAULT_MCLK_PRD;
I2C_Master_MCLK_CMP_REG = I2C_Master_DEFAULT_MCLK_CMP;
#endif /* (I2C_Master_MODE_MASTER_ENABLED) */
#if(I2C_Master_MODE_SLAVE_ENABLED)
I2C_Master_ADDR_REG = I2C_Master_backup.addr;
/* Restore slave bit counter period */
I2C_Master_PERIOD_REG = I2C_Master_DEFAULT_PERIOD;
#endif /* (I2C_Master_MODE_SLAVE_ENABLED) */
#endif /* (CY_UDB_V0) */
I2C_Master_CFG_REG = I2C_Master_backup.control;
#endif /* (I2C_Master_FF_IMPLEMENTED) */
#if(I2C_Master_TIMEOUT_ENABLED)
I2C_Master_TimeoutRestoreConfig();
#endif /* (I2C_Master_TIMEOUT_ENABLED) */
}
/*******************************************************************************
* Function Name: ADC_SAR_Seq_0_Init
********************************************************************************
*
* Summary:
* Initialize component's parameters to the parameters set by user in the
* customizer of the component placed onto schematic. Usually called in
* ADC_SAR_Seq_0_Start().
*
* Parameters:
* None.
*
* Return:
* None.
*
* Global variables:
* The ADC_SAR_Seq_0_offset variable is initialized.
*
*******************************************************************************/
void ADC_SAR_Seq_0_Init(void)
{
uint32 chNum;
uint32 tmpRegVal;
int32 counts;
#if(ADC_SAR_Seq_0_TOTAL_CHANNELS_NUM > 1u)
static const uint8 CYCODE ADC_SAR_Seq_0_InputsPlacement[] =
{
(uint8)(ADC_SAR_Seq_0_cy_psoc4_sarmux_8__CH_0_PORT << 4u) |
(uint8)ADC_SAR_Seq_0_cy_psoc4_sarmux_8__CH_0_PIN
,(uint8)(ADC_SAR_Seq_0_cy_psoc4_sarmux_8__CH_1_PORT << 4u) |
(uint8)ADC_SAR_Seq_0_cy_psoc4_sarmux_8__CH_1_PIN
#if(ADC_SAR_Seq_0_TOTAL_CHANNELS_NUM > 2u)
,(uint8)(ADC_SAR_Seq_0_cy_psoc4_sarmux_8__CH_2_PORT << 4u) |
(uint8)ADC_SAR_Seq_0_cy_psoc4_sarmux_8__CH_2_PIN
#endif /* End ADC_SAR_Seq_0_TOTAL_CHANNELS_NUM > 2u */
#if(ADC_SAR_Seq_0_TOTAL_CHANNELS_NUM > 3u)
,(uint8)(ADC_SAR_Seq_0_cy_psoc4_sarmux_8__CH_3_PORT << 4u) |
(uint8)ADC_SAR_Seq_0_cy_psoc4_sarmux_8__CH_3_PIN
#endif /* End ADC_SAR_Seq_0_TOTAL_CHANNELS_NUM > 3u */
#if(ADC_SAR_Seq_0_TOTAL_CHANNELS_NUM > 4u)
,(uint8)(ADC_SAR_Seq_0_cy_psoc4_sarmux_8__CH_4_PORT << 4u) |
(uint8)ADC_SAR_Seq_0_cy_psoc4_sarmux_8__CH_4_PIN
#endif /* End ADC_SAR_Seq_0_TOTAL_CHANNELS_NUM > 4u */
#if(ADC_SAR_Seq_0_TOTAL_CHANNELS_NUM > 5u)
,(uint8)(ADC_SAR_Seq_0_cy_psoc4_sarmux_8__CH_5_PORT << 4u) |
(uint8)ADC_SAR_Seq_0_cy_psoc4_sarmux_8__CH_5_PIN
#endif /* End ADC_SAR_Seq_0_TOTAL_CHANNELS_NUM > 5u */
#if(ADC_SAR_Seq_0_TOTAL_CHANNELS_NUM > 6u)
,(uint8)(ADC_SAR_Seq_0_cy_psoc4_sarmux_8__CH_6_PORT << 4u) |
(uint8)ADC_SAR_Seq_0_cy_psoc4_sarmux_8__CH_6_PIN
#endif /* End ADC_SAR_Seq_0_TOTAL_CHANNELS_NUM > 6u */
#if(ADC_SAR_Seq_0_TOTAL_CHANNELS_NUM > 7u)
,(uint8)(ADC_SAR_Seq_0_cy_psoc4_sarmux_8__CH_7_PORT << 4u) |
(uint8)ADC_SAR_Seq_0_cy_psoc4_sarmux_8__CH_7_PIN
#endif /* End ADC_SAR_Seq_0_TOTAL_CHANNELS_NUM > 7u */
#if(ADC_SAR_Seq_0_TOTAL_CHANNELS_NUM > 8u)
,(uint8)(ADC_SAR_Seq_0_cy_psoc4_sarmux_8__CH_8_PORT << 4u) |
(uint8)ADC_SAR_Seq_0_cy_psoc4_sarmux_8__CH_8_PIN
#endif /* End ADC_SAR_Seq_0_TOTAL_CHANNELS_NUM > 8u */
};
#endif /* End ADC_SAR_Seq_0_TOTAL_CHANNELS_NUM > 1u */
#if(ADC_SAR_Seq_0_IRQ_REMOVE == 0u)
/* Start and set interrupt vector */
CyIntSetPriority(ADC_SAR_Seq_0_INTC_NUMBER, ADC_SAR_Seq_0_INTC_PRIOR_NUMBER);
(void)CyIntSetVector(ADC_SAR_Seq_0_INTC_NUMBER, &ADC_SAR_Seq_0_ISR);
#endif /* End ADC_SAR_Seq_0_IRQ_REMOVE */
/* Init SAR and MUX registers */
ADC_SAR_Seq_0_SAR_CHAN_EN_REG = ADC_SAR_Seq_0_DEFAULT_EN_CHANNELS;
ADC_SAR_Seq_0_SAR_CTRL_REG = ADC_SAR_Seq_0_DEFAULT_CTRL_REG_CFG;
ADC_SAR_Seq_0_SAR_SAMPLE_CTRL_REG = ADC_SAR_Seq_0_DEFAULT_SAMPLE_CTRL_REG_CFG;
ADC_SAR_Seq_0_SAR_RANGE_THRES_REG = ADC_SAR_Seq_0_DEFAULT_RANGE_THRES_REG_CFG;
ADC_SAR_Seq_0_SAR_RANGE_COND_REG = ADC_SAR_Seq_0_COMPARE_MODE;
ADC_SAR_Seq_0_SAR_SAMPLE_TIME01_REG = ADC_SAR_Seq_0_DEFAULT_SAMPLE_TIME01_REG_CFG;
ADC_SAR_Seq_0_SAR_SAMPLE_TIME23_REG = ADC_SAR_Seq_0_DEFAULT_SAMPLE_TIME23_REG_CFG;
/* Connect Vm to VSSA when even one channel is single-ended or multiple channels configured */
#if(ADC_SAR_Seq_0_DEFAULT_MUX_SWITCH0 != 0u)
ADC_SAR_Seq_0_MUX_SWITCH0_REG |= ADC_SAR_Seq_0_DEFAULT_MUX_SWITCH0;
/* Set MUX_HW_CTRL_VSSA in MUX_SWITCH_HW_CTRL when multiple channels enabled */
#if(ADC_SAR_Seq_0_TOTAL_CHANNELS_NUM > 1u)
ADC_SAR_Seq_0_MUX_SWITCH_HW_CTRL_REG |= ADC_SAR_Seq_0_DEFAULT_MUX_SWITCH0;
#endif /* ADC_SAR_Seq_0_TOTAL_CHANNELS_NUM > 1u */
#endif /*ADC_SAR_Seq_0_CHANNELS_MODE !=0 */
ADC_SAR_Seq_0_SAR_SATURATE_INTR_MASK_REG = 0u;
ADC_SAR_Seq_0_SAR_RANGE_INTR_MASK_REG = 0u;
ADC_SAR_Seq_0_SAR_INTR_MASK_REG = ADC_SAR_Seq_0_SAR_INTR_MASK;
ADC_SAR_Seq_0_ANA_TRIM_REG = ADC_SAR_Seq_0_TRIM_COEF;
/* Read and modify default configuration based on characterization */
tmpRegVal = ADC_SAR_Seq_0_SAR_DFT_CTRL_REG;
#if(ADC_SAR_Seq_0_NOMINAL_CLOCK_FREQ > (ADC_SAR_Seq_0_MAX_FREQUENCY / 2))
tmpRegVal &= (uint32)~ADC_SAR_Seq_0_DCEN;
tmpRegVal |= ADC_SAR_Seq_0_SEL_CSEL_DFT_CHAR;
#else /* clock speed < 9 Mhz */
tmpRegVal |= ADC_SAR_Seq_0_DLY_INC;
#endif /* clock speed > 9 Mhz */
ADC_SAR_Seq_0_SAR_DFT_CTRL_REG = tmpRegVal;
#if(ADC_SAR_Seq_0_MAX_RESOLUTION != ADC_SAR_Seq_0_RESOLUTION_12)
ADC_SAR_Seq_0_WOUNDING_REG = ADC_SAR_Seq_0_ALT_WOUNDING;
#endif /* ADC_SAR_Seq_0_MAX_RESOLUTION != ADC_SAR_Seq_0_RESOLUTION_12 */
for(chNum = 0u; chNum < ADC_SAR_Seq_0_TOTAL_CHANNELS_NUM; chNum++)
{
tmpRegVal = (ADC_SAR_Seq_0_channelsConfig[chNum] & ADC_SAR_Seq_0_CHANNEL_CONFIG_MASK);
#if(ADC_SAR_Seq_0_TOTAL_CHANNELS_NUM > 1u)
tmpRegVal |= ADC_SAR_Seq_0_InputsPlacement[chNum];
#endif /* End ADC_SAR_Seq_0_TOTAL_CHANNELS_NUM > 1u */
/* When the part is wounded to 10-bit then the SUB_RESOLUTION bit
* will be ignored and the RESOLUTION bit selects between 10-bit
* (0) and 8-bit (1) resolution.
*/
#if((ADC_SAR_Seq_0_MAX_RESOLUTION != ADC_SAR_Seq_0_RESOLUTION_12) && \
(ADC_SAR_Seq_0_ALT_WOUNDING == ADC_SAR_Seq_0_WOUNDING_10BIT))
tmpRegVal &= (uint32)(~ADC_SAR_Seq_0_ALT_RESOLUTION_ON);
#endif /* ADC_SAR_Seq_0_MAX_RESOLUTION != ADC_SAR_Seq_0_RESOLUTION_12 */
#if(ADC_SAR_Seq_0_INJ_CHANNEL_ENABLED)
if(chNum < ADC_SAR_Seq_0_SEQUENCED_CHANNELS_NUM)
#endif /* ADC_SAR_Seq_0_INJ_CHANNEL_ENABLED */
{
CY_SET_REG32((reg32 *)(ADC_SAR_Seq_0_SAR_CHAN_CONFIG_IND + (uint32)(chNum << 2)), tmpRegVal);
if((ADC_SAR_Seq_0_channelsConfig[chNum] & ADC_SAR_Seq_0_IS_SATURATE_EN_MASK) != 0u)
{
ADC_SAR_Seq_0_SAR_SATURATE_INTR_MASK_REG |= (uint16)((uint16)1 << chNum);
}
if((ADC_SAR_Seq_0_channelsConfig[chNum] & ADC_SAR_Seq_0_IS_RANGE_CTRL_EN_MASK) != 0u)
{
ADC_SAR_Seq_0_SAR_RANGE_INTR_MASK_REG |= (uint16)((uint16)1 << chNum);
}
}
#if(ADC_SAR_Seq_0_INJ_CHANNEL_ENABLED)
else
{
CY_SET_REG32(ADC_SAR_Seq_0_SAR_INJ_CHAN_CONFIG_PTR, tmpRegVal | ADC_SAR_Seq_0_INJ_TAILGATING);
if((ADC_SAR_Seq_0_channelsConfig[chNum] & ADC_SAR_Seq_0_IS_SATURATE_EN_MASK) != 0u)
{
ADC_SAR_Seq_0_SAR_INTR_MASK_REG |= ADC_SAR_Seq_0_INJ_SATURATE_MASK;
}
if((ADC_SAR_Seq_0_channelsConfig[chNum] & ADC_SAR_Seq_0_IS_RANGE_CTRL_EN_MASK) != 0u)
{
ADC_SAR_Seq_0_SAR_INTR_MASK_REG |= ADC_SAR_Seq_0_INJ_RANGE_MASK;
}
}
#endif /* ADC_SAR_Seq_0_INJ_CHANNEL_ENABLED */
if((ADC_SAR_Seq_0_channelsConfig[chNum] & ADC_SAR_Seq_0_ALT_RESOLUTION_ON) != 0u)
{
counts = (int32)ADC_SAR_Seq_0_DEFAULT_MAX_WRK_ALT;
}
else
{
counts = (int32)ADC_SAR_Seq_0_SAR_WRK_MAX_12BIT;
}
if((ADC_SAR_Seq_0_channelsConfig[chNum] & ADC_SAR_Seq_0_DIFFERENTIAL_EN) == 0u)
{
#if((ADC_SAR_Seq_0_DEFAULT_SE_RESULT_FORMAT_SEL == ADC_SAR_Seq_0__FSIGNED) && \
(ADC_SAR_Seq_0_DEFAULT_NEG_INPUT_SEL == ADC_SAR_Seq_0__VREF))
/* Set offset to the minus half scale to convert results to unsigned format */
ADC_SAR_Seq_0_offset[chNum] = (int16)(counts / -2);
#else
ADC_SAR_Seq_0_offset[chNum] = 0;
#endif /* end DEFAULT_SE_RESULT_FORMAT_SEL == ADC_SAR_Seq_0__FSIGNED */
}
else /* Differential channel */
{
#if(ADC_SAR_Seq_0_DEFAULT_DIFF_RESULT_FORMAT_SEL == ADC_SAR_Seq_0__FUNSIGNED)
/* Set offset to the half scale to convert results to signed format */
ADC_SAR_Seq_0_offset[chNum] = (int16)(counts / 2);
#else
ADC_SAR_Seq_0_offset[chNum] = 0;
#endif /* end ADC_SAR_Seq_0_DEFAULT_DIFF_RESULT_FORMAT_SEL == ADC_SAR_Seq_0__FUNSIGNED */
}
/* Calculate gain in counts per 10 volts with rounding */
ADC_SAR_Seq_0_countsPer10Volt[chNum] = (int16)(((counts * ADC_SAR_Seq_0_10MV_COUNTS) +
ADC_SAR_Seq_0_DEFAULT_VREF_MV_VALUE) / (ADC_SAR_Seq_0_DEFAULT_VREF_MV_VALUE * 2));
}
}
/*******************************************************************************
* Function Name: `$INSTANCE_NAME`_Init
********************************************************************************
*
* Summary:
* Initialize component's parameters to the parameters set by user in the
* customizer of the component placed onto schematic. Usually called in
* `$INSTANCE_NAME`_Start().
*
* Parameters:
* None.
*
* Return:
* None.
*
* Global variables:
* The `$INSTANCE_NAME`_offset variable is initialized.
*
*******************************************************************************/
void `$INSTANCE_NAME`_Init(void)
{
uint32 chNum;
uint32 tmpRegVal;
int32 counts;
#if(`$INSTANCE_NAME`_TOTAL_CHANNELS_NUM > 1u)
static const uint8 CYCODE `$INSTANCE_NAME`_InputsPlacement[] =
{
(uint8)(`$INSTANCE_NAME`_cy_psoc4_sarmux_8__CH_0_PORT << 4u) |
(uint8)`$INSTANCE_NAME`_cy_psoc4_sarmux_8__CH_0_PIN
,(uint8)(`$INSTANCE_NAME`_cy_psoc4_sarmux_8__CH_1_PORT << 4u) |
(uint8)`$INSTANCE_NAME`_cy_psoc4_sarmux_8__CH_1_PIN
#if(`$INSTANCE_NAME`_TOTAL_CHANNELS_NUM > 2u)
,(uint8)(`$INSTANCE_NAME`_cy_psoc4_sarmux_8__CH_2_PORT << 4u) |
(uint8)`$INSTANCE_NAME`_cy_psoc4_sarmux_8__CH_2_PIN
#endif /* End `$INSTANCE_NAME`_TOTAL_CHANNELS_NUM > 2u */
#if(`$INSTANCE_NAME`_TOTAL_CHANNELS_NUM > 3u)
,(uint8)(`$INSTANCE_NAME`_cy_psoc4_sarmux_8__CH_3_PORT << 4u) |
(uint8)`$INSTANCE_NAME`_cy_psoc4_sarmux_8__CH_3_PIN
#endif /* End `$INSTANCE_NAME`_TOTAL_CHANNELS_NUM > 3u */
#if(`$INSTANCE_NAME`_TOTAL_CHANNELS_NUM > 4u)
,(uint8)(`$INSTANCE_NAME`_cy_psoc4_sarmux_8__CH_4_PORT << 4u) |
(uint8)`$INSTANCE_NAME`_cy_psoc4_sarmux_8__CH_4_PIN
#endif /* End `$INSTANCE_NAME`_TOTAL_CHANNELS_NUM > 4u */
#if(`$INSTANCE_NAME`_TOTAL_CHANNELS_NUM > 5u)
,(uint8)(`$INSTANCE_NAME`_cy_psoc4_sarmux_8__CH_5_PORT << 4u) |
(uint8)`$INSTANCE_NAME`_cy_psoc4_sarmux_8__CH_5_PIN
#endif /* End `$INSTANCE_NAME`_TOTAL_CHANNELS_NUM > 5u */
#if(`$INSTANCE_NAME`_TOTAL_CHANNELS_NUM > 6u)
,(uint8)(`$INSTANCE_NAME`_cy_psoc4_sarmux_8__CH_6_PORT << 4u) |
(uint8)`$INSTANCE_NAME`_cy_psoc4_sarmux_8__CH_6_PIN
#endif /* End `$INSTANCE_NAME`_TOTAL_CHANNELS_NUM > 6u */
#if(`$INSTANCE_NAME`_TOTAL_CHANNELS_NUM > 7u)
,(uint8)(`$INSTANCE_NAME`_cy_psoc4_sarmux_8__CH_7_PORT << 4u) |
(uint8)`$INSTANCE_NAME`_cy_psoc4_sarmux_8__CH_7_PIN
#endif /* End `$INSTANCE_NAME`_TOTAL_CHANNELS_NUM > 7u */
#if(`$INSTANCE_NAME`_TOTAL_CHANNELS_NUM > 8u)
,(uint8)(`$INSTANCE_NAME`_cy_psoc4_sarmux_8__CH_8_PORT << 4u) |
(uint8)`$INSTANCE_NAME`_cy_psoc4_sarmux_8__CH_8_PIN
#endif /* End `$INSTANCE_NAME`_TOTAL_CHANNELS_NUM > 8u */
};
#endif /* End `$INSTANCE_NAME`_TOTAL_CHANNELS_NUM > 1u */
#if(`$INSTANCE_NAME`_IRQ_REMOVE == 0u)
/* Start and set interrupt vector */
CyIntSetPriority(`$INSTANCE_NAME`_INTC_NUMBER, `$INSTANCE_NAME`_INTC_PRIOR_NUMBER);
(void)CyIntSetVector(`$INSTANCE_NAME`_INTC_NUMBER, &`$INSTANCE_NAME`_ISR);
#endif /* End `$INSTANCE_NAME`_IRQ_REMOVE */
/* Init SAR and MUX registers */
`$INSTANCE_NAME`_SAR_CHAN_EN_REG = `$INSTANCE_NAME`_DEFAULT_EN_CHANNELS;
`$INSTANCE_NAME`_SAR_CTRL_REG = `$INSTANCE_NAME`_DEFAULT_CTRL_REG_CFG;
`$INSTANCE_NAME`_SAR_SAMPLE_CTRL_REG = `$INSTANCE_NAME`_DEFAULT_SAMPLE_CTRL_REG_CFG;
`$INSTANCE_NAME`_SAR_RANGE_THRES_REG = `$INSTANCE_NAME`_DEFAULT_RANGE_THRES_REG_CFG;
`$INSTANCE_NAME`_SAR_RANGE_COND_REG = `$INSTANCE_NAME`_COMPARE_MODE;
`$INSTANCE_NAME`_SAR_SAMPLE_TIME01_REG = `$INSTANCE_NAME`_DEFAULT_SAMPLE_TIME01_REG_CFG;
`$INSTANCE_NAME`_SAR_SAMPLE_TIME23_REG = `$INSTANCE_NAME`_DEFAULT_SAMPLE_TIME23_REG_CFG;
/* Connect Vm to VSSA when even one channel is single-ended or multiple channels configured */
#if(`$INSTANCE_NAME`_DEFAULT_MUX_SWITCH0 != 0u)
`$INSTANCE_NAME`_MUX_SWITCH0_REG |= `$INSTANCE_NAME`_DEFAULT_MUX_SWITCH0;
/* Set MUX_HW_CTRL_VSSA in MUX_SWITCH_HW_CTRL when multiple channels enabled */
#if(`$INSTANCE_NAME`_TOTAL_CHANNELS_NUM > 1u)
`$INSTANCE_NAME`_MUX_SWITCH_HW_CTRL_REG |= `$INSTANCE_NAME`_DEFAULT_MUX_SWITCH0;
#endif
#endif /*`$INSTANCE_NAME`_CHANNELS_MODE !=0 */
`$INSTANCE_NAME`_SAR_SATURATE_INTR_MASK_REG = 0u;
`$INSTANCE_NAME`_SAR_RANGE_INTR_MASK_REG = 0u;
`$INSTANCE_NAME`_SAR_INTR_MASK_REG = `$INSTANCE_NAME`_SAR_INTR_MASK;
#if(`$INSTANCE_NAME`_MAX_RESOLUTION != `$INSTANCE_NAME`_RESOLUTION_12)
`$INSTANCE_NAME`_WOUNDING_REG = `$INSTANCE_NAME`_ALT_WOUNDING;
#endif /* `$INSTANCE_NAME`_MAX_RESOLUTION != `$INSTANCE_NAME`_RESOLUTION_12 */
for(chNum = 0u; chNum < `$INSTANCE_NAME`_TOTAL_CHANNELS_NUM; chNum++)
{
tmpRegVal = (`$INSTANCE_NAME`_channelsConfig[chNum] & `$INSTANCE_NAME`_CHANNEL_CONFIG_MASK);
#if(`$INSTANCE_NAME`_TOTAL_CHANNELS_NUM > 1u)
tmpRegVal |= `$INSTANCE_NAME`_InputsPlacement[chNum];
#endif /* End `$INSTANCE_NAME`_TOTAL_CHANNELS_NUM > 1u */
/* When the part is wounded to 10-bit then the SUB_RESOLUTION bit will be ignored and the
* RESOLUTION bit selects between 10-bit (0) and 8-bit (1) resolution.
*/
#if((`$INSTANCE_NAME`_MAX_RESOLUTION != `$INSTANCE_NAME`_RESOLUTION_12) && \
(`$INSTANCE_NAME`_ALT_WOUNDING == `$INSTANCE_NAME`_WOUNDING_10BIT))
tmpRegVal &= (uint32)(~`$INSTANCE_NAME`_ALT_RESOLUTION_ON);
#endif /* `$INSTANCE_NAME`_MAX_RESOLUTION != `$INSTANCE_NAME`_RESOLUTION_12 */
#if(`$INSTANCE_NAME`_INJ_CHANNEL_ENABLED)
if(chNum < `$INSTANCE_NAME`_SEQUENCED_CHANNELS_NUM)
#endif /* `$INSTANCE_NAME`_INJ_CHANNEL_ENABLED */
{
CY_SET_REG32((reg32 *)(`$INSTANCE_NAME`_SAR_CHAN_CONFIG_IND + (uint32)(chNum << 2)), tmpRegVal);
if((`$INSTANCE_NAME`_channelsConfig[chNum] & `$INSTANCE_NAME`_IS_SATURATE_EN_MASK) != 0u)
{
`$INSTANCE_NAME`_SAR_SATURATE_INTR_MASK_REG |= (uint16)((uint16)1 << chNum);
}
if((`$INSTANCE_NAME`_channelsConfig[chNum] & `$INSTANCE_NAME`_IS_RANGE_CTRL_EN_MASK) != 0u)
{
`$INSTANCE_NAME`_SAR_RANGE_INTR_MASK_REG |= (uint16)((uint16)1 << chNum);
}
}
#if(`$INSTANCE_NAME`_INJ_CHANNEL_ENABLED)
else
{
CY_SET_REG32(`$INSTANCE_NAME`_SAR_INJ_CHAN_CONFIG_PTR, tmpRegVal | `$INSTANCE_NAME`_INJ_TAILGATING);
if((`$INSTANCE_NAME`_channelsConfig[chNum] & `$INSTANCE_NAME`_IS_SATURATE_EN_MASK) != 0u)
{
`$INSTANCE_NAME`_SAR_INTR_MASK_REG |= `$INSTANCE_NAME`_INJ_SATURATE_MASK;
}
if((`$INSTANCE_NAME`_channelsConfig[chNum] & `$INSTANCE_NAME`_IS_RANGE_CTRL_EN_MASK) != 0u)
{
`$INSTANCE_NAME`_SAR_INTR_MASK_REG |= `$INSTANCE_NAME`_INJ_RANGE_MASK;
}
}
#endif /* `$INSTANCE_NAME`_INJ_CHANNEL_ENABLED */
if((`$INSTANCE_NAME`_channelsConfig[chNum] & `$INSTANCE_NAME`_ALT_RESOLUTION_ON) != 0u)
{
counts = (int32)`$INSTANCE_NAME`_DEFAULT_MAX_WRK_ALT;
}
else
{
counts = (int32)`$INSTANCE_NAME`_SAR_WRK_MAX_12BIT;
}
if((`$INSTANCE_NAME`_channelsConfig[chNum] & `$INSTANCE_NAME`_DIFFERENTIAL_EN) == 0u)
{
#if((`$INSTANCE_NAME`_DEFAULT_SE_RESULT_FORMAT_SEL == `$INSTANCE_NAME`__FSIGNED) && \
(`$INSTANCE_NAME`_DEFAULT_NEG_INPUT_SEL == `$INSTANCE_NAME`__VREF))
/* Set offset to the minus half scale to convert results to unsigned format */
`$INSTANCE_NAME`_offset[chNum] = (int16)(counts / -2);
#else
`$INSTANCE_NAME`_offset[chNum] = 0;
#endif /* end DEFAULT_SE_RESULT_FORMAT_SEL == `$INSTANCE_NAME`__FSIGNED */
}
else /* Differential channel */
{
#if(`$INSTANCE_NAME`_DEFAULT_DIFF_RESULT_FORMAT_SEL == `$INSTANCE_NAME`__FUNSIGNED)
/* Set offset to the half scale to convert results to signed format */
`$INSTANCE_NAME`_offset[chNum] = (int16)(counts / 2);
#else
`$INSTANCE_NAME`_offset[chNum] = 0;
#endif /* end `$INSTANCE_NAME`_DEFAULT_DIFF_RESULT_FORMAT_SEL == `$INSTANCE_NAME`__FUNSIGNED */
}
/* Calculate gain in counts per 10 volts with rounding */
`$INSTANCE_NAME`_countsPer10Volt[chNum] = (int16)(((counts * `$INSTANCE_NAME`_10MV_COUNTS) +
`$INSTANCE_NAME`_DEFAULT_VREF_MV_VALUE) / (`$INSTANCE_NAME`_DEFAULT_VREF_MV_VALUE * 2));
}
}
