CPU_BOOLEAN CSP_DMA_CH_FreeExt (CSP_DEV_NBR ch_nbr)
{
CSP_DMA_REG *p_dma_reg;
CSP_DMA_CH_REG *p_dma_ch_reg;
CSP_DMA_CH *p_ch_tbl;
CPU_SR_ALLOC();
#if (CSP_CFG_ARG_CHK_EN == DEF_ENABLED)
if (ch_nbr > CSP_DMA_CH_MAX_NBR - 1u) {
return (DEF_FAIL);
}
#endif
p_dma_reg = (CSP_DMA_REG *)CSP_ADDR_DMA_REG;
p_dma_ch_reg = &(p_dma_reg->CHx[ch_nbr]);
p_ch_tbl = &CSP_DMA_ChTbl[ch_nbr];
CPU_CRITICAL_ENTER();
p_dma_reg->IntTCClr = DEF_BIT(ch_nbr); /* Clear all pending interrupts. */
p_dma_reg->IntErrClr = DEF_BIT(ch_nbr);
p_ch_tbl->State = CSP_DMA_CH_STATE_FREE; /* Free the channel. */
p_dma_ch_reg->SrcAddr = DEF_BIT_NONE; /* Unitialize DMA channel cfg & ctrl registers. */
p_dma_ch_reg->DestAddr = DEF_BIT_NONE;
p_dma_ch_reg->Cfg = DEF_BIT_NONE;
p_dma_ch_reg->Ctrl = DEF_BIT_NONE;
CPU_CRITICAL_EXIT();
return (DEF_OK);
}
void CSP_TmrIntClr (CSP_DEV_NBR tmr_nbr)
{
CSP_TMR_REG *p_tmr_reg;
CSP_DEV_NBR match_nbr;
CPU_INT32U reg_msk;
CPU_INT32U reg_stat;
CPU_INT32U reg_clr;
#if (CSP_CFG_ARG_CHK_EN == DEF_ENABLED)
if (tmr_nbr > CSP_TMR_NBR_03) {
return;
}
#endif
p_tmr_reg = (CSP_TMR_REG *)CSP_TmrAddrTbl[tmr_nbr];
reg_clr = DEF_BIT_NONE;
reg_msk = p_tmr_reg->MCR;
reg_stat = p_tmr_reg->IR;
for (match_nbr = 0; match_nbr <= CSP_TMR_MATCH_NBR_03; match_nbr++) {
if ((DEF_BIT_IS_SET(reg_msk, CSP_TMR_BIT_MCR_MRIx(match_nbr)) == DEF_YES) &&
(DEF_BIT_IS_SET(reg_stat, DEF_BIT(match_nbr)) == DEF_YES)) {
DEF_BIT_SET(reg_clr, DEF_BIT(match_nbr));
}
}
p_tmr_reg->IR = reg_clr;
}
void BSP_PeriphEn (CPU_DATA pwr_clk_id)
{
switch (pwr_clk_id) {
case BSP_PERIPH_ID_DMA1:
case BSP_PERIPH_ID_DMA2:
case BSP_PERIPH_ID_SRAM:
case BSP_PERIPH_ID_FLITF:
case BSP_PERIPH_ID_CRC:
case BSP_PERIPH_ID_FSMC:
case BSP_PERIPH_ID_SDIO:
BSP_PERIPH_REG_RCC_AHBENR |= DEF_BIT(pwr_clk_id);
break;
case BSP_PERIPH_ID_AFIO:
case BSP_PERIPH_ID_IOPA:
case BSP_PERIPH_ID_IOPB:
case BSP_PERIPH_ID_IOPC:
case BSP_PERIPH_ID_IOPD:
case BSP_PERIPH_ID_IOPE:
case BSP_PERIPH_ID_IOPF:
case BSP_PERIPH_ID_IOPG:
case BSP_PERIPH_ID_ADC1:
case BSP_PERIPH_ID_ADC2:
case BSP_PERIPH_ID_TIM1:
case BSP_PERIPH_ID_SPI1:
case BSP_PERIPH_ID_TIM8:
case BSP_PERIPH_ID_USART1:
case BSP_PERIPH_ID_ADC3:
BSP_PERIPH_REG_RCC_APB2ENR |= DEF_BIT(pwr_clk_id - 32);
break;
case BSP_PERIPH_ID_TIM2:
case BSP_PERIPH_ID_TIM3:
case BSP_PERIPH_ID_TIM4:
case BSP_PERIPH_ID_TIM5:
case BSP_PERIPH_ID_TIM6:
case BSP_PERIPH_ID_TIM7:
case BSP_PERIPH_ID_WWDG:
case BSP_PERIPH_ID_SPI2:
case BSP_PERIPH_ID_SPI3:
case BSP_PERIPH_ID_USART2:
case BSP_PERIPH_ID_USART3:
case BSP_PERIPH_ID_USART4:
case BSP_PERIPH_ID_USART5:
case BSP_PERIPH_ID_I2C1:
case BSP_PERIPH_ID_I2C2:
case BSP_PERIPH_ID_USB:
case BSP_PERIPH_ID_CAN:
case BSP_PERIPH_ID_BKP:
case BSP_PERIPH_ID_PWR:
case BSP_PERIPH_ID_DAC:
BSP_PERIPH_REG_RCC_APB1ENR |= DEF_BIT(pwr_clk_id - 64);
break;
}
}
static void CSP_DMA_IntHandler (void *p_arg)
{
CSP_DMA_REG *p_dma_reg;
CSP_DMA_CH_REG *p_dma_ch_reg;
CSP_DMA_CH *p_dma_ch;
void *p_callback_arg;
CSP_DMA_CALLBACK_PTR callback_fnct;
CSP_DEV_NBR ch_nbr;
CPU_INT32U int_tc_stat;
CPU_INT32U int_err_stat;
CPU_BOOLEAN status;
CPU_INT16U xfer_size_rem;
p_dma_reg = (CSP_DMA_REG *)CSP_ADDR_DMA_REG;
int_tc_stat = p_dma_reg->IntTCStat & DEF_BIT_FIELD(8u, 0u);
int_err_stat = p_dma_reg->IntErrStat & DEF_BIT_FIELD(8u, 0u);
/* --------- INTERRUPT TERMINAL COUNT HANDLING -------- */
while (int_tc_stat != DEF_BIT_NONE) {
/* Get current DMA channel number */
ch_nbr = 31u - CPU_CntLeadZeros(int_tc_stat);
p_dma_ch_reg = &(p_dma_reg->CHx[ch_nbr]);
p_dma_ch = &(CSP_DMA_ChTbl[ch_nbr]);
callback_fnct = p_dma_ch->CallBackFnctPtr; /* Get the callback function */
p_callback_arg = p_dma_ch->CallBackArgPtr; /* Get the callback argument pointer. */
/* Get the remaining transfer size. */
xfer_size_rem = p_dma_ch_reg->Ctrl & DEF_BIT_FIELD(12u, 0u);
p_dma_reg->IntTCClr = DEF_BIT(ch_nbr); /* Clear the terminal count interrupt. */
if (DEF_BIT_IS_SET(int_err_stat, DEF_BIT(ch_nbr))) { /* If an error occured in the channel... */
status = DEF_FAIL; /* ... set the status, and clear the error interrupt. */
p_dma_reg->IntErrClr = DEF_BIT(ch_nbr);
} else {
status = DEF_OK;
}
callback_fnct(ch_nbr, /* Call the callback function. */
xfer_size_rem,
p_callback_arg,
status);
/* Read the terminal count and error interrupts status */
int_tc_stat = p_dma_reg->IntTCStat & DEF_BIT_FIELD(8u, 0u);
int_err_stat = p_dma_reg->IntErrStat & DEF_BIT_FIELD(8u, 0u);
}
/* --------------- ERROR INTERRUPT HANDLING ------------ */
int_err_stat = p_dma_reg->IntErrStat & DEF_BIT_FIELD(8u, 0u);
while (int_err_stat != DEF_BIT_NONE) {
ch_nbr = 31u - CPU_CntLeadZeros(int_err_stat);
p_dma_ch_reg = &(p_dma_reg->CHx[ch_nbr]);
p_dma_ch = &(CSP_DMA_ChTbl[ch_nbr]);
callback_fnct = p_dma_ch->CallBackFnctPtr;
p_callback_arg = p_dma_ch->CallBackArgPtr;
p_dma_ch->State = CSP_DMA_CH_STATE_ALLOC; /* Set the channel state = 'ALLOC' */
xfer_size_rem = p_dma_ch_reg->Ctrl & DEF_BIT_FIELD(12u, 0u);
status = DEF_FAIL;
p_dma_reg->IntErrClr = DEF_BIT(ch_nbr);
callback_fnct(ch_nbr,
xfer_size_rem,
p_callback_arg,
status);
int_err_stat = p_dma_reg->IntErrStat & DEF_BIT_FIELD(8u, 0u);
}
}
CPU_BOOLEAN CSP_DMA_CH_CfgExt (CSP_DEV_NBR ch_nbr,
CSP_OPT xfer_type,
CSP_OPT src_burst_size,
CSP_OPT src_width,
CSP_OPT dest_burst_size,
CSP_OPT dest_width,
CSP_DEV_NBR src_req,
CSP_DEV_NBR dest_req)
{ CSP_DMA_REG *p_dma_reg;
CSP_DMA_CH_REG *p_dma_ch_reg;
CPU_INT32U reg_cfg;
CPU_INT32U reg_ctrl;
CPU_INT32U reg_val;
CPU_SR_ALLOC();
/* ------------------ ARGUMENTS CHECKING -------------- */
#if (CSP_CFG_ARG_CHK_EN == DEF_ENABLED)
if (ch_nbr > CSP_DMA_CH_MAX_NBR - 1u) { /* Invalid channel number? */
return (DEF_FAIL);
}
/* Channel not available? */
if (CSP_DMA_ChTbl[ch_nbr].State != CSP_DMA_CH_STATE_ALLOC) {
return (DEF_FAIL);
}
if ((src_width != CPU_WORD_SIZE_08) && /* Check src width parameter. */
(src_width != CPU_WORD_SIZE_16) &&
(src_width != CPU_WORD_SIZE_32)) {
return (DEF_FAIL);
}
if ((dest_width != CPU_WORD_SIZE_08) && /* Check src width parameter. */
(dest_width != CPU_WORD_SIZE_16) &&
(dest_width != CPU_WORD_SIZE_32)) {
return (DEF_FAIL);
}
#endif
/* Channel configuration. */
reg_cfg = DEF_BIT_NONE;
reg_ctrl = DEF_BIT_NONE;
if (src_burst_size == 255u) { /* Set the source/destination burst size. */
reg_val = 7u;
} else if (src_burst_size >= 4u) {
reg_val = (DEF_INT_32_NBR_BITS - CPU_CntLeadZeros(src_burst_size) - 2u);
} else {
reg_val = DEF_BIT_NONE;
}
DEF_BIT_SET(reg_ctrl, reg_val << 12u);
if (dest_burst_size == 255u) {
reg_val = 7u;
} else if (dest_burst_size >= 4u) {
reg_val = (DEF_INT_32_NBR_BITS - CPU_CntLeadZeros(dest_burst_size) - 2u);
} else {
reg_val = DEF_BIT_NONE;
}
DEF_BIT_SET(reg_ctrl, reg_val << 15u);
DEF_BIT_SET(reg_ctrl, (src_width - 1u) << 18u);
DEF_BIT_SET(reg_ctrl, (dest_width - 1u) << 21u);
/* Set the transfer type. */
switch (xfer_type) {
case CSP_DMA_XFER_TYPE_MEM_TO_PER:
DEF_BIT_SET(reg_cfg, CSP_DMA_BIT_CH_CFG_XFER_MEM_TO_PER);
break;
case CSP_DMA_XFER_TYPE_MEM_TO_MEM:
DEF_BIT_SET(reg_cfg, CSP_DMA_BIT_CH_CFG_XFER_MEM_TO_MEM);
break;
case CSP_DMA_XFER_TYPE_PER_TO_MEM:
DEF_BIT_SET(reg_cfg, CSP_DMA_BIT_CH_CFG_XFER_PER_TO_MEM);
break;
case CSP_DMA_XFER_TYPE_PER_TO_PER:
DEF_BIT_SET(reg_cfg, CSP_DMA_BIT_CH_CFG_XFER_PER_TO_PER);
break;
default:
return (DEF_FAIL);
}
/* Configure source request signal (see note #3) */
/* ... transfer from peripheral? */
if (((xfer_type == CSP_DMA_XFER_TYPE_PER_TO_MEM ) ||
(xfer_type == CSP_DMA_XFER_TYPE_PER_TO_PER ))) {
if (src_req < CSP_DMA_XFER_PER_REQ_UART_00_TX) {
;
} else if (src_req < CSP_DMA_XFER_PER_REQ_TMR_00_MATCH_0) {
CPU_CRITICAL_ENTER();
DEF_BIT_CLR(CSP_DMA_REG_REQ_SEL, DEF_BIT(src_req - CSP_DMA_XFER_PER_REQ_UART_00_TX));
CPU_CRITICAL_EXIT();
} else {
src_req -= CSP_DMA_XFER_PER_REQ_UART_00_TX;
CPU_CRITICAL_ENTER();
DEF_BIT_SET(CSP_DMA_REG_REQ_SEL, DEF_BIT(src_req - CSP_DMA_XFER_PER_REQ_UART_00_TX));
CPU_CRITICAL_EXIT();
}
DEF_BIT_SET(reg_cfg, (src_req & CSP_DMA_MSK_CH_CFG_PER_REQ) << 1u);
}
if (((xfer_type == CSP_DMA_XFER_TYPE_MEM_TO_PER ) ||
(xfer_type == CSP_DMA_XFER_TYPE_PER_TO_PER ))) {
if (dest_req < CSP_DMA_XFER_PER_REQ_UART_00_TX) {
;
} else if (dest_req < CSP_DMA_XFER_PER_REQ_TMR_00_MATCH_0) {
CPU_CRITICAL_ENTER();
DEF_BIT_CLR(CSP_DMA_REG_REQ_SEL, DEF_BIT(dest_req - CSP_DMA_XFER_PER_REQ_UART_00_TX));
CPU_CRITICAL_EXIT();
} else {
dest_req -= CSP_DMA_XFER_PER_REQ_UART_00_TX;
CPU_CRITICAL_ENTER();
DEF_BIT_SET(CSP_DMA_REG_REQ_SEL, DEF_BIT(dest_req - CSP_DMA_XFER_PER_REQ_UART_00_TX));
CPU_CRITICAL_EXIT();
}
DEF_BIT_SET(reg_cfg, (dest_req & CSP_DMA_MSK_CH_CFG_PER_REQ) << 6u);
}
p_dma_reg = (CSP_DMA_REG *)CSP_ADDR_DMA_REG;
p_dma_ch_reg = &(p_dma_reg->CHx[ch_nbr]);
CPU_CRITICAL_ENTER();
p_dma_ch_reg->Cfg = (CPU_INT32U)reg_cfg;
p_dma_ch_reg->Ctrl = (CPU_INT32U)reg_ctrl;
CPU_CRITICAL_EXIT();
return (DEF_OK);
}
void BSP_GPIO_Cfg (CPU_INT08U gpio_port,
CPU_INT32U gpio_pins,
CPU_INT16U gpio_opt)
{
BSP_GPIO_FAST_REG *p_gpio_fast_reg;
CPU_REG32 *p_gpio_pinsel;
CPU_REG32 *p_gpio_pinmode;
CPU_REG32 *p_gpio_pinmode_od;
CPU_INT32U pinsel_opt;
CPU_INT32U pinmode_opt;
CPU_INT32U pin_nbr;
switch (gpio_port) {
case BSP_GPIO_PORT0_FAST:
p_gpio_fast_reg = (BSP_GPIO_FAST_REG *)(BSP_GPIO_REG_PORT0_FAST_BASE_ADDR);
p_gpio_pinsel = (CPU_REG32 *)(BSP_GPIO_REG_PINSEL_BASE_ADDR + 0x00);
p_gpio_pinmode = (CPU_REG32 *)(BSP_GPIO_REG_PINMODE_BASE_ADDR + 0x00);
p_gpio_pinmode_od = (CPU_REG32 *)(BSP_GPIO_REG_PINMODE_OD0_BASE_ADDR);
break;
case BSP_GPIO_PORT1_FAST:
p_gpio_fast_reg = (BSP_GPIO_FAST_REG *)(BSP_GPIO_REG_PORT1_FAST_BASE_ADDR);
p_gpio_pinsel = (CPU_REG32 *)(BSP_GPIO_REG_PINSEL_BASE_ADDR + 0x08);
p_gpio_pinmode = (CPU_REG32 *)(BSP_GPIO_REG_PINMODE_BASE_ADDR + 0x08);
p_gpio_pinmode_od = (CPU_REG32 *)(BSP_GPIO_REG_PINMODE_OD1_BASE_ADDR);
break;
case BSP_GPIO_PORT2_FAST:
p_gpio_fast_reg = (BSP_GPIO_FAST_REG *)(BSP_GPIO_REG_PORT2_FAST_BASE_ADDR);
p_gpio_pinsel = (CPU_REG32 *)(BSP_GPIO_REG_PINSEL_BASE_ADDR + 0x10);
p_gpio_pinmode = (CPU_REG32 *)(BSP_GPIO_REG_PINMODE_BASE_ADDR + 0x10);
p_gpio_pinmode_od = (CPU_REG32 *)(BSP_GPIO_REG_PINMODE_OD2_BASE_ADDR);
break;
case BSP_GPIO_PORT3_FAST:
p_gpio_fast_reg = (BSP_GPIO_FAST_REG *)(BSP_GPIO_REG_PORT3_FAST_BASE_ADDR);
p_gpio_pinsel = (CPU_REG32 *)(BSP_GPIO_REG_PINSEL_BASE_ADDR + 0x18);
p_gpio_pinmode = (CPU_REG32 *)(BSP_GPIO_REG_PINMODE_BASE_ADDR + 0x18);
p_gpio_pinmode_od = (CPU_REG32 *)(BSP_GPIO_REG_PINMODE_OD3_BASE_ADDR);
break;
case BSP_GPIO_PORT4_FAST:
p_gpio_fast_reg = (BSP_GPIO_FAST_REG *)(BSP_GPIO_REG_PORT4_FAST_BASE_ADDR);
p_gpio_pinsel = (CPU_REG32 *)(BSP_GPIO_REG_PINSEL_BASE_ADDR + 0x20);
p_gpio_pinmode = (CPU_REG32 *)(BSP_GPIO_REG_PINMODE_BASE_ADDR + 0x20);
p_gpio_pinmode_od = (CPU_REG32 *)(BSP_GPIO_REG_PINMODE_OD4_BASE_ADDR);
break;
case BSP_GPIO_PORT0:
case BSP_GPIO_PORT1:
default:
return;
}
/* ------------ I/O DIRECTION CONFIGURATION ----------- */
if (DEF_BIT_IS_SET(gpio_opt, BSP_GPIO_OPT_OUT_EN)) {
DEF_BIT_SET(p_gpio_fast_reg->FIODIR, gpio_pins);
}
if (DEF_BIT_IS_SET(gpio_opt, BSP_GPIO_OPT_IN_EN)) {
DEF_BIT_CLR(p_gpio_fast_reg->FIODIR, gpio_pins);
}
if (DEF_BIT_IS_SET(gpio_opt, BSP_GPIO_OPT_RD_WR_EN)) {
DEF_BIT_CLR(p_gpio_fast_reg->FIOMASK, gpio_pins);
}
if (DEF_BIT_IS_SET(gpio_opt, BSP_GPIO_OPT_RD_WR_DIS)) {
DEF_BIT_SET(p_gpio_fast_reg->FIOMASK, gpio_pins);
}
/* ---- I/O MODE/PERIPHERAL FUNCTION CONFIGURATION ---- */
pinsel_opt = BSP_GPIO_OPT_FNCT_INVALID;
pinmode_opt = BSP_GPIO_OPT_MODE_INVALID;
/* Set PINSELxx based on BSP_GPIO_OPT_FNCT_xxx */
if (DEF_BIT_IS_SET_ANY(gpio_opt, BSP_GPIO_OPT_FNCT_ANY)) {
if (DEF_BIT_IS_SET(gpio_opt, BSP_GPIO_OPT_FNCT_1)) {
pinsel_opt = 0x00;
} else if (DEF_BIT_IS_SET(gpio_opt, BSP_GPIO_OPT_FNCT_2)) {
pinsel_opt = 0x01;
} else if (DEF_BIT_IS_SET(gpio_opt, BSP_GPIO_OPT_FNCT_3)) {
pinsel_opt = 0x02;
} else if (DEF_BIT_IS_SET(gpio_opt, BSP_GPIO_OPT_FNCT_4)) {
pinsel_opt = 0x03;
} else {
return;
}
}
/* Set PMODExx based on BSP_GPIO_OPT_MDOE_xxx */
if (DEF_BIT_IS_SET_ANY(gpio_opt, BSP_GPIO_OPT_MODE_ANY)) {
if (DEF_BIT_IS_SET(gpio_opt, BSP_GPIO_OPT_MODE_PULLUP)) {
pinmode_opt = 0x00;
} else if (DEF_BIT_IS_SET(gpio_opt, BSP_GPIO_OPT_MODE_REPEATER)) {
pinmode_opt = 0x01;
} else if (DEF_BIT_IS_SET(gpio_opt, BSP_GPIO_OPT_MODE_NONE)) {
pinmode_opt = 0x02;
} else if (DEF_BIT_IS_SET(gpio_opt, BSP_GPIO_OPT_MODE_PULLDOWN)) {
pinmode_opt = 0x03;
}
}
if ((pinsel_opt != BSP_GPIO_OPT_FNCT_INVALID) ||
(pinmode_opt != BSP_GPIO_OPT_MODE_INVALID)) {
for (pin_nbr = 0; pin_nbr < 32; pin_nbr++) {
if (DEF_BIT_IS_SET(gpio_pins, DEF_BIT(pin_nbr))) {
if (pinsel_opt != BSP_GPIO_OPT_FNCT_INVALID) {
if (pin_nbr < 16) {
DEF_BIT_CLR(*p_gpio_pinsel, DEF_BIT_FIELD(2, pin_nbr * 2));
DEF_BIT_SET(*p_gpio_pinsel, DEF_BIT_MASK(pinsel_opt, pin_nbr * 2));
} else {
DEF_BIT_CLR(*((CPU_REG32 *)((CPU_INT32U)p_gpio_pinsel + 0x04)), DEF_BIT_FIELD(2, (pin_nbr - 16) * 2));
DEF_BIT_SET(*((CPU_REG32 *)((CPU_INT32U)p_gpio_pinsel + 0x04)), DEF_BIT_MASK(pinsel_opt, (pin_nbr - 16) * 2));
}
}
if (DEF_BIT_IS_SET(gpio_pins, DEF_BIT(pin_nbr))) {
if (pinmode_opt != BSP_GPIO_OPT_MODE_INVALID) {
if (pin_nbr < 16) {
DEF_BIT_CLR(*p_gpio_pinmode, DEF_BIT_FIELD(2, pin_nbr * 2));
DEF_BIT_SET(*p_gpio_pinmode, DEF_BIT_MASK(pinmode_opt, pin_nbr * 2));
} else {
DEF_BIT_CLR(*((CPU_REG32 *)((CPU_INT32U)p_gpio_pinmode + 0x04)), DEF_BIT_FIELD(2, (pin_nbr - 16) * 2));
DEF_BIT_SET(*((CPU_REG32 *)((CPU_INT32U)p_gpio_pinmode + 0x04)), DEF_BIT_MASK(pinmode_opt, (pin_nbr - 16) * 2));
}
}
}
}
}
}
if (DEF_BIT_IS_SET(gpio_opt, BSP_GPIO_OPT_MODE_OPEN_DRAIN)) {
*p_gpio_pinmode_od = gpio_pins;
}
}
