/*
* bus dma alloc handle entry point:
*/
int
px_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_attr_t *attrp,
int (*waitfp)(caddr_t), caddr_t arg, ddi_dma_handle_t *handlep)
{
px_t *px_p = DIP_TO_STATE(dip);
ddi_dma_impl_t *mp;
int rval;
DBG(DBG_DMA_ALLOCH, dip, "rdip=%s%d\n",
ddi_driver_name(rdip), ddi_get_instance(rdip));
if (attrp->dma_attr_version != DMA_ATTR_V0)
return (DDI_DMA_BADATTR);
if (!(mp = px_dma_allocmp(dip, rdip, waitfp, arg)))
return (DDI_DMA_NORESOURCES);
/*
* Save requestor's information
*/
mp->dmai_attr = *attrp; /* whole object - augmented later */
*PX_DEV_ATTR(mp) = *attrp; /* whole object - device orig attr */
DBG(DBG_DMA_ALLOCH, dip, "mp=%p\n", mp);
/* check and convert dma attributes to handle parameters */
if (rval = px_dma_attr2hdl(px_p, mp)) {
px_dma_freehdl(dip, rdip, (ddi_dma_handle_t)mp);
*handlep = NULL;
return (rval);
}
*handlep = (ddi_dma_handle_t)mp;
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
px_dma_ctlops(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle,
enum ddi_dma_ctlops cmd, off_t *offp, size_t *lenp, caddr_t *objp,
uint_t cache_flags)
{
ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle;
#ifdef DEBUG
DBG(DBG_DMA_CTL, dip, "%s: rdip=%s%d\n", px_dmactl_str[cmd],
ddi_driver_name(rdip), ddi_get_instance(rdip));
#endif /* DEBUG */
switch (cmd) {
case DDI_DMA_FREE:
(void) px_dma_unbindhdl(dip, rdip, handle);
(void) px_dma_freehdl(dip, rdip, handle);
return (DDI_SUCCESS);
case DDI_DMA_RESERVE: {
px_t *px_p = DIP_TO_STATE(dip);
return (px_fdvma_reserve(dip, rdip, px_p,
(ddi_dma_req_t *)offp, (ddi_dma_handle_t *)objp));
}
case DDI_DMA_RELEASE: {
px_t *px_p = DIP_TO_STATE(dip);
return (px_fdvma_release(dip, px_p, mp));
}
default:
break;
}
switch (PX_DMA_TYPE(mp)) {
case PX_DMAI_FLAGS_DVMA:
return (px_dvma_ctl(dip, rdip, mp, cmd, offp, lenp, objp,
cache_flags));
case PX_DMAI_FLAGS_PTP:
case PX_DMAI_FLAGS_BYPASS:
return (px_dma_ctl(dip, rdip, mp, cmd, offp, lenp, objp,
cache_flags));
default:
cmn_err(CE_PANIC, "%s%d: px_dma_ctlops(%x):bad dma type %x",
ddi_driver_name(rdip), ddi_get_instance(rdip), cmd,
mp->dmai_flags);
/*NOTREACHED*/
}
return (0);
}
/* ARGSUSED */
int
px_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op,
ddi_intr_handle_impl_t *hdlp, void *result)
{
int intr_types, ret = DDI_SUCCESS;
px_t *px_p = DIP_TO_STATE(dip);
DBG(DBG_INTROPS, dip, "px_intr_ops: rdip=%s%d\n",
ddi_driver_name(rdip), ddi_get_instance(rdip));
/* Process DDI_INTROP_SUPPORTED_TYPES request here */
if (intr_op == DDI_INTROP_SUPPORTED_TYPES) {
*(int *)result = i_ddi_get_intx_nintrs(rdip) ?
DDI_INTR_TYPE_FIXED : 0;
if ((pci_msi_get_supported_type(rdip,
&intr_types)) == DDI_SUCCESS) {
/*
* Double check supported interrupt types vs.
* what the host bridge supports.
*/
*(int *)result |= intr_types;
}
*(int *)result &=
(px_force_intx_support ?
(px_p->px_supp_intr_types | DDI_INTR_TYPE_FIXED) :
px_p->px_supp_intr_types);
return (*(int *)result ? DDI_SUCCESS : DDI_FAILURE);
}
/*
* PCI-E nexus driver supports fixed, MSI and MSI-X interrupts.
* Return failure if interrupt type is not supported.
*/
switch (hdlp->ih_type) {
case DDI_INTR_TYPE_FIXED:
ret = px_intx_ops(dip, rdip, intr_op, hdlp, result);
break;
case DDI_INTR_TYPE_MSI:
case DDI_INTR_TYPE_MSIX:
ret = px_msix_ops(dip, rdip, intr_op, hdlp, result);
break;
default:
ret = DDI_ENOTSUP;
break;
}
return (ret);
}
/*ARGSUSED*/
int
px_dma_unbindhdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle)
{
ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle;
px_t *px_p = DIP_TO_STATE(dip);
px_mmu_t *mmu_p = px_p->px_mmu_p;
DBG(DBG_DMA_UNBINDH, dip, "rdip=%s%d, mp=%p\n",
ddi_driver_name(rdip), ddi_get_instance(rdip), handle);
if ((mp->dmai_flags & PX_DMAI_FLAGS_INUSE) == 0) {
DBG(DBG_DMA_UNBINDH, dip, "handle not inuse\n");
return (DDI_FAILURE);
}
mp->dmai_error.err_cf = NULL;
/*
* Here if the handle is using the iommu. Unload all the iommu
* translations.
*/
switch (PX_DMA_TYPE(mp)) {
case PX_DMAI_FLAGS_DVMA:
px_mmu_unmap_window(mmu_p, mp);
px_dvma_unmap(mmu_p, mp);
px_dma_freepfn(mp);
break;
case PX_DMAI_FLAGS_BYPASS:
case PX_DMAI_FLAGS_PTP:
px_dma_freewin(mp);
break;
default:
cmn_err(CE_PANIC, "%s%d: px_dma_unbindhdl:bad dma type %p",
ddi_driver_name(rdip), ddi_get_instance(rdip), mp);
/*NOTREACHED*/
}
if (mmu_p->mmu_dvma_clid != 0) {
DBG(DBG_DMA_UNBINDH, dip, "run dvma callback\n");
ddi_run_callback(&mmu_p->mmu_dvma_clid);
}
if (px_kmem_clid) {
DBG(DBG_DMA_UNBINDH, dip, "run handle callback\n");
ddi_run_callback(&px_kmem_clid);
}
mp->dmai_flags &= PX_DMAI_FLAGS_PRESERVE;
return (DDI_SUCCESS);
}
/*
* bus dma bind handle entry point:
*/
int
px_dma_bindhdl(dev_info_t *dip, dev_info_t *rdip,
ddi_dma_handle_t handle, ddi_dma_req_t *dmareq,
ddi_dma_cookie_t *cookiep, uint_t *ccountp)
{
px_t *px_p = DIP_TO_STATE(dip);
px_mmu_t *mmu_p = px_p->px_mmu_p;
ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle;
int ret;
DBG(DBG_DMA_BINDH, dip, "rdip=%s%d mp=%p dmareq=%p\n",
ddi_driver_name(rdip), ddi_get_instance(rdip), mp, dmareq);
if (mp->dmai_flags & PX_DMAI_FLAGS_INUSE)
return (DDI_DMA_INUSE);
ASSERT((mp->dmai_flags & ~PX_DMAI_FLAGS_PRESERVE) == 0);
mp->dmai_flags |= PX_DMAI_FLAGS_INUSE;
if (ret = px_dma_type(px_p, dmareq, mp))
goto err;
if (ret = px_dma_pfn(px_p, dmareq, mp))
goto err;
switch (PX_DMA_TYPE(mp)) {
case PX_DMAI_FLAGS_DVMA:
if (ret = px_dvma_win(px_p, dmareq, mp))
goto map_err;
if (!PX_DMA_CANCACHE(mp)) { /* try fast track */
if (PX_DMA_CANFAST(mp)) {
if (!px_dvma_map_fast(mmu_p, mp))
goto mapped; /*LINTED E_NOP_ELSE_STMT*/
} else {
PX_DVMA_FASTTRAK_PROF(mp);
}
}
if (ret = px_dvma_map(mp, dmareq, mmu_p))
goto map_err;
mapped:
*ccountp = 1;
MAKE_DMA_COOKIE(cookiep, mp->dmai_mapping, mp->dmai_size);
break;
case PX_DMAI_FLAGS_BYPASS:
case PX_DMAI_FLAGS_PTP:
if (ret = px_dma_physwin(px_p, dmareq, mp))
goto map_err;
*ccountp = PX_WINLST(mp)->win_ncookies;
*cookiep =
*(ddi_dma_cookie_t *)(PX_WINLST(mp) + 1); /* wholeobj */
break;
default:
cmn_err(CE_PANIC, "%s%d: px_dma_bindhdl(%p): bad dma type",
ddi_driver_name(rdip), ddi_get_instance(rdip), mp);
/*NOTREACHED*/
}
DBG(DBG_DMA_BINDH, dip, "cookie %" PRIx64 "+%x\n",
cookiep->dmac_address, cookiep->dmac_size);
px_dump_dma_handle(DBG_DMA_MAP, dip, mp);
/* insert dma handle into FMA cache */
if (mp->dmai_attr.dma_attr_flags & DDI_DMA_FLAGERR)
mp->dmai_error.err_cf = px_err_dma_hdl_check;
return (mp->dmai_nwin == 1 ? DDI_DMA_MAPPED : DDI_DMA_PARTIAL_MAP);
map_err:
px_dma_freepfn(mp);
err:
mp->dmai_flags &= PX_DMAI_FLAGS_PRESERVE;
return (ret);
}
/*
* bus dma map entry point
* return value:
* DDI_DMA_PARTIAL_MAP 1
* DDI_DMA_MAPOK 0
* DDI_DMA_MAPPED 0
* DDI_DMA_NORESOURCES -1
* DDI_DMA_NOMAPPING -2
* DDI_DMA_TOOBIG -3
*/
int
px_dma_setup(dev_info_t *dip, dev_info_t *rdip, ddi_dma_req_t *dmareq,
ddi_dma_handle_t *handlep)
{
px_t *px_p = DIP_TO_STATE(dip);
px_mmu_t *mmu_p = px_p->px_mmu_p;
ddi_dma_impl_t *mp;
int ret;
DBG(DBG_DMA_MAP, dip, "mapping - rdip=%s%d type=%s\n",
ddi_driver_name(rdip), ddi_get_instance(rdip),
handlep ? "alloc" : "advisory");
if (!(mp = px_dma_lmts2hdl(dip, rdip, mmu_p, dmareq)))
return (DDI_DMA_NORESOURCES);
if (mp == (ddi_dma_impl_t *)DDI_DMA_NOMAPPING)
return (DDI_DMA_NOMAPPING);
if (ret = px_dma_type(px_p, dmareq, mp))
goto freehandle;
if (ret = px_dma_pfn(px_p, dmareq, mp))
goto freehandle;
switch (PX_DMA_TYPE(mp)) {
case PX_DMAI_FLAGS_DVMA: /* LINTED E_EQUALITY_NOT_ASSIGNMENT */
if ((ret = px_dvma_win(px_p, dmareq, mp)) || !handlep)
goto freehandle;
if (!PX_DMA_CANCACHE(mp)) { /* try fast track */
if (PX_DMA_CANFAST(mp)) {
if (!px_dvma_map_fast(mmu_p, mp))
break;
/* LINTED E_NOP_ELSE_STMT */
} else {
PX_DVMA_FASTTRAK_PROF(mp);
}
}
if (ret = px_dvma_map(mp, dmareq, mmu_p))
goto freehandle;
break;
case PX_DMAI_FLAGS_PTP: /* LINTED E_EQUALITY_NOT_ASSIGNMENT */
if ((ret = px_dma_physwin(px_p, dmareq, mp)) || !handlep)
goto freehandle;
break;
case PX_DMAI_FLAGS_BYPASS:
default:
cmn_err(CE_PANIC, "%s%d: px_dma_setup: bad dma type 0x%x",
ddi_driver_name(rdip), ddi_get_instance(rdip),
PX_DMA_TYPE(mp));
/*NOTREACHED*/
}
*handlep = (ddi_dma_handle_t)mp;
mp->dmai_flags |= PX_DMAI_FLAGS_INUSE;
px_dump_dma_handle(DBG_DMA_MAP, dip, mp);
return ((mp->dmai_nwin == 1) ? DDI_DMA_MAPPED : DDI_DMA_PARTIAL_MAP);
freehandle:
if (ret == DDI_DMA_NORESOURCES)
px_dma_freemp(mp); /* don't run_callback() */
else
(void) px_dma_freehdl(dip, rdip, (ddi_dma_handle_t)mp);
return (ret);
}
/*
* bus map entry point:
*
* if map request is for an rnumber
* get the corresponding regspec from device node
* build a new regspec in our parent's format
* build a new map_req with the new regspec
* call up the tree to complete the mapping
*/
int
px_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp,
off_t off, off_t len, caddr_t *addrp)
{
px_t *px_p = DIP_TO_STATE(dip);
struct regspec p_regspec;
ddi_map_req_t p_mapreq;
int reglen, rval, r_no;
pci_regspec_t reloc_reg, *rp = &reloc_reg;
DBG(DBG_MAP, dip, "rdip=%s%d:",
ddi_driver_name(rdip), ddi_get_instance(rdip));
if (mp->map_flags & DDI_MF_USER_MAPPING)
return (DDI_ME_UNIMPLEMENTED);
switch (mp->map_type) {
case DDI_MT_REGSPEC:
reloc_reg = *(pci_regspec_t *)mp->map_obj.rp; /* dup whole */
break;
case DDI_MT_RNUMBER:
r_no = mp->map_obj.rnumber;
DBG(DBG_MAP | DBG_CONT, dip, " r#=%x", r_no);
if (ddi_getlongprop(DDI_DEV_T_ANY, rdip, DDI_PROP_DONTPASS,
"reg", (caddr_t)&rp, ®len) != DDI_SUCCESS)
return (DDI_ME_RNUMBER_RANGE);
if (r_no < 0 || r_no >= reglen / sizeof (pci_regspec_t)) {
kmem_free(rp, reglen);
return (DDI_ME_RNUMBER_RANGE);
}
rp += r_no;
break;
default:
return (DDI_ME_INVAL);
}
DBG(DBG_MAP | DBG_CONT, dip, "\n");
if ((rp->pci_phys_hi & PCI_REG_ADDR_M) == PCI_ADDR_CONFIG) {
/*
* There may be a need to differentiate between PCI
* and PCI-Ex devices so the following range check is
* done correctly, depending on the implementation of
* pcieb bridge nexus driver.
*/
if ((off >= PCIE_CONF_HDR_SIZE) ||
(len > PCIE_CONF_HDR_SIZE) ||
(off + len > PCIE_CONF_HDR_SIZE))
return (DDI_ME_INVAL);
/*
* the following function returning a DDI_FAILURE assumes
* that there are no virtual config space access services
* defined in this layer. Otherwise it is availed right
* here and we return.
*/
rval = px_lib_map_vconfig(dip, mp, off, rp, addrp);
if (rval == DDI_SUCCESS)
goto done;
}
/*
* No virtual config space services or we are mapping
* a region of memory mapped config/IO/memory space, so proceed
* to the parent.
*/
/* relocate within 64-bit pci space through "assigned-addresses" */
if (rval = px_reloc_reg(dip, rdip, px_p, rp))
goto done;
if (len) /* adjust regspec according to mapping request */
rp->pci_size_low = len; /* MIN ? */
rp->pci_phys_low += off;
/* translate relocated pci regspec into parent space through "ranges" */
if (rval = px_xlate_reg(px_p, rp, &p_regspec))
goto done;
p_mapreq = *mp; /* dup the whole structure */
p_mapreq.map_type = DDI_MT_REGSPEC;
p_mapreq.map_obj.rp = &p_regspec;
px_lib_map_attr_check(&p_mapreq);
rval = ddi_map(dip, &p_mapreq, 0, 0, addrp);
if (rval == DDI_SUCCESS) {
/*
* Set-up access functions for FM access error capable drivers.
*/
if (DDI_FM_ACC_ERR_CAP(ddi_fm_capable(rdip)))
px_fm_acc_setup(mp, rdip, rp);
}
done:
if (mp->map_type == DDI_MT_RNUMBER)
kmem_free(rp - r_no, reglen);
return (rval);
}
/*
* control ops entry point:
*
* Requests handled completely:
* DDI_CTLOPS_INITCHILD see init_child() for details
* DDI_CTLOPS_UNINITCHILD
* DDI_CTLOPS_REPORTDEV see report_dev() for details
* DDI_CTLOPS_IOMIN cache line size if streaming otherwise 1
* DDI_CTLOPS_REGSIZE
* DDI_CTLOPS_NREGS
* DDI_CTLOPS_DVMAPAGESIZE
* DDI_CTLOPS_POKE
* DDI_CTLOPS_PEEK
*
* All others passed to parent.
*/
int
px_ctlops(dev_info_t *dip, dev_info_t *rdip,
ddi_ctl_enum_t op, void *arg, void *result)
{
px_t *px_p = DIP_TO_STATE(dip);
struct detachspec *ds;
struct attachspec *as;
switch (op) {
case DDI_CTLOPS_INITCHILD:
return (px_init_child(px_p, (dev_info_t *)arg));
case DDI_CTLOPS_UNINITCHILD:
return (px_uninit_child(px_p, (dev_info_t *)arg));
case DDI_CTLOPS_ATTACH:
if (!pcie_is_child(dip, rdip))
return (DDI_SUCCESS);
as = (struct attachspec *)arg;
switch (as->when) {
case DDI_PRE:
if (as->cmd == DDI_ATTACH) {
DBG(DBG_PWR, dip, "PRE_ATTACH for %s@%d\n",
ddi_driver_name(rdip),
ddi_get_instance(rdip));
return (pcie_pm_hold(dip));
}
if (as->cmd == DDI_RESUME) {
DBG(DBG_PWR, dip, "PRE_RESUME for %s@%d\n",
ddi_driver_name(rdip),
ddi_get_instance(rdip));
pcie_clear_errors(rdip);
}
return (DDI_SUCCESS);
case DDI_POST:
DBG(DBG_PWR, dip, "POST_ATTACH for %s@%d\n",
ddi_driver_name(rdip), ddi_get_instance(rdip));
if (as->cmd == DDI_ATTACH &&
as->result != DDI_SUCCESS) {
/*
* Attach failed for the child device. The child
* driver may have made PM calls before the
* attach failed. pcie_pm_remove_child() should
* cleanup PM state and holds (if any)
* associated with the child device.
*/
return (pcie_pm_remove_child(dip, rdip));
}
if (as->result == DDI_SUCCESS)
pf_init(rdip, (void *)px_p->px_fm_ibc, as->cmd);
(void) pcie_postattach_child(rdip);
return (DDI_SUCCESS);
default:
break;
}
break;
case DDI_CTLOPS_DETACH:
if (!pcie_is_child(dip, rdip))
return (DDI_SUCCESS);
ds = (struct detachspec *)arg;
switch (ds->when) {
case DDI_POST:
if (ds->cmd == DDI_DETACH &&
ds->result == DDI_SUCCESS) {
DBG(DBG_PWR, dip, "POST_DETACH for %s@%d\n",
ddi_driver_name(rdip),
ddi_get_instance(rdip));
return (pcie_pm_remove_child(dip, rdip));
}
return (DDI_SUCCESS);
case DDI_PRE:
pf_fini(rdip, ds->cmd);
return (DDI_SUCCESS);
default:
break;
}
break;
case DDI_CTLOPS_REPORTDEV:
if (ddi_get_parent(rdip) == dip)
return (px_report_dev(rdip));
(void) px_lib_fabric_sync(rdip);
return (DDI_SUCCESS);
case DDI_CTLOPS_IOMIN:
return (DDI_SUCCESS);
case DDI_CTLOPS_REGSIZE:
*((off_t *)result) = px_get_reg_set_size(rdip, *((int *)arg));
return (*((off_t *)result) == 0 ? DDI_FAILURE : DDI_SUCCESS);
case DDI_CTLOPS_NREGS:
*((uint_t *)result) = px_get_nreg_set(rdip);
return (DDI_SUCCESS);
case DDI_CTLOPS_DVMAPAGESIZE:
*((ulong_t *)result) = MMU_PAGE_SIZE;
return (DDI_SUCCESS);
case DDI_CTLOPS_POKE: /* platform dependent implementation. */
return (px_lib_ctlops_poke(dip, rdip,
(peekpoke_ctlops_t *)arg));
case DDI_CTLOPS_PEEK: /* platform dependent implementation. */
return (px_lib_ctlops_peek(dip, rdip,
(peekpoke_ctlops_t *)arg, result));
case DDI_CTLOPS_POWER:
default:
break;
}
/*
* Now pass the request up to our parent.
*/
DBG(DBG_CTLOPS, dip, "passing request to parent: rdip=%s%d\n",
ddi_driver_name(rdip), ddi_get_instance(rdip));
return (ddi_ctlops(dip, rdip, op, arg, result));
}
/*
* bus dma win entry point:
*/
int
px_dma_win(dev_info_t *dip, dev_info_t *rdip,
ddi_dma_handle_t handle, uint_t win, off_t *offp,
size_t *lenp, ddi_dma_cookie_t *cookiep, uint_t *ccountp)
{
ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle;
int ret;
DBG(DBG_DMA_WIN, dip, "rdip=%s%d\n",
ddi_driver_name(rdip), ddi_get_instance(rdip));
px_dump_dma_handle(DBG_DMA_WIN, dip, mp);
if (win >= mp->dmai_nwin) {
DBG(DBG_DMA_WIN, dip, "%x out of range\n", win);
return (DDI_FAILURE);
}
switch (PX_DMA_TYPE(mp)) {
case PX_DMAI_FLAGS_DVMA:
if (win != PX_DMA_CURWIN(mp)) {
px_t *px_p = DIP_TO_STATE(dip);
px_mmu_t *mmu_p = px_p->px_mmu_p;
px_mmu_unmap_window(mmu_p, mp);
/* map_window sets dmai_mapping/size/offset */
px_mmu_map_window(mmu_p, mp, win);
if ((ret = px_mmu_map_window(mmu_p,
mp, win)) != DDI_SUCCESS)
return (ret);
}
if (cookiep)
MAKE_DMA_COOKIE(cookiep, mp->dmai_mapping,
mp->dmai_size);
if (ccountp)
*ccountp = 1;
break;
case PX_DMAI_FLAGS_PTP:
case PX_DMAI_FLAGS_BYPASS: {
int i;
ddi_dma_cookie_t *ck_p;
px_dma_win_t *win_p = mp->dmai_winlst;
for (i = 0; i < win; win_p = win_p->win_next, i++) {};
ck_p = (ddi_dma_cookie_t *)(win_p + 1);
*cookiep = *ck_p;
mp->dmai_offset = win_p->win_offset;
mp->dmai_size = win_p->win_size;
mp->dmai_mapping = ck_p->dmac_laddress;
mp->dmai_cookie = ck_p + 1;
win_p->win_curseg = 0;
if (ccountp)
*ccountp = win_p->win_ncookies;
}
break;
default:
cmn_err(CE_WARN, "%s%d: px_dma_win:bad dma type 0x%x",
ddi_driver_name(rdip), ddi_get_instance(rdip),
PX_DMA_TYPE(mp));
return (DDI_FAILURE);
}
if (cookiep)
DBG(DBG_DMA_WIN, dip,
"cookie - dmac_address=%x dmac_size=%x\n",
cookiep->dmac_address, cookiep->dmac_size);
if (offp)
*offp = (off_t)mp->dmai_offset;
if (lenp)
*lenp = mp->dmai_size;
return (DDI_SUCCESS);
}
/*
* Perform register accesses on the nexus device itself.
*/
int
pxtool_bus_reg_ops(dev_info_t *dip, void *arg, int cmd, int mode)
{
pcitool_reg_t prg;
size_t size;
px_t *px_p = DIP_TO_STATE(dip);
boolean_t is_write = B_FALSE;
uint32_t rval = 0;
if (cmd == PCITOOL_NEXUS_SET_REG)
is_write = B_TRUE;
DBG(DBG_TOOLS, dip, "pxtool_bus_reg_ops set/get reg\n");
/* Read data from userland. */
if (ddi_copyin(arg, &prg, sizeof (pcitool_reg_t),
mode) != DDI_SUCCESS) {
DBG(DBG_TOOLS, dip, "Error reading arguments\n");
return (EFAULT);
}
size = PCITOOL_ACC_ATTR_SIZE(prg.acc_attr);
DBG(DBG_TOOLS, dip, "raw bus:0x%x, dev:0x%x, func:0x%x\n",
prg.bus_no, prg.dev_no, prg.func_no);
DBG(DBG_TOOLS, dip, "barnum:0x%x, offset:0x%" PRIx64 ", acc:0x%x\n",
prg.barnum, prg.offset, prg.acc_attr);
DBG(DBG_TOOLS, dip, "data:0x%" PRIx64 ", phys_addr:0x%" PRIx64 "\n",
prg.data, prg.phys_addr);
/*
* If bank num == ff, base phys addr passed in from userland.
*
* Normal bank specification is invalid, as there is no OBP property to
* back it up.
*/
if (prg.barnum != PCITOOL_BASE) {
prg.status = PCITOOL_OUT_OF_RANGE;
rval = EINVAL;
goto done;
}
/* Allow only size of 8-bytes. */
if (size != sizeof (uint64_t)) {
prg.status = PCITOOL_INVALID_SIZE;
rval = EINVAL;
goto done;
}
/* Alignment checking. */
if (!IS_P2ALIGNED(prg.offset, size)) {
DBG(DBG_TOOLS, dip, "not aligned.\n");
prg.status = PCITOOL_NOT_ALIGNED;
rval = EINVAL;
goto done;
}
prg.phys_addr += prg.offset;
/*
* Only the hypervisor can access nexus registers. As a result, there
* can be no error recovery in the OS. If there is an error, the
* system will go down, but with a trap type 7f. The OS cannot
* intervene with this kind of trap.
*/
/* Access device. prg.status is modified. */
rval = pxtool_phys_access(px_p, prg.phys_addr, &prg.data,
PCITOOL_ACC_IS_BIG_ENDIAN(prg.acc_attr), is_write);
done:
prg.drvr_version = PCITOOL_VERSION;
if (ddi_copyout(&prg, arg, sizeof (pcitool_reg_t),
mode) != DDI_SUCCESS) {
DBG(DBG_TOOLS, dip, "Copyout failed.\n");
return (EFAULT);
}
return (rval);
}
/*
* Perform register accesses on the nexus device itself.
*/
int
pxtool_bus_reg_ops(dev_info_t *dip, void *arg, int cmd, int mode)
{
pcitool_reg_t prg;
uint64_t base_addr;
uint32_t reglen;
px_t *px_p = DIP_TO_STATE(dip);
px_nexus_regspec_t *px_rp = NULL;
uint32_t numbanks = 0;
boolean_t write_flag = B_FALSE;
uint32_t rval = 0;
if (cmd == PCITOOL_NEXUS_SET_REG)
write_flag = B_TRUE;
DBG(DBG_TOOLS, dip, "pxtool_bus_reg_ops set/get reg\n");
/* Read data from userland. */
if (ddi_copyin(arg, &prg, sizeof (pcitool_reg_t), mode) !=
DDI_SUCCESS) {
DBG(DBG_TOOLS, dip, "Error reading arguments\n");
return (EFAULT);
}
/* Read reg property which contains starting addr and size of banks. */
if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
"reg", (int **)&px_rp, ®len) == DDI_SUCCESS) {
if (((reglen * sizeof (int)) %
sizeof (px_nexus_regspec_t)) != 0) {
DBG(DBG_TOOLS, dip, "reg prop not well-formed");
prg.status = PCITOOL_REGPROP_NOTWELLFORMED;
rval = EIO;
goto done;
}
}
numbanks = (reglen * sizeof (int)) / sizeof (px_nexus_regspec_t);
/* Bounds check the bank number. */
if (prg.barnum >= numbanks) {
prg.status = PCITOOL_OUT_OF_RANGE;
rval = EINVAL;
goto done;
}
base_addr = px_rp[prg.barnum].phys_addr;
prg.phys_addr = base_addr + prg.offset;
DBG(DBG_TOOLS, dip, "pxtool_bus_reg_ops: nexus: base:0x%" PRIx64 ", "
"offset:0x%" PRIx64 ", addr:0x%" PRIx64 ", max_offset:"
"0x%" PRIx64 "\n",
base_addr, prg.offset, prg.phys_addr, px_rp[prg.barnum].size);
if (prg.offset >= px_rp[prg.barnum].size) {
prg.status = PCITOOL_OUT_OF_RANGE;
rval = EINVAL;
goto done;
}
/* Access device. prg.status is modified. */
rval = pxtool_access(px_p, &prg, &prg.data, write_flag);
done:
if (px_rp != NULL)
ddi_prop_free(px_rp);
if (ddi_copyout(&prg, arg, sizeof (pcitool_reg_t),
mode) != DDI_SUCCESS) {
DBG(DBG_TOOLS, dip, "Copyout failed.\n");
return (EFAULT);
}
return (rval);
}