int pwm_write(const void *pwmb,unsigned int pwm_selector) { PWMB *pwm_block,*userPWMB; /*if(current_task != pwm.owner_task) return -1;*/ /* Choose PWM */ switch(pwm_selector){ case FPWM: DIRECTFPWMBLOCK(pwm_block); break; case SPWM: /* For 240 DIRECTSPWMBLOCK(pwm_block); */ break; } userPWMB = (PWMB*)pwmb; pwm_block->T1 = userPWMB->T1; pwm_block->T2 = userPWMB->T2; pwm_block->T3 = userPWMB->T3; return 1; }
int pwm_write(const void *pwmb,unsigned int pwm_selector) { PWMB *pwm_block,*userPWMB; /*if(current_task != pwm.owner_task) return -1;*/ /* Choose PWM */ switch(pwm_selector){ case FPWM: DIRECTFPWMBLOCK(pwm_block); break; case SPWM: /* For 240 DIRECTSPWMBLOCK(pwm_block); break; */ } userPWMB = (PWMB*)pwmb; pwm_block->T1 = userPWMB->T1; pwm_block->T2 = userPWMB->T2; pwm_block->T3 = userPWMB->T3; return 1; } int pwm_ioctl(unsigned request,void *argp) { /* unsigned *timebase; unsigned *action; unsigned *deadband; */ unsigned *uArgp = (unsigned *)argp; /*if(current_task != pwm.owner_task) return -1;*/ switch(request){ case PWM_RUN: MMREGS[COMCON] |= 0x8007; MMREGS[T1CNT] = 0; MMREGS[T1CON] |= 0x0040; break; case PWM_HOLD: MMREGS[COMCON] &= 0x7FF8; MMREGS[T1CON] &= 0x00B0; break; case PWM_TIMEBASE: /*timebase = (unsigned *)argp;*/ MMREGS[T1PR] = *uArgp;/**timebase;*/ break; case FPWM_ACTION: /*action = (unsigned *)argp;*/ MMREGS[ACTR] = *uArgp;/**action;*/ break; /* For 240 case SPWM_ACTION: */ /*action = (unsigned *)argp;*/ /* MMREGS[SACTR] = *uArgp;/*action;*//* MMREGS[OCRA] |= 0x0700; break; */ case PWM_DEADBAND: /*deadband = (unsigned *)argp;*/ /**deadband <<= 8;*/ *uArgp <<= 8; MMREGS[DBTCON] = 0; MMREGS[DBTCON] = *uArgp;/**deadband;*/ MMREGS[DBTCON] |= 0x00E0; break; case PWM_DBT1_ENABLE: MMREGS[DBTCON] |= 0x0020; break; case PWM_DBT1_DISABLE: MMREGS[DBTCON] &= 0xFFC0; break; case PWM_DBT2_ENABLE: MMREGS[DBTCON] |= 0x0040; break; case PWM_DBT2_DISABLE: MMREGS[DBTCON] &= 0xFFA0; break; case PWM_DBT3_ENABLE: MMREGS[DBTCON] |= 0x0080; break; case PWM_DBT3_DISABLE: MMREGS[DBTCON] &= 0x0060; break; } return 1; }