}; static struct clk_div_table mdivclk_d[] = { { .val = 0, .div = 1 }, { .val = 1, .div = 3 }, { .val = 2, .div = 5 }, { .val = 3, .div = 7 }, { .val = 4, .div = 9 }, { .val = 5, .div = 11 }, { .val = 6, .div = 13 }, { .val = 7, .div = 15 }, { /* sentinel */ }, }; static struct samsung_div_clock s3c2443_common_dividers[] __initdata = { DIV_T(0, "mdivclk", "xti", CLKDIV0, 6, 3, mdivclk_d), DIV(0, "prediv", "msysclk", CLKDIV0, 4, 2), DIV_T(HCLK, "hclk", "prediv", CLKDIV0, 0, 2, hclk_d), DIV(PCLK, "pclk", "hclk", CLKDIV0, 2, 1), DIV(0, "div_hsspi0_epll", "esysclk", CLKDIV1, 24, 2), DIV(0, "div_fimd", "esysclk", CLKDIV1, 16, 8), DIV(0, "div_i2s0", "esysclk", CLKDIV1, 12, 4), DIV(0, "div_uart", "esysclk", CLKDIV1, 8, 4), DIV(0, "div_hsmmc1", "esysclk", CLKDIV1, 6, 2), DIV(0, "div_usbhost", "esysclk", CLKDIV1, 4, 2), }; static struct samsung_gate_clock s3c2443_common_gates[] __initdata = { GATE(SCLK_HSMMC_EXT, "sclk_hsmmcext", "ext", SCLKCON, 13, 0, 0), GATE(SCLK_HSMMC1, "sclk_hsmmc1", "div_hsmmc1", SCLKCON, 12, 0, 0), GATE(SCLK_FIMD, "sclk_fimd", "div_fimd", SCLKCON, 10, 0, 0),
}; static struct clk_div_table divslow_d[] = { { .val = 0, .div = 1 }, { .val = 1, .div = 2 }, { .val = 2, .div = 4 }, { .val = 3, .div = 6 }, { .val = 4, .div = 8 }, { .val = 5, .div = 10 }, { .val = 6, .div = 12 }, { .val = 7, .div = 14 }, { /* sentinel */ }, }; static struct samsung_div_clock s3c2410_common_dividers[] __initdata = { DIV_T(0, "div_slow", "xti", CLKSLOW, 0, 3, divslow_d), DIV(PCLK, "pclk", "hclk", CLKDIVN, 0, 1), }; static struct samsung_gate_clock s3c2410_common_gates[] __initdata = { GATE(PCLK_SPI, "spi", "pclk", CLKCON, 18, 0, 0), GATE(PCLK_I2S, "i2s", "pclk", CLKCON, 17, 0, 0), GATE(PCLK_I2C, "i2c", "pclk", CLKCON, 16, 0, 0), GATE(PCLK_ADC, "adc", "pclk", CLKCON, 15, 0, 0), GATE(PCLK_RTC, "rtc", "pclk", CLKCON, 14, 0, 0), GATE(PCLK_GPIO, "gpio", "pclk", CLKCON, 13, CLK_IGNORE_UNUSED, 0), GATE(PCLK_UART2, "uart2", "pclk", CLKCON, 12, 0, 0), GATE(PCLK_UART1, "uart1", "pclk", CLKCON, 11, 0, 0), GATE(PCLK_UART0, "uart0", "pclk", CLKCON, 10, 0, 0), GATE(PCLK_SDI, "sdi", "pclk", CLKCON, 9, 0, 0), GATE(PCLK_PWM, "pwm", "pclk", CLKCON, 8, 0, 0),
#endif static struct clk_div_table divxti_d[] = { { .val = 0, .div = 1 }, { .val = 1, .div = 2 }, { .val = 2, .div = 4 }, { .val = 3, .div = 6 }, { .val = 4, .div = 8 }, { .val = 5, .div = 10 }, { .val = 6, .div = 12 }, { .val = 7, .div = 14 }, { /* sentinel */ }, }; struct samsung_div_clock s3c2412_dividers[] __initdata = { DIV_T(0, "div_xti", "xti", CLKSRC, 0, 3, divxti_d), DIV(0, "div_cam", "mux_cam", CLKDIVN, 16, 4), DIV(0, "div_i2s", "mux_i2s", CLKDIVN, 12, 4), DIV(0, "div_uart", "mux_uart", CLKDIVN, 8, 4), DIV(0, "div_usb", "mux_usb", CLKDIVN, 6, 1), DIV(0, "div_hclk_half", "hclk", CLKDIVN, 5, 1), DIV(ARMDIV, "armdiv", "msysclk", CLKDIVN, 3, 1), DIV(PCLK, "pclk", "hclk", CLKDIVN, 2, 1), DIV(HCLK, "hclk", "armdiv", CLKDIVN, 0, 2), }; struct samsung_fixed_factor_clock s3c2412_ffactor[] __initdata = { FFACTOR(0, "ff_hclk", "hclk", 2, 1, CLK_SET_RATE_PARENT), }; /*