void Configure_DMA(){ ADC2Filter_DMA_Chan = ADC2Filter_DMA_DmaInitialize(ADC2Filter_DMA_BYTES_PER_BURST, ADC2Filter_DMA_REQUEST_PER_BURST, HI16(ADC2Filter_DMA_SRC_BASE), HI16(ADC2Filter_DMA_DST_BASE)); ADC2Filter_DMA_TD[0] = CyDmaTdAllocate(); ADC2Filter_DMA_TD[1] = CyDmaTdAllocate(); CyDmaTdSetConfiguration(ADC2Filter_DMA_TD[0], 2, ADC2Filter_DMA_TD[1], TD_AUTO_EXEC_NEXT); CyDmaTdSetConfiguration(ADC2Filter_DMA_TD[1], 2, ADC2Filter_DMA_TD[0], ADC2Filter_DMA__TD_TERMOUT_EN); CyDmaTdSetAddress(ADC2Filter_DMA_TD[0], LO16((uint32)ADC_DelSig_1_DEC_SAMP_PTR), LO16((uint32)Filter_STAGEA_PTR)); CyDmaTdSetAddress(ADC2Filter_DMA_TD[1], LO16((uint32)ADC_DelSig_1_DEC_SAMP_PTR), LO16((uint32)Filter_STAGEB_PTR)); CyDmaChSetInitialTd(ADC2Filter_DMA_Chan, ADC2Filter_DMA_TD[0]); CyDmaChEnable(ADC2Filter_DMA_Chan, 1); /*Second buffer*/ DMA_2_Chan = DMA_2_DmaInitialize(DMA_2_BYTES_PER_BURST, DMA_2_REQUEST_PER_BURST, HI16(DMA_2_SRC_BASE), HI16(DMA_2_DST_BASE)); DMA_2_TD[0] = CyDmaTdAllocate(); CyDmaTdSetConfiguration(DMA_2_TD[0], buffersize, CY_DMA_DISABLE_TD /* DMA_2_TD[0]*/, DMA_2__TD_TERMOUT_EN | TD_INC_SRC_ADR | TD_INC_DST_ADR); CyDmaTdSetAddress(DMA_2_TD[0], LO16((uint32)ADC_samples), LO16((uint32)Buffer_samples)); CyDmaChSetInitialTd(DMA_2_Chan, DMA_2_TD[0]); CyDmaChEnable(DMA_2_Chan, 1); /*First buffer*/ DMA_1_Chan = DMA_1_DmaInitialize(DMA_1_BYTES_PER_BURST, DMA_1_REQUEST_PER_BURST, HI16(DMA_1_SRC_BASE), HI16(DMA_1_DST_BASE)); DMA_1_TD[0] = CyDmaTdAllocate(); CyDmaTdSetConfiguration(DMA_1_TD[0], buffersize,/* CY_DMA_DISABLE_TD*/ DMA_1_TD[0], DMA_1__TD_TERMOUT_EN | TD_INC_DST_ADR); CyDmaTdSetAddress(DMA_1_TD[0], LO16((uint32)Filter_HOLDA_PTR), LO16((uint32)ADC_samples)); CyDmaChSetInitialTd(DMA_1_Chan, DMA_1_TD[0]); CyDmaChEnable(DMA_1_Chan, 1); DMA_3_Chan = DMA_3_DmaInitialize(DMA_3_BYTES_PER_BURST, DMA_3_REQUEST_PER_BURST, HI16(DMA_3_SRC_BASE), HI16(DMA_3_DST_BASE)); DMA_3_TD[0] = CyDmaTdAllocate(); CyDmaTdSetConfiguration(DMA_3_TD[0], buffersize, DMA_3_TD[0], DMA_3__TD_TERMOUT_EN | TD_INC_DST_ADR); CyDmaTdSetAddress(DMA_3_TD[0], LO16((uint32)Filter_HOLDB_PTR), LO16((uint32)LPF_samples)); CyDmaChSetInitialTd(DMA_3_Chan, DMA_3_TD[0]); CyDmaChEnable(DMA_3_Chan, 1); DMA_4_Chan = DMA_4_DmaInitialize(DMA_4_BYTES_PER_BURST, DMA_4_REQUEST_PER_BURST, HI16(DMA_4_SRC_BASE), HI16(DMA_4_DST_BASE)); DMA_4_TD[0] = CyDmaTdAllocate(); CyDmaTdSetConfiguration(DMA_4_TD[0], buffersize, CY_DMA_DISABLE_TD /*DMA_4_TD[0]*/, DMA_4__TD_TERMOUT_EN | TD_INC_SRC_ADR | TD_INC_DST_ADR); CyDmaTdSetAddress(DMA_4_TD[0], LO16((uint32)LPF_samples), LO16((uint32)LPF_buffer)); CyDmaChSetInitialTd(DMA_4_Chan, DMA_4_TD[0]); CyDmaChEnable(DMA_4_Chan, 1); }
void DMA_2_Config() { // Variable declarations for DMA_2 // Move these variable declarations to the top of the function uint8 DMA_2_Chan; uint8 DMA_2_TD[1]; // DMA Configuration for DMA_2 #define DMA_2_BYTES_PER_BURST 2 #define DMA_2_REQUEST_PER_BURST 1 #define DMA_2_SRC_BASE (CYDEV_PERIPH_BASE) #define DMA_2_DST_BASE (CYDEV_SRAM_BASE) DMA_2_Chan = DMA_2_DmaInitialize(DMA_2_BYTES_PER_BURST, DMA_2_REQUEST_PER_BURST, HI16(DMA_2_SRC_BASE), HI16(DMA_2_DST_BASE)); DMA_2_TD[0] = CyDmaTdAllocate(); CyDmaTdSetConfiguration(DMA_2_TD[0], n*2, DMA_INVALID_TD, TD_SWAP_EN | DMA_2__TD_TERMOUT_EN | TD_INC_SRC_ADR | TD_INC_DST_ADR); CyDmaTdSetAddress(DMA_2_TD[0], LO16((uint32)Filter_1_HOLDAM_PTR), LO16((uint32)V_Sample)); CyDmaChSetInitialTd(DMA_2_Chan, DMA_2_TD[0]); CyDmaChEnable(DMA_2_Chan, 1); }
/******************************************************************************* * Function Name: DMA_Config ******************************************************************************** * * Summary: * Initializes and sets up DMA for use (generated by DMA Wizard) * * Parameters: * None. * * Return: * None. * *******************************************************************************/ void DMA_Config(void) { /* Declare variable to hold the handle for DMA channel */ uint8 channelHandle; /* Declare DMA Transaction Descriptor for memory transfer into * Filter Channel. */ uint8 tdChanA; /* Configure the DMA to Transfer the data in 1 burst with individual trigger * for each burst. */ channelHandle = DMA_DmaInitialize(BYTES_PER_BURST, REQUEST_PER_BURST, HI16(UPPER_SRC_ADDRESS), HI16(UPPER_DEST_ADDRESS)); /* This function allocates a TD for use with an initialized DMA channel */ tdChanA = CyDmaTdAllocate(); /* Configure the tdChanA to transfer 1 byte with no next TD */ CyDmaTdSetConfiguration(tdChanA, 1u, DMA_INVALID_TD, 0u); /* Set the source address as ADC_DelSig and the destination as * Filter Channel A. */ CyDmaTdSetAddress(tdChanA, LO16((uint32)ADC_DelSig_DEC_SAMP_PTR), LO16((uint32)Filter_STAGEAH_PTR)); /* Set tdChanA to be the initial TD associated with channelHandle */ CyDmaChSetInitialTd(channelHandle, tdChanA); /* Enable the DMA channel represented by channelHandle and preserve the TD */ CyDmaChEnable(channelHandle, 1u); uint8 DMA_1_Chan; uint8 DMA_1_TD[1]; DMA_1_Chan = DMA_1_DmaInitialize(DMA_1_BYTES_PER_BURST, DMA_1_REQUEST_PER_BURST, HI16(DMA_1_SRC_BASE), HI16(DMA_1_DST_BASE)); DMA_1_TD[0] = CyDmaTdAllocate(); CyDmaTdSetConfiguration(DMA_1_TD[0], buffersize, CY_DMA_DISABLE_TD, TD_INC_DST_ADR); CyDmaTdSetAddress(DMA_1_TD[0], LO16((uint32)Filter_HOLDA_PTR), LO16((uint32)buffer)); CyDmaChSetInitialTd(DMA_1_Chan, DMA_1_TD[0]); CyDmaChEnable(DMA_1_Chan, 1); /* Variable declarations for DMA_2 */ /* Move these variable declarations to the top of the function */ uint8 DMA_2_Chan; uint8 DMA_2_TD[1]; DMA_2_Chan = DMA_2_DmaInitialize(DMA_2_BYTES_PER_BURST, DMA_2_REQUEST_PER_BURST, HI16(DMA_2_SRC_BASE), HI16(DMA_2_DST_BASE)); DMA_2_TD[0] = CyDmaTdAllocate(); CyDmaTdSetConfiguration(DMA_2_TD[0], 1, CY_DMA_DISABLE_TD, 0); CyDmaTdSetAddress(DMA_2_TD[0], LO16((uint32)Filter_HOLDA_PTR), LO16((uint32)VDAC8_Data_PTR)); CyDmaChSetInitialTd(DMA_2_Chan, DMA_2_TD[0]); CyDmaChEnable(DMA_2_Chan, 1); }