/*! \brief set DMA memory base address \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel to set memory base address \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) \param[in] address: memory base address \param[out] none \retval none */ void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) { if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ DMA_WRONG_HANDLE } DMA_CHMADDR(dma_periph, channelx) = address; }
/*! \brief deinitialize DMA a channel registers \param[in] channelx: specify which DMA channel is deinitialized \arg DMA_CHx(x=0..6) \param[out] none \retval none */ void dma_deinit(dma_channel_enum channelx) { /* disable DMA a channel */ DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CHEN; /* reset DMA channel registers */ DMA_CHCTL(channelx) = DMA_CHCTL_RESET_VALUE; DMA_CHCNT(channelx) = DMA_CHCNT_RESET_VALUE; DMA_CHPADDR(channelx) = DMA_CHPADDR_RESET_VALUE; DMA_CHMADDR(channelx) = DMA_CHMADDR_RESET_VALUE; DMA_INTC |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE,channelx); }
/*! \brief deinitialize DMA a channel registers \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel is deinitialized \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) \param[out] none \retval none */ void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx) { if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ DMA_WRONG_HANDLE } /* disable DMA a channel */ DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN; /* reset DMA channel registers */ DMA_CHCTL(dma_periph, channelx) = DMA_CHCTL_RESET_VALUE; DMA_CHCNT(dma_periph, channelx) = DMA_CHCNT_RESET_VALUE; DMA_CHPADDR(dma_periph, channelx) = DMA_CHPADDR_RESET_VALUE; DMA_CHMADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE; DMA_INTC(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx); }
/*! \brief initialize DMA channel \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel is initialized \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) \param[in] init_struct: the data needed to initialize DMA channel periph_addr: peripheral base address periph_width: DMA_PERIPHERAL_WIDTH_8BIT, DMA_PERIPHERAL_WIDTH_16BIT, DMA_PERIPHERAL_WIDTH_32BIT periph_inc: DMA_PERIPH_INCREASE_ENABLE, DMA_PERIPH_INCREASE_DISABLE memory_addr: memory base address memory_width: DMA_MEMORY_WIDTH_8BIT, DMA_MEMORY_WIDTH_16BIT, DMA_MEMORY_WIDTH_32BIT memory_inc: DMA_MEMORY_INCREASE_ENABLE, DMA_MEMORY_INCREASE_DISABLE direction: DMA_PERIPHERAL_TO_MEMORY, DMA_MEMORY_TO_PERIPHERAL number: the number of remaining data to be transferred by the DMA priority: DMA_PRIORITY_LOW, DMA_PRIORITY_MEDIUM, DMA_PRIORITY_HIGH, DMA_PRIORITY_ULTRA_HIGH \param[out] none \retval none */ void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct init_struct) { uint32_t ctl; if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ DMA_WRONG_HANDLE } /* configure peripheral base address */ DMA_CHPADDR(dma_periph, channelx) = init_struct.periph_addr; /* configure memory base address */ DMA_CHMADDR(dma_periph, channelx) = init_struct.memory_addr; /* configure the number of remaining data to be transferred */ DMA_CHCNT(dma_periph, channelx) = (init_struct.number & DMA_CHANNEL_CNT_MASK); /* configure peripheral transfer width,memory transfer width, */ ctl = DMA_CHCTL(dma_periph, channelx); ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO); ctl |= (init_struct.periph_width | init_struct.memory_width | init_struct.priority); DMA_CHCTL(dma_periph, channelx) = ctl; /* configure peripheral increasing mode */ if(DMA_PERIPH_INCREASE_ENABLE == init_struct.periph_inc){ DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; }else{ DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; } /* configure memory increasing mode */ if(DMA_MEMORY_INCREASE_ENABLE == init_struct.memory_inc){ DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; }else{ DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; } /* configure the direction of data transfer */ if(DMA_PERIPHERAL_TO_MEMORY == init_struct.direction){ DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR; }else{ DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR; } }
/*! \brief set DMA Memory base address \param[in] channelx: specify which DMA channel to set Memory base address \arg DMA_CHx(x=0..6) \param[in] address: Memory base address \param[out] none \retval none */ void dma_memory_address_config(dma_channel_enum channelx,uint32_t address) { DMA_CHMADDR(channelx) = address; }