/**
* @brief 初始化DMA模块
* @param DMA_InitStruct :DMA初始化配置结构体，详见dma.h
* @retval None
*/
void DMA_Init(DMA_Init_t *Init)
{
/* enable DMA and DMAMUX clock */
SIM->SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
SIM->SCGC7 |= SIM_SCGC7_DMA_MASK;
/* disable chl first */
DMA0->DMA[Init->chl].DSR_BCR |= DMA_DSR_BCR_DONE_MASK;
DMA0->DMA[Init->chl].DCR &= ~DMA_DCR_ERQ_MASK;
/* dma chl source config */
DMAMUX0->CHCFG[Init->chl] = DMAMUX_CHCFG_SOURCE(Init->chlTrigSrc);
/* trigger mode */
switch(Init->trigSrcMod)
{
case kDMA_TrigSrc_Normal:
DMAMUX0->CHCFG[Init->chl] &= ~DMAMUX_CHCFG_TRIG_MASK;
break;
case kDMA_TrigSrc_Periodic:
DMAMUX0->CHCFG[Init->chl] |= DMAMUX_CHCFG_TRIG_MASK;
break;
default:
break;
}
DMA0->DMA[Init->chl].DCR = 0;
/* transfer bytes cnt */
DMA0->DMA[Init->chl].DSR_BCR = DMA_DSR_BCR_BCR(Init->transCnt);
/* source config */
DMA0->DMA[Init->chl].SAR = Init->sAddr;
DMA0->DMA[Init->chl].DCR |= DMA_DCR_SSIZE(Init->sDataWidth);
(Init->sAddrIsInc)?(DMA0->DMA[Init->chl].DCR |= DMA_DCR_SINC_MASK):(DMA0->DMA[Init->chl].DCR &= ~DMA_DCR_SINC_MASK);
DMA0->DMA[Init->chl].DCR |= DMA_DCR_SMOD(Init->sMod);
/* dest config */
DMA0->DMA[Init->chl].DAR = Init->dAddr;
DMA0->DMA[Init->chl].DCR |= DMA_DCR_DSIZE(Init->sDataWidth);
(Init->dAddrIsInc)?(DMA0->DMA[Init->chl].DCR |= DMA_DCR_DINC_MASK):(DMA0->DMA[Init->chl].DCR &= ~DMA_DCR_DINC_MASK);
DMA0->DMA[Init->chl].DCR |= DMA_DCR_DMOD(Init->dMod);
/* defaut: cycle steal */
DMA0->DMA[Init->chl].DCR |= DMA_DCR_CS_MASK;
/* defaut: enable auto disable req */
DMA0->DMA[Init->chl].DCR |= DMA_DCR_D_REQ_MASK;
/* enable chl */
DMAMUX0->CHCFG[Init->chl] |= DMAMUX_CHCFG_ENBL_MASK;
}
//======================================================================
//函数名称：DMA_Init()
//函数功能：初始化1个DMA模块
//输 入：DMA_Struct_TypeDef *DMA_Struct 需要初始化的DMA结构体地址
//输 出：无
//返 回： 0 : 成功
// -1 : 失败
// -2 : 传输字节数超出范围(<0x0FFFFF)
//======================================================================
int DMA_Init(DMA_Struct_TypeDef *DMA_Struct)
{
if ((*DMA_Struct).DMA_BytesCount > 0x0FFFFF)
return (-2);
const DMAMUX_x_TypeDef DMAMUX_x = DMAMUX_x_GET((*DMA_Struct).DMAMUX_Source);
switch (DMAMUX_x)
{
case DMAMUX0:
SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
break;
default:
return (-1);
}
SIM_SCGC7 |= SIM_SCGC7_DMA_MASK;
DMAMUX_CHCFG_REG(DMAMUXx[DMAMUX_x], (*DMA_Struct).DMA_CHn) = 0;
DMA_DCR_REG(DMAx[0], (*DMA_Struct).DMA_CHn) = 0;
DMA_DCR_REG(DMAx[0], (*DMA_Struct).DMA_CHn) &= ~DMA_DCR_DMOD_MASK;
const DMAMUX_SRC_TypeDef DMAMUX_SRC = DMAMUX_SRC_GET((*DMA_Struct).DMAMUX_Source);
if (DMAMUX_SRC == DMA_SoftTrig)
{
DMA_DCR_REG(DMAx[0], (*DMA_Struct).DMA_CHn) &= ~DMA_DCR_ERQ_MASK;
}
else
{
DMAMUX_CHCFG_REG(DMAMUXx[DMAMUX_x], (*DMA_Struct).DMA_CHn) |= DMAMUX_CHCFG_SOURCE(DMAMUX_SRC);
if ((*DMA_Struct).DMAMUX_Trig == DMA_Periodic)
DMAMUX_CHCFG_REG(DMAMUXx[DMAMUX_x], (*DMA_Struct).DMA_CHn) |= DMAMUX_CHCFG_TRIG_MASK;
else
DMAMUX_CHCFG_REG(DMAMUXx[DMAMUX_x], (*DMA_Struct).DMA_CHn) &= ~DMAMUX_CHCFG_TRIG_MASK;
}
//Source
DMA_SAR_REG(DMAx[0], (*DMA_Struct).DMA_CHn) =
DMA_SAR_SAR((*DMA_Struct).DMA_Source.DMA_Addr);
DMA_DCR_REG(DMAx[0], (*DMA_Struct).DMA_CHn) &= ~DMA_DCR_SSIZE_MASK;
DMA_DCR_REG(DMAx[0], (*DMA_Struct).DMA_CHn) |= DMA_DCR_SSIZE((*DMA_Struct).DMA_Source.Data_Size);
if ((*DMA_Struct).DMA_Source.Addr_INC == DMA_ADDR_INC)
DMA_DCR_REG(DMAx[0], (*DMA_Struct).DMA_CHn) |= DMA_DCR_SINC_MASK;
else
DMA_DCR_REG(DMAx[0], (*DMA_Struct).DMA_CHn) &= ~DMA_DCR_SINC_MASK;
DMA_DCR_REG(DMAx[0], (*DMA_Struct).DMA_CHn) &= ~DMA_DCR_SMOD_MASK;
DMA_DCR_REG(DMAx[0], (*DMA_Struct).DMA_CHn) |= DMA_DCR_SMOD((*DMA_Struct).DMA_Source.Addr_MOD);
//Destination
DMA_DAR_REG(DMAx[0], (*DMA_Struct).DMA_CHn) =
DMA_SAR_SAR((*DMA_Struct).DMA_Destination.DMA_Addr);
DMA_DCR_REG(DMAx[0], (*DMA_Struct).DMA_CHn) &= ~DMA_DCR_DSIZE_MASK;
DMA_DCR_REG(DMAx[0], (*DMA_Struct).DMA_CHn) |= DMA_DCR_DSIZE((*DMA_Struct).DMA_Destination.Data_Size);
if ((*DMA_Struct).DMA_Destination.Addr_INC == DMA_ADDR_INC)
DMA_DCR_REG(DMAx[0], (*DMA_Struct).DMA_CHn) |= DMA_DCR_DINC_MASK;
else
DMA_DCR_REG(DMAx[0], (*DMA_Struct).DMA_CHn) &= ~DMA_DCR_DINC_MASK;
DMA_DCR_REG(DMAx[0], (*DMA_Struct).DMA_CHn) |= DMA_DCR_DMOD((*DMA_Struct).DMA_Destination.Addr_MOD);
DMA_DSR_BCR_REG(DMAx[0], (*DMA_Struct).DMA_CHn) &= ~DMA_DSR_BCR_BCR_MASK;
DMA_DSR_BCR_REG(DMAx[0], (*DMA_Struct).DMA_CHn) |= DMA_DSR_BCR_BCR((*DMA_Struct).DMA_BytesCount);
if ((*DMA_Struct).DMA_CycleSteal == DMA_CycleSteal)
DMA_DCR_REG(DMAx[0], (*DMA_Struct).DMA_CHn) &= ~DMA_DCR_CS_MASK;
else
DMA_DCR_REG(DMAx[0], (*DMA_Struct).DMA_CHn) |= DMA_DCR_CS_MASK;
if (DMAMUX_SRC == DMA_SoftTrig)
DMA_DCR_REG(DMAx[0], (*DMA_Struct).DMA_CHn) |= DMA_DCR_START_MASK;
else
DMA_DCR_REG(DMAx[0], (*DMA_Struct).DMA_CHn) |= DMA_DCR_ERQ_MASK;
//DMAMUX_CHCFG_REG(DMAMUXx[DMAMUX_x], (*DMA_Struct).DMA_CHx) |= DMAMUX_CHCFG_ENBL_MASK;
return (0);
}
void DMA1_Init(void)
{
APP_TRACE("start 4.1\n\r");
/* SIM_SCGC7: DMA=1 */
SIM_SCGC7 |= SIM_SCGC7_DMA_MASK;
/* SIM_SCGC6: DMAMUX=1 */
SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
/* DMAMUX0_CHCFG0: ENBL=0,TRIG=0,SOURCE=0 */
DMAMUX0_CHCFG0 = DMAMUX_CHCFG_SOURCE(0x00);
/* DMAMUX0_CHCFG1: ENBL=0,TRIG=0,SOURCE=0 */
DMAMUX0_CHCFG1 = DMAMUX_CHCFG_SOURCE(0x00);
/* DMAMUX0_CHCFG2: ENBL=0,TRIG=0,SOURCE=0 */
DMAMUX0_CHCFG2 = DMAMUX_CHCFG_SOURCE(0x00);
/* DMAMUX0_CHCFG3: ENBL=0,TRIG=0,SOURCE=0 */
DMAMUX0_CHCFG3 = DMAMUX_CHCFG_SOURCE(0x00);
/* DMA_DSR_BCR0: DONE=1 */
DMA_DSR_BCR0 |= DMA_DSR_BCR_DONE_MASK;
/* DMA_DSR_BCR1: DONE=1 */
DMA_DSR_BCR1 |= DMA_DSR_BCR_DONE_MASK;
/* DMA_DSR_BCR2: DONE=1 */
DMA_DSR_BCR2 |= DMA_DSR_BCR_DONE_MASK;
/* DMA_SAR0 = (uint32_t)&ADC0_RA */
DMA_SAR0 = (uint32_t)((uint32_t)&ADC0_RA);
/* DMA_SAR1 = 0 */
DMA_SAR1 = (uint32_t)(0);
/* DMA_SAR2 = 0 */
DMA_SAR2 = (uint32_t)(0);
/* DMA_DAR1 = &ADC0_CFG2 */
DMA_DAR1 = (uint32_t)(&ADC0_CFG2);
/* DMA_DAR2 = &ADC0_SC1A */
DMA_DAR2 = (uint32_t)(&ADC0_SC1A);
/* DMA_DSR_BCR0: ??=0,CE=0,BES=0,BED=0,??=0,REQ=0,BSY=0,DONE=0,BCR=0x10 */
DMA_DSR_BCR0 = DMA_DSR_BCR_BCR(0x10);
/* DMA_DSR_BCR1: ??=0,CE=0,BES=0,BED=0,??=0,REQ=0,BSY=0,DONE=0,BCR=8 */
DMA_DSR_BCR1 = DMA_DSR_BCR_BCR(0x08);
/* DMA_DSR_BCR2: ??=0,CE=0,BES=0,BED=0,??=0,REQ=0,BSY=0,DONE=0,BCR=8 */
DMA_DSR_BCR2 = DMA_DSR_BCR_BCR(0x08);
APP_TRACE("start 4.2\n\r");
/* DMA_DCR0: EINT=1,ERQ=1,CS=1,AA=0,??=0,??=0,??=0,??=0,EADREQ=1,SINC=0,SSIZE=2,DINC=1,DSIZE=2,START=0,SMOD=0,DMOD=0,D_REQ=0,??=0,LINKCC=2,LCH1=1,LCH2=0 */
DMA_DCR0 = DMA_DCR_EINT_MASK |
DMA_DCR_ERQ_MASK |
DMA_DCR_CS_MASK |
DMA_DCR_EADREQ_MASK |
DMA_DCR_SSIZE(0x02) |
DMA_DCR_DINC_MASK |
DMA_DCR_DSIZE(0x02) |
DMA_DCR_SMOD(0x00) |
DMA_DCR_DMOD(0x00) |
DMA_DCR_LINKCC(0x02) |
DMA_DCR_LCH1(0x01) |
DMA_DCR_LCH2(0x00);
/* DMA_DCR1: EINT=0,ERQ=1,CS=1,AA=0,??=0,??=0,??=0,??=0,EADREQ=1,SINC=1,SSIZE=1,DINC=0,DSIZE=1,START=0,SMOD=0,DMOD=0,D_REQ=1,??=0,LINKCC=2,LCH1=2,LCH2=0 */
DMA_DCR1 = DMA_DCR_ERQ_MASK |
DMA_DCR_CS_MASK |
DMA_DCR_EADREQ_MASK |
DMA_DCR_SINC_MASK |
DMA_DCR_SSIZE(0x01) |
DMA_DCR_DSIZE(0x01) |
DMA_DCR_SMOD(0x00) |
DMA_DCR_DMOD(0x00) |
DMA_DCR_D_REQ_MASK |
DMA_DCR_LINKCC(0x02) |
DMA_DCR_LCH1(0x02) |
DMA_DCR_LCH2(0x00);
/* DMA_DCR2: EINT=0,ERQ=1,CS=1,AA=0,??=0,??=0,??=0,??=0,EADREQ=1,SINC=1,SSIZE=1,DINC=0,DSIZE=1,START=0,SMOD=0,DMOD=0,D_REQ=1,??=0,LINKCC=0,LCH1=0,LCH2=0 */
APP_TRACE("start 4.3\n\r");
DMA_DCR2 = DMA_DCR_ERQ_MASK |
DMA_DCR_CS_MASK |
DMA_DCR_EADREQ_MASK |
DMA_DCR_SINC_MASK |
DMA_DCR_SSIZE(0x01) |
DMA_DCR_DSIZE(0x01) |
DMA_DCR_SMOD(0x00) |
DMA_DCR_DMOD(0x00) |
DMA_DCR_D_REQ_MASK |
DMA_DCR_LINKCC(0x00) |
DMA_DCR_LCH1(0x00) |
DMA_DCR_LCH2(0x00);
/* DMAMUX0_CHCFG0: ENBL=1,TRIG=0,SOURCE=0x28 */
DMAMUX0_CHCFG0 = (DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(0x28));
/* DMAMUX0_CHCFG1: ENBL=1,TRIG=0,SOURCE=0 */
DMAMUX0_CHCFG1 = (DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(0x00));
/* DMAMUX0_CHCFG2: ENBL=1,SOURCE=0 */
APP_TRACE("start 4.4\n\r");
DMAMUX0_CHCFG2 = (uint8_t)((DMAMUX0_CHCFG2 & (uint8_t)~(uint8_t)(
DMAMUX_CHCFG_SOURCE(0x3F)
)) | (uint8_t)(
DMAMUX_CHCFG_ENBL_MASK
));
_int_install_isr(LDD_ivIndex_INT_DMA0, adc0_isr, NULL);
enable_irq(0) ; // ready for this interrupt.
// set_irq_priority(0, 2);
APP_TRACE("start 4.5\n\r");
}
