static void dma8237_write(int which, offs_t offset, UINT8 data) { int channel; dma8237_verify(which); offset &= 0x0F; switch(offset) { case 0: case 2: case 4: case 6: /* DMA address register */ if (dma[which].msb) dma[which].chan[offset / 2].address |= ((UINT16) data) << 8; else dma[which].chan[offset / 2].address = data; prepare_msb_flip(which); break; case 1: case 3: case 5: case 7: /* DMA count register */ if (dma[which].msb) dma[which].chan[offset / 2].count |= ((UINT16) data) << 8; else dma[which].chan[offset / 2].count = data; prepare_msb_flip(which); break; case 8: /* DMA command register */ dma[which].command = data; break; case 10: /* DMA mask register */ channel = DMA_MODE_CHANNEL(data); if (data & 0x04) dma[which].mask |= 0x11 << channel; else dma[which].mask &= ~(0x11 << channel); break; case 11: /* DMA mode register */ channel = DMA_MODE_CHANNEL(data); dma[which].chan[channel].mode = data; break; case 12: /* DMA clear byte pointer flip-flop */ dma[which].temp = data; dma[which].msb = 0; break; case 13: /* DMA master clear */ dma[which].msb = 0; break; case 14: /* DMA clear mask register */ dma[which].mask &= ~data; dma8237_update_status(which); break; case 15: /* DMA write mask register */ dma[which].mask |= data; break; } }
WRITE8_DEVICE_HANDLER_TRAMPOLINE(i8237, i8237_w) { offset &= 0x0F; // logerror("i8237_w: offset = %02x, data = %02x\n", offset, data ); switch(offset) { case 0: case 2: case 4: case 6: { /* DMA address register */ int channel = offset / 2; if (m_msb) { m_chan[channel].m_base_address = ( m_chan[channel].m_base_address & 0x00FF ) | ( data << 8 ); m_chan[channel].m_address = ( m_chan[channel].m_address & 0x00FF ) | ( data << 8 ); } else { m_chan[channel].m_base_address = ( m_chan[channel].m_base_address & 0xFF00 ) | data; m_chan[channel].m_address = ( m_chan[channel].m_address & 0xFF00 ) | data; } m_msb ^= 1; break; } case 1: case 3: case 5: case 7: { /* DMA count register */ int channel = offset / 2; if (m_msb) { m_chan[channel].m_base_count = ( m_chan[channel].m_base_count & 0x00FF ) | ( data << 8 ); m_chan[channel].m_count = ( m_chan[channel].m_count & 0x00FF ) | ( data << 8 ); } else { m_chan[channel].m_base_count = ( m_chan[channel].m_base_count & 0xFF00 ) | data; m_chan[channel].m_count = ( m_chan[channel].m_count & 0xFF00 ) | data; } m_msb ^= 1; break; } case 8: /* DMA command register */ m_command = data; m_timer->enable( ( m_command & 0x04 ) ? 0 : 1 ); break; case 9: { /* DMA request register */ int channel = DMA_MODE_CHANNEL(data); if ( data & 0x04 ) { m_drq |= 0x01 << channel; m_timer->enable( ( m_command & 0x04 ) ? 0 : 1 ); } else { m_status &= ~ ( 0x10 << channel ); m_drq &= ~ ( 0x01 << channel ); } break; } case 10: { /* DMA mask register */ int channel = DMA_MODE_CHANNEL(data); if (data & 0x04) { m_mask |= 0x11 << channel; } else { m_mask &= ~(0x11 << channel); } break; } case 11: { /* DMA mode register */ int channel = DMA_MODE_CHANNEL(data); m_chan[channel].m_mode = data; /* Apparently mode writes also clear the TC bit(?) */ m_status &= ~ ( 1 << channel ); break; } case 12: /* DMA clear byte pointer flip-flop */ m_temp = data; m_msb = 0; break; case 13: /* DMA master clear */ m_msb = 0; m_mask = 0x0f; m_state = DMA8237_SI; m_status &= 0xF0; m_temp = 0; break; case 14: /* DMA clear mask register */ m_mask &= ~data; m_mask = 0; break; case 15: /* DMA write mask register */ m_mask = data & 0x0f; break; } }