bool PIOS_Hsync_ISR() {
if(dev_cfg->hsync->pin.gpio->IDR & dev_cfg->hsync->pin.init.GPIO_Pin) {
//rising
if(gLineType == LINE_TYPE_GRAPHICS)
{
// Activate new line
DMA_Cmd(dev_cfg->level.dma.tx.channel, ENABLE);
DMA_Cmd(dev_cfg->mask.dma.tx.channel, ENABLE);
}
} else {
//falling
gLineType = LINE_TYPE_UNKNOWN; // Default case
gActiveLine++;
if ((gActiveLine >= GRAPHICS_LINE) && (gActiveLine < (GRAPHICS_LINE + GRAPHICS_HEIGHT))) {
gLineType = LINE_TYPE_GRAPHICS;
gActivePixmapLine = (gActiveLine - GRAPHICS_LINE);
line = gActivePixmapLine*GRAPHICS_WIDTH;
}
if(gLineType == LINE_TYPE_GRAPHICS)
{
// Load new line
DMA_Cmd(dev_cfg->mask.dma.tx.channel, DISABLE);
DMA_Cmd(dev_cfg->level.dma.tx.channel, DISABLE);
DMA_MemoryTargetConfig(dev_cfg->level.dma.tx.channel,(uint32_t)&disp_buffer_level[line],DMA_Memory_0);
DMA_MemoryTargetConfig(dev_cfg->mask.dma.tx.channel,(uint32_t)&disp_buffer_mask[line],DMA_Memory_0);
DMA_SetCurrDataCounter(dev_cfg->level.dma.tx.channel,BUFFER_LINE_LENGTH);
DMA_SetCurrDataCounter(dev_cfg->mask.dma.tx.channel,BUFFER_LINE_LENGTH);
}
}
return false;
}
void WS2812B_Send_Buffer(void)
{
WS2812B_TC = 0;
DMA_ClearFlag(DMA1_FLAG_TC2 | DMA1_FLAG_HT2 | DMA1_FLAG_GL2 | DMA1_FLAG_TE2);
DMA_ClearFlag(DMA1_FLAG_TC3 | DMA1_FLAG_HT3 | DMA1_FLAG_GL3 | DMA1_FLAG_TE3);
DMA_ClearFlag(DMA1_FLAG_TC4 | DMA1_FLAG_HT4 | DMA1_FLAG_GL4 | DMA1_FLAG_TE4);
DMA_SetCurrDataCounter(DMA1_Channel2, WS2812B_BUFFER_SIZE);
DMA_SetCurrDataCounter(DMA1_Channel3, WS2812B_BUFFER_SIZE);
DMA_SetCurrDataCounter(DMA1_Channel4, WS2812B_BUFFER_SIZE);
TIM3->SR = 0;
DMA_Cmd(DMA1_Channel2, ENABLE);
DMA_Cmd(DMA1_Channel3, ENABLE);
DMA_Cmd(DMA1_Channel4, ENABLE);
TIM_DMACmd(TIM3, TIM_DMA_CC1, ENABLE);
TIM_DMACmd(TIM3, TIM_DMA_CC3, ENABLE);
TIM_DMACmd(TIM3, TIM_DMA_Update, ENABLE);
TIM_SetCounter(TIM3, 10);
TIM_Cmd(TIM3, ENABLE);
}
/**
* Prepare the system to watch for a HSYNC pulse to trigger the pixel
* clock and clock out the next line
*/
static void prepare_line(uint32_t line_num)
{
if (line_num < GRAPHICS_HEIGHT) {
uint32_t buf_offset = line_num * GRAPHICS_WIDTH;
dev_cfg->pixel_timer.timer->CNT = dc;
DMA_ClearFlag(dev_cfg->mask.dma.tx.channel, DMA_FLAG_TCIF7 | DMA_FLAG_HTIF7 | DMA_FLAG_FEIF7 | DMA_FLAG_TEIF7);
DMA_ClearFlag(dev_cfg->level.dma.tx.channel, DMA_FLAG_FEIF5 | DMA_FLAG_TEIF5);
// Load new line
DMA_MemoryTargetConfig(dev_cfg->level.dma.tx.channel, (uint32_t)&disp_buffer_level[buf_offset], DMA_Memory_0);
DMA_MemoryTargetConfig(dev_cfg->mask.dma.tx.channel, (uint32_t)&disp_buffer_mask[buf_offset], DMA_Memory_0);
// Enable DMA, Slave first
DMA_SetCurrDataCounter(dev_cfg->level.dma.tx.channel, BUFFER_LINE_LENGTH);
DMA_SetCurrDataCounter(dev_cfg->mask.dma.tx.channel, BUFFER_LINE_LENGTH);
SPI_Cmd(dev_cfg->level.regs, ENABLE);
SPI_Cmd(dev_cfg->mask.regs, ENABLE);
/* Enable SPI interrupts to DMA */
SPI_I2S_DMACmd(dev_cfg->mask.regs, SPI_I2S_DMAReq_Tx, ENABLE);
SPI_I2S_DMACmd(dev_cfg->level.regs, SPI_I2S_DMAReq_Tx, ENABLE);
DMA_Cmd(dev_cfg->level.dma.tx.channel, ENABLE);
DMA_Cmd(dev_cfg->mask.dma.tx.channel, ENABLE);
}
reset_hsync_timers();
}
void Serial::sendBuffer() {
//if no data
if (txBufPos < 1)
return;
if (thisPort == RS485) {
RS485_EnableTransmit(true); //will be set to false at transfer complete ISR
//Transmission Complete flag.
USART_ClearFlag(USART1, USART_FLAG_TC);
DMA_Cmd(DMA2_Stream7, DISABLE);
DMA_SetCurrDataCounter(DMA2_Stream7, txBufPos);
DMA_ClearFlag(DMA2_Stream7, DMA_FLAG_TCIF7);
DMA_Cmd(DMA2_Stream7, ENABLE);
}
else if (thisPort == DSC) {
//Transmission Complete flag.
USART_ClearFlag(USART2, USART_FLAG_TC);
DMA_Cmd(DMA1_Stream6, DISABLE);
DMA_SetCurrDataCounter(DMA1_Stream6, txBufPos);
DMA_ClearFlag(DMA1_Stream6, DMA_FLAG_TCIF6);
DMA_Cmd(DMA1_Stream6, ENABLE);
}
txBufPos = 0;
}
void startSpi(uint16_t number)
{
DMA_SetCurrDataCounter(DMA1_Stream3, number);
DMA_SetCurrDataCounter(DMA1_Stream4, number);
csOn();
spi2Work = 1;
DMA_Cmd(DMA1_Stream3, ENABLE);
DMA_Cmd(DMA1_Stream4, ENABLE);
}
//-----------------------------------------------------------------
void StartSPI(uint8_t number)
{
DMA_SetCurrDataCounter(DMA2_Stream0, number);
DMA_SetCurrDataCounter(DMA2_Stream3, number);
SPI_work = 1;
CS_ON();
DMA_Cmd(DMA2_Stream0, ENABLE);
DMA_Cmd(DMA2_Stream3, ENABLE);
}
static void AdcStartPre34()
{
DMA_InitTypeDef DMA_InitStructure;
DMA_DeInit(DMA2_Channel5);
DMA_DeInit(DMA2_Channel2);
DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&ADC3->DR;
DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)&g_resultBuffer[0];
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
DMA_InitStructure.DMA_BufferSize = g_ResultBufferSize;
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
DMA_InitStructure.DMA_Priority = DMA_Priority_High;
DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
DMA_Init(DMA2_Channel5, &DMA_InitStructure);
DMA_Cmd(DMA2_Channel5, ENABLE);
DMA_ITConfig(DMA2_Channel5, DMA_IT_TC, ENABLE);
DMA_SetCurrDataCounter(DMA2_Channel5, 0);
DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&ADC4->DR;
DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)&g_resultBuffer[g_ResultBufferSize/2];
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
DMA_InitStructure.DMA_BufferSize = g_ResultBufferSize;
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
DMA_InitStructure.DMA_Priority = DMA_Priority_High;
DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
DMA_Init(DMA2_Channel2, &DMA_InitStructure);
DMA_Cmd(DMA2_Channel2, ENABLE);
DMA_ITConfig(DMA2_Channel2, DMA_IT_TC, ENABLE);
DMA_SetCurrDataCounter(DMA2_Channel2, 0);
uint8_t sample_ticks = DacSampleTicks()<72?ADC_SampleTime_7Cycles5:ADC_SampleTime_19Cycles5;
//uint8_t sample_ticks = ADC_SampleTime_601Cycles5;
ADC_RegularChannelConfig(ADC3, ADC_Channel_1/*PB1*/, 1, sample_ticks);
ADC_RegularChannelConfig(ADC4, ADC_Channel_1/*PE14*/, 1, sample_ticks);
ADC_Cmd(ADC3, ENABLE);
ADC_Cmd(ADC4, ENABLE);
ADC_DMACmd(ADC3, ENABLE);
ADC_DMACmd(ADC4, ENABLE);
g_adcStatus = 1;
g_adc_cycles = 0;
}
void uarts_sport_irq_handler_callback(void)
{
uint32_t temp = 0;
uint16_t len = 0;
uint8_t RxBuffer[S_PORT_RX_BUFF_LEN];
if(USART_GetITStatus(USART_S_PORT, USART_IT_IDLE) != RESET)
{
DMA_Cmd(USART_S_PORT_Rx_DMA_STREAM,DISABLE);
temp = USART_S_PORT->SR;
temp = USART_S_PORT->DR; //清USART_IT_IDLE标志
temp = temp;
//接收字节数
len = S_PORT_RX_BUFF_LEN - DMA_GetCurrDataCounter(USART_S_PORT_Rx_DMA_STREAM);
memcpy(RxBuffer, Sport_RxBuffer, len);
//设置传输数据长度
DMA_SetCurrDataCounter(USART_S_PORT_Rx_DMA_STREAM,S_PORT_RX_BUFF_LEN);
//打开DMA
DMA_Cmd(USART_S_PORT_Rx_DMA_STREAM,ENABLE);
uarts_sport_irq_handler_cb_hook(RxBuffer, len);
}
}
void ws2811LedStripDMAEnable(void)
{
DMA_SetCurrDataCounter(DMA1_Channel3, WS2811_DMA_BUFFER_SIZE); // load number of bytes to be transferred
TIM_SetCounter(TIM16, 0);
TIM_Cmd(TIM16, ENABLE);
DMA_Cmd(DMA1_Channel3, ENABLE);
}
void DMA_Enable(void)
{
DMA_Cmd(DMA1_Channel2, DISABLE ); //??USART1 TX DMA1 ??????
DMA_SetCurrDataCounter(DMA1_Channel2,4);//DMA???DMA?????
DMA_Cmd(DMA1_Channel2, ENABLE); //??USART1 TX DMA1 ??????
}
void pwmWriteDigital(uint8_t index, uint16_t value)
{
if (!pwmMotorsEnabled) {
return;
}
motorDmaOutput_t * const motor = &dmaMotors[index];
if (!motor->timerHardware->dmaChannel) {
return;
}
uint16_t packet = (value << 1) | (motor->requestTelemetry ? 1 : 0);
motor->requestTelemetry = false; // reset telemetry request to make sure it's triggered only once in a row
// compute checksum
int csum = 0;
int csum_data = packet;
for (int i = 0; i < 3; i++) {
csum ^= csum_data; // xor data by nibbles
csum_data >>= 4;
}
csum &= 0xf;
// append checksum
packet = (packet << 4) | csum;
// generate pulses for whole packet
for (int i = 0; i < 16; i++) {
motor->dmaBuffer[i] = (packet & 0x8000) ? MOTOR_BIT_1 : MOTOR_BIT_0; // MSB first
packet <<= 1;
}
DMA_SetCurrDataCounter(motor->timerHardware->dmaChannel, MOTOR_DMA_BUFFER_SIZE);
DMA_Cmd(motor->timerHardware->dmaChannel, ENABLE);
}
/**
* ISR for USART6 RX DMA Stream Interrupt
*/
void DMA2_Stream2_IRQHandler()
{
// Stream2 transfer complete interrupt?
if(DMA_GetITStatus(DMA2_Stream2,DMA_IT_TCIF2))
{
// clear pending interrupt
DMA_ClearFlag(DMA2_Stream2,DMA_IT_TCIF2);
UART6_Str.Recv_Len = UART6_MAX_RECV_LEN -DMA_GetCurrDataCounter(DMA2_Stream2);
if(UART6_Str.Recv_Len > 0)
{
UART6_Str.data = UART6_Recv_Buf[UART6_User_Buf_No];
UART6_Str.Recv_Flag = 1;
UART6_User_Buf_No++;
if(UART6_User_Buf_No >= UART6_MAX_ARR)
UART6_User_Buf_No = 0;
}
DMA_ClearFlag(DMA2_Stream2,DMA_FLAG_DMEIF2 | DMA_FLAG_FEIF2 | DMA_FLAG_TCIF2 | DMA_FLAG_TEIF2 | DMA_FLAG_HTIF2);//清标志
DMA_SetCurrDataCounter(DMA2_Stream2,UART6_MAX_RECV_LEN);//重装填
//USART6_Rcv_Str.Free_Buf_No = DMA_GetCurrentMemoryTarget(DMA2_Stream2);
UART6_DMA_RX.DMA_Memory0BaseAddr = (u32)&UART6_Recv_Buf[UART6_User_Buf_No];
DMA_Init(DMA2_Stream2, &UART6_DMA_RX);
}
DMA_ClearFlag(DMA2_Stream2,DMA_IT_TEIF2 | DMA_FLAG_HTIF2);
}
//return true if success
bool Serial::armReceiveCompleteEvent( bool on, u16 rxlen )
{
//NA in this port
if(thisPort==RS485) return false;
if(rxlen>RXBUFSIZE) return false;
if(on)
{
rxPacketLen = rxlen;
rxBufPos=0;
//Transmission Complete flag.
DMA_ITConfig(DMA1_Stream5, DMA_IT_TC, DISABLE);
DMA_Cmd(DMA1_Stream5, DISABLE);
DMA_ClearITPendingBit( DMA1_Stream5, DMA_IT_TCIF5 );
DMA_SetCurrDataCounter(DMA1_Stream5, rxlen);
DMA_ClearFlag(DMA1_Stream5, DMA_FLAG_TCIF5);
DMA_Cmd(DMA1_Stream5, ENABLE);
DMA_ITConfig(DMA1_Stream5, DMA_IT_TC, ENABLE);
}
else
{
DMA_ITConfig(DMA1_Stream5, DMA_IT_TC, DISABLE);
}
return true;
}
void USART2_IRQHandler(void) //����2 �жϷ������
{
uint8_t tmp;
task * uart2_task;
struct uart_buffer *uart2_buf;
uint16_t length = 0;
if(USART_GetITStatus(USART2, USART_IT_IDLE) != RESET)
{
tmp = USART_ReceiveData(USART2);
DMA_Cmd(DMA1_Channel6, DISABLE); // close DMA
length = USART_RECEIVED_MAX_LEN - DMA_GetCurrDataCounter(DMA1_Channel6);
//printf("uart2 dma2 length:%d\n", length);
uart2_buf = (struct uart_buffer*)malloc(sizeof(struct uart_buffer));
uart2_buf->buf = (uint8_t*)malloc(length + 1);
uart2_buf->length = length + 1;
memcpy(uart2_buf->buf, g_usart2_received_buf, length);
uart2_buf->buf[length] = 0;
uart2_task = new_task();
uart2_task->handler = module_data_handler;
uart2_task->pdata = uart2_buf;
add_task(uart2_task);
// set data length of transmission
DMA_SetCurrDataCounter(DMA1_Channel6, USART_RECEIVED_MAX_LEN);
// open DMA
DMA_Cmd(DMA1_Channel6,ENABLE);
}
if(USART_GetITStatus(USART2, USART_IT_TXE) != RESET) //�����Ϊ�˱���STM32 USART ��һ���ֽڷ�����ȥ��BUG
{
USART_ITConfig(USART2, USART_IT_TXE, DISABLE); //��ֹ�����������жϣ�
}
}
void TUartDMA() {
sprintf(serialPort3->txBuf, "hello\r\n");
int length = strlen(serialPort3->txBuf);
DMA_SetCurrDataCounter(USARTx_TX_DMA_STREAM, length);
DMA_Cmd(USARTx_TX_DMA_STREAM, ENABLE);
USART_DMACmd(USARTx, USART_DMAReq_Tx, ENABLE);
}
void transponderIrDMAEnable(void)
{
DMA_SetCurrDataCounter(TRANSPONDER_DMA_CHANNEL, TRANSPONDER_DMA_BUFFER_SIZE); // load number of bytes to be transferred
TIM_SetCounter(TRANSPONDER_TIMER, 0);
TIM_Cmd(TRANSPONDER_TIMER, ENABLE);
DMA_Cmd(TRANSPONDER_DMA_CHANNEL, ENABLE);
}
void UART_DMA_Rx_Enable(void)
{
USART_DMACmd(USART1, USART_DMAReq_Rx, ENABLE);
DMA_Cmd(DMA1_Channel5, DISABLE );
DMA_SetCurrDataCounter(DMA1_Channel5,UART_RX_BUFFER_SIZE);
DMA_Cmd(DMA1_Channel5, ENABLE);
}
/* This function sends data bytes out to a string of WS2812s
* The first argument is a pointer to the first RGB triplet to be sent
* The seconds argument is the number of LEDs in the chain
*
* This will result in the RGB triplet passed by argument 1 being sent to
* the LED that is the furthest away from the controller (the point where
* data is injected into the chain)
*/
void WS2812_send2(const uint8_t (*color)[3], const uint16_t _len)
{
int i, j;
uint8_t led;
uint16_t memaddr;
uint16_t buffersize;
uint16_t len = _len;
// Byte order mapping. 0 is red, 1 is green, 2 is blue
const uint8_t pix_map[3] = {0, 2, 1};
buffersize = (len*24); // number of bytes needed is #LEDs * 24 bytes + 42 trailing bytes
memaddr = 0; // reset buffer memory index
led = 0; // reset led index
// fill transmit buffer with correct compare values to achieve
// correct pulse widths according to color values
while (len)
{
for (i = 0; i < 3; i++)
{
for (j = 0; j < 8; j++) // GREEN data
{
if ( (color[led][pix_map[i]]<<j) & 0x80 ) // data sent MSB first, j = 0 is MSB j = 7 is LSB
{
LED_BYTE_Buffer[memaddr] = TIM_COMPARE_LOGIC_1; // compare value for logical 1
}
else
{
LED_BYTE_Buffer[memaddr] = TIM_COMPARE_LOGIC_0; // compare value for logical 0
}
memaddr++;
}
}
led++;
len--;
}
LED_BYTE_Buffer[memaddr++] = 0;
LED_BYTE_Buffer[memaddr++] = 0;
DMA_SetCurrDataCounter(DMA_STREAM, buffersize + 2); // load number of bytes to be transferred
// PAP: Clear the timer's counter and set the compare value to 0. This
// sets the output low on start and gives us a full cycle to set up DMA.
TIM_SetCounter(PWM_TIMER, 0);
TIM_SetCompare1(PWM_TIMER, 0);
TIM_Cmd(PWM_TIMER, ENABLE); // enable Timer 3
// PAP: Start DMA transfer after starting the timer. This prevents the
// DMA/PWM from dropping the first bit.
DMA_Cmd(DMA_STREAM, ENABLE); // enable DMA channel 6
while(!DMA_GetFlagStatus(DMA_STREAM, DMA_TCIF)); // wait until transfer complete
TIM_Cmd(PWM_TIMER, DISABLE); // disable Timer 3
DMA_Cmd(DMA_STREAM, DISABLE); // disable DMA channel 6
DMA_ClearFlag(DMA_STREAM, DMA_TCIF); // clear DMA1 Channel 6 transfer complete flag
}
void ws2811LedStripDMAEnable(void)
{
if (!ws2811Initialised)
return;
DMA_SetCurrDataCounter(DMA1_Channel6, WS2811_DMA_BUFFER_SIZE); // load number of bytes to be transferred
TIM_SetCounter(TIM3, 0);
TIM_Cmd(TIM3, ENABLE);
DMA_Cmd(DMA1_Channel6, ENABLE);
}
//not working!!!!!!!!!!!
void UART_PutChar(char data) {
while (!IsUsartTransferComplete(serialPort3)) {
}
sprintf(serialPort3->txBuf, &data);
u16 retCounter = DMA_GetCurrDataCounter(USARTx_TX_DMA_STREAM);
DMA_Cmd(USARTx_TX_DMA_STREAM, DISABLE);
DMA_SetCurrDataCounter(USARTx_TX_DMA_STREAM,
retCounter + 1);
DMA_Cmd(USARTx_TX_DMA_STREAM, ENABLE);
}
//----------------------------------------------------------------------------
void DMA1_Stream1_IRQHandler(void) //-- UART3 Rx
{
//--- Reload DMA - urgent
DMA_ClearFlag(DMA1_Stream1, DMA_FLAG_TCIF1);
#ifdef USE_USART3
DMA_Cmd(DMA1_Stream1, DISABLE);
DMA_SetCurrDataCounter(DMA1_Stream1, USART3_RX_BUF_SIZE);
DMA_Cmd(DMA1_Stream1, ENABLE);
#endif
tn_int_exit();
}
//----------------------------------------------------------------------------
void DMA2_Stream5_IRQHandler(void) //-- UART1 Rx
{
//--- Reload DMA - urgent
DMA_ClearFlag(DMA2_Stream5, DMA_FLAG_TCIF5);
#ifdef USE_USART1
DMA_Cmd(DMA2_Stream5, DISABLE);
DMA_SetCurrDataCounter(DMA2_Stream5, USART1_RX_BUF_SIZE);
DMA_Cmd(DMA2_Stream5, ENABLE);
#endif
tn_int_exit();
}
void I2C_DMA_Read(u8 slaveAddr, u8 readAddr)
{
/* Disable DMA channel*/
DMA_Cmd(DMA1_Channel7, DISABLE);
/* Set current data number again to 14 for MPu6050, only possible after disabling the DMA channel */
DMA_SetCurrDataCounter(DMA1_Channel7, 14);
/* While the bus is busy */
while(I2C_GetFlagStatus(MPU6050_I2C, I2C_FLAG_BUSY));
/* Enable DMA NACK automatic generation */
I2C_DMALastTransferCmd(MPU6050_I2C, ENABLE); //Note this one, very important
/* Send START condition */
I2C_GenerateSTART(MPU6050_I2C, ENABLE);
/* Test on EV5 and clear it */
while(!I2C_CheckEvent(MPU6050_I2C, I2C_EVENT_MASTER_MODE_SELECT));
/* Send MPU6050 address for write */
I2C_Send7bitAddress(MPU6050_I2C, slaveAddr, I2C_Direction_Transmitter);
/* Test on EV6 and clear it */
while(!I2C_CheckEvent(MPU6050_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED));
/* Clear EV6 by setting again the PE bit */
I2C_Cmd(MPU6050_I2C, ENABLE);
/* Send the MPU6050's internal address to write to */
I2C_SendData(MPU6050_I2C, readAddr);
/* Test on EV8 and clear it */
while(!I2C_CheckEvent(MPU6050_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTED));
/* Send STRAT condition a second time */
I2C_GenerateSTART(MPU6050_I2C, ENABLE);
/* Test on EV5 and clear it */
while(!I2C_CheckEvent(MPU6050_I2C, I2C_EVENT_MASTER_MODE_SELECT));
/* Send MPU6050 address for read */
I2C_Send7bitAddress(MPU6050_I2C, slaveAddr, I2C_Direction_Receiver);
/* Test on EV6 and clear it */
while(!I2C_CheckEvent(MPU6050_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED));
/* Start DMA to receive data from I2C */
DMA_Cmd(DMA1_Channel7, ENABLE);
I2C_DMACmd(MPU6050_I2C, ENABLE);
// When the data transmission is complete, it will automatically jump to DMA interrupt routine to finish the rest.
//now go back to the main routine
}
void dma_usart2_nputs(const char* pString, int stringSize){
DMA_Cmd(DMA1_Channel7, DISABLE);
DMA_ClearFlag(DMA1_FLAG_TC7);
DMA1_Channel7->CMAR =(uint32_t) pString;
DMA_SetCurrDataCounter(DMA1_Channel7, stringSize);
USART_ClearFlag(USART2, USART_FLAG_TC);
DMA_ClearFlag(DMA1_FLAG_TC7);
dma_usart2_tx_complete = 0;
dma_usart2_irq_enable();
DMA_Cmd(DMA1_Channel7,ENABLE);
}
static void uart1TxDMA(void)
{
if ((tx1DmaEnabled == true) || (tx1BufferHead == tx1BufferTail)) // Ignore call if already active or no new data in buffer
return;
DMA2_Stream7->M0AR = (uint32_t)&tx1Buffer[tx1BufferTail];
if (tx1BufferHead > tx1BufferTail)
{
DMA_SetCurrDataCounter(DMA2_Stream7, tx1BufferHead - tx1BufferTail);
tx1BufferTail = tx1BufferHead;
}
else
{
DMA_SetCurrDataCounter(DMA2_Stream7, UART1_BUFFER_SIZE - tx1BufferTail);
tx1BufferTail = 0;
}
tx1DmaEnabled = true;
DMA_Cmd(DMA2_Stream7, ENABLE);
}
void i2c_dma_read( u8 read_addr)
{
// read_addr +=1;
//disable dma channel
DMA_Cmd( MPU6050_DMA_CHANNEL, DISABLE);
//? set current data number again to 14
DMA_SetCurrDataCounter(MPU6050_DMA_CHANNEL, 14);
//while the bus is busy
while( I2C_GetFlagStatus( MPU6050_I2C,I2C_FLAG_BUSY));
//enable dma nack automatic generation.....
I2C_DMALastTransferCmd( MPU6050_I2C, ENABLE);
//send start condition
I2C_GenerateSTART( MPU6050_I2C, ENABLE);
//test on ev5 and clear it
while( !I2C_CheckEvent( MPU6050_I2C, I2C_EVENT_MASTER_MODE_SELECT));
//send mpu6050 address for write
I2C_Send7bitAddress( MPU6050_I2C, I2C1_MPU6050, I2C_Direction_Transmitter );
//test on ev6 and clear it
while( !I2C_CheckEvent(MPU6050_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED));
//clear ev6 by setting again the PE bit
I2C_Cmd( MPU6050_I2C,ENABLE);
//send the mpu6050 internal address to write to
I2C_SendData( MPU6050_I2C, read_addr);
//test on ev8 and clear it
while(!I2C_CheckEvent( MPU6050_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTED));
//send start condition a second time
I2C_GenerateSTART(MPU6050_I2C, ENABLE);
//test on ev5 and clear it
while( !I2C_CheckEvent(MPU6050_I2C, I2C_EVENT_MASTER_MODE_SELECT));
//send mpu6050 address for read
I2C_Send7bitAddress(MPU6050_I2C,I2C1_MPU6050, I2C_Direction_Receiver);
//test on ev6 and clear it
while( !I2C_CheckEvent( MPU6050_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED));
//start dma to receive data from i2c
DMA_Cmd(MPU6050_DMA_CHANNEL, ENABLE);
I2C_DMACmd(MPU6050_I2C, ENABLE);
//when the data transmission is complete, it will automatically jump to dma interrupt routine
//to finish the rest.
}
void dma_usart2_nputs(const char* pString, int stringSize, void (*tx_complete_callback)(void)){
DMA_Cmd(DMA1_Channel4, DISABLE);
DMA_ClearFlag(DMA1_FLAG_TC4);
DMA1_Channel4->CMAR =(uint32_t) pString;
DMA_SetCurrDataCounter(DMA1_Channel4, stringSize);
USART_ClearFlag(USART2, USART_FLAG_TC);
DMA_ClearFlag(DMA1_FLAG_TC4);
dma_usart2_tx_callback = tx_complete_callback;
dma_usart2_tx_complete = 0;
dma_usart2_irq_enable();
DMA_Cmd(DMA1_Channel4,ENABLE);
}
/***************************************************************************************************
* @fn ana_inputs_sample_start
*
* @brief Ò¡¸Ë¡¢²¦ÂÖ¼°µçѹ¼à²â²ÉÑù¿ªÊ¼
* @param NULL
* @return NULL
***************************************************************************************************/
void ana_inputs_sample_start(void)
{
DMA_Cmd(SKYBORNE_ADC_DMA_STREAM,DISABLE);
ADC_ClearFlag(SKYBORNE_ADC, ADC_FLAG_EOC | ADC_FLAG_STRT | ADC_FLAG_OVR);
DMA_ClearITPendingBit(SKYBORNE_ADC_DMA_STREAM, SKYBORNE_ADC_DMA_TC_FLAG);
DMA_SetCurrDataCounter(SKYBORNE_ADC_DMA_STREAM, ADC_MODULE_NUMBER);
ADC_DMARequestAfterLastTransferCmd(SKYBORNE_ADC, ENABLE);
ADC_DMACmd(SKYBORNE_ADC, ENABLE);
DMA_ITConfig(SKYBORNE_ADC_DMA_STREAM, DMA_IT_TC, ENABLE);
DMA_Cmd(SKYBORNE_ADC_DMA_STREAM, ENABLE);
ADC_SoftwareStartConv(SKYBORNE_ADC);
}
//-----------------------------------------------------------------
//RX
void DMA2_Stream0_IRQHandler(void)
{
uint16_t temp;
if (DMA_GetITStatus(DMA2_Stream0, DMA_IT_TCIF0) == SET)
{
DMA_ClearITPendingBit(DMA2_Stream0, DMA_IT_TCIF0);
CS_OFF();
SPI_work = 0;
buffer[0] = 0xAA;
buffer[1] = 0xBB;
temp = (((uint16_t)SPI_In[2])<<8)|((uint16_t)SPI_In[1]);
if (temp >= 0x8000)
{
temp = temp - 0x8000;
} else {
temp = temp + 0x8000;
}
buffer[2] = (uint8_t)(temp>>8);//X
buffer[3] = (uint8_t)temp;
temp = (((uint16_t)SPI_In[4])<<8)|((uint16_t)SPI_In[3]);//Y
if (temp >= 0x8000)
{
temp = temp - 0x8000;
} else {
temp = temp + 0x8000;
}
buffer[4] = (uint8_t)(temp>>8);//Y
buffer[5] = (uint8_t)temp;
temp = (((uint16_t)SPI_In[6])<<8)|((uint16_t)SPI_In[5]);//Z
if (temp >= 0x8000)
{
temp = temp - 0x8000;
} else {
temp = temp + 0x8000;
}
buffer[6] = (uint8_t)(temp>>8);//Z
buffer[7] = (uint8_t)temp;
DMA_SetCurrDataCounter(DMA1_Stream6, 8);
DMA_Cmd(DMA1_Stream6, ENABLE);
}
void set_task_adc(struct signal* psig, struct head_data_adc* phadc) {
if(pb_adc == NULL || !check_buffer_is_free(pb_adc))
pb_adc = alloc_buf(SIZE_BIG_BUFFER);
init_header_buffer_adc(pb_adc, sizeof(struct head_data_adc) + SIZE_BIG_BUFFER * sizeof(uint16_t), phadc);
DMA_SetCurrDataCounter(DMA2_Stream0, NUMBER_SAMPL_ADC);
DMA2_Stream0->M0AR = (uint32_t)((char*) pb_adc->pbuf + sizeof(struct head) + sizeof(struct head_data_adc));
TIM3->ARR = psig->arr_adc;
TIM_PrescalerConfig(TIM3, psig->psc_adc, TIM_PSCReloadMode_Update);
/*Refill register TIM1CCR1*/
TIM3->EGR |= 0x0001;
DMA_Cmd(DMA2_Stream0, ENABLE);
ADC_Cmd(ADC1, ENABLE);
ADC_DMACmd(ADC1, DISABLE);
ADC_DMACmd(ADC1, ENABLE);
}
