/*
Process the upper socket ioctl command
*/
static int dmfe_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
{
board_info_t *db = netdev_priv(dev);
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,7) /* for kernel 2.6.7 */
struct mii_ioctl_data *data=(struct mii_ioctl_data *)&ifr->ifr_data;
#endif
int rc=0;
DMFE_DBUG(0, "dmfe_do_ioctl()", 0);
if (!netif_running(dev))
return -EINVAL;
if (cmd == SIOCETHTOOL)
rc = dmfe_ethtool_ioctl(dev, (void *) ifr->ifr_data);
else {
spin_lock_irq(&db->lock);
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,7) /* for kernel 2.6.7 */
rc = generic_mii_ioctl(&db->mii, data, cmd, NULL);
#else
rc = generic_mii_ioctl(&db->mii, if_mii(ifr), cmd, NULL);
#endif
spin_unlock_irq(&db->lock);
}
return rc;
}
/* Our watchdog timed out. Called by the networking layer */
static void dmfe_timeout(struct net_device *dev)
{
board_info_t *db = netdev_priv(dev);
int i;
DMFE_DBUG(0, "dmfe_TX_timeout()", 0);
printk("TX time-out -- dmfe_timeout().\n");
db->reset_tx_timeout++;
db->stats.tx_errors++;
#if FALSE
printk("TX packet count = %d\n", db->tx_pkt_cnt);
printk("TX timeout = %d\n", db->reset_tx_timeout);
printk("22H=0x%02x 23H=0x%02x\n",ior(db,0x22),ior(db,0x23));
printk("faH=0x%02x fbH=0x%02x\n",ior(db,0xfa),ior(db,0xfb));
#endif
i=0;
while((i++<100)&&(ior(db,DM9KS_TCR) & 0x01))
{
udelay(30);
}
if(i<100)
{
db->tx_pkt_cnt = 0;
netif_wake_queue(dev);
}
else
{
dmfe_reset(dev);
}
}
/*
Open the interface.
The interface is opened whenever "ifconfig" actives it.
*/
static int dmfe_open(struct net_device *dev)
{
board_info_t *db = (board_info_t *)dev->priv;
u8 reg_nsr;
int i;
DMFE_DBUG(0, "dmfe_open", 0);
/* [email protected] */
if (request_irq(dev->irq,&dmfe_interrupt, IRQF_TRIGGER_RISING,dev->name,dev))
return -EAGAIN;
/* Initilize DM910X board */
dmfe_init_dm9000(dev);
#ifdef DM8606
// control DM8606
printk("[8606]reg0=0x%04x\n",dm8606_read(db,0));
printk("[8606]reg1=0x%04x\n",dm8606_read(db,0x1));
#endif
/* Init driver variable */
db->reset_counter = 0;
db->reset_tx_timeout = 0;
db->cont_rx_pkt_cnt = 0;
/* check link state and media speed */
db->Speed =10;
i=0;
do {
reg_nsr = ior(db,DM9KS_NSR);
if(reg_nsr & 0x40) /* link OK!! */
{
/* wait for detected Speed */
mdelay(200);
reg_nsr = ior(db,DM9KS_NSR);
if(reg_nsr & 0x80)
db->Speed =10;
else
db->Speed =100;
break;
}
i++;
mdelay(1);
}while(i<3000); /* wait 3 second */
//printk("i=%d Speed=%d\n",i,db->Speed);
/* set and active a timer process */
init_timer(&db->timer);
db->timer.expires = DMFE_TIMER_WUT;
db->timer.data = (unsigned long)dev;
db->timer.function = &dmfe_timer;
add_timer(&db->timer); //Move to DM9000 initiallization was finished.
netif_start_queue(dev);
return 0;
}
/* Initilize DM910X board
Reset DM910X board
Initilize TX/Rx descriptor chain structure
Send the set-up frame
Enable Tx/Rx machine
*/
static void dmfe_init_dm910x(struct device *dev)
{
struct dmfe_board_info *db = dev->priv;
u32 ioaddr = db->ioaddr;
DMFE_DBUG(0, "dmfe_init_dm910x()", 0);
/* Reset DM910x board : need 32 PCI clock to complete */
outl(DM910X_RESET, ioaddr + DCR0); /* RESET MAC */
DELAY_5US;
outl(db->cr0_data, ioaddr + DCR0);
outl(0x180, ioaddr + DCR12); /* Let bit 7 output port */
outl(0x80, ioaddr + DCR12); /* RESET DM9102 phyxcer */
outl(0x0, ioaddr + DCR12); /* Clear RESET signal */
/* Phy addr : DM910(A)2/DM9132/9801, phy address = 1 */
db->phy_addr = 1;
/* Media Mode Check */
db->media_mode = dmfe_media_mode;
if (db->media_mode & DMFE_AUTO)
dmfe_sense_speed(db);
else
db->op_mode = db->media_mode;
dmfe_process_mode(db);
/* Initiliaze Transmit/Receive decriptor and CR3/4 */
dmfe_descriptor_init(db, ioaddr);
/* Init CR6 to program DM910x operation */
update_cr6(db->cr6_data, ioaddr);
/* Send setup frame */
if (db->chip_id == PCI_DM9132_ID)
dm9132_id_table(dev, dev->mc_count); /* DM9132 */
else
send_filter_frame(dev, dev->mc_count); /* DM9102/DM9102A */
/* Init CR5/CR7, interrupt active bit */
outl(0xffffffff, ioaddr + DCR5); /* clear all CR5 status */
db->cr7_data = CR7_DEFAULT;
outl(db->cr7_data, ioaddr + DCR7);
/* Init CR15, Tx jabber and Rx watchdog timer */
db->cr15_data = CR15_DEFAULT;
outl(db->cr15_data, ioaddr + DCR15);
/* Enable DM910X Tx/Rx function */
db->cr6_data |= CR6_RXSC | CR6_TXSC;
update_cr6(db->cr6_data, ioaddr);
}
/*
Set DM9000/DM9010 multicast address
*/
static void dm9000_hash_table(struct net_device *dev)
{
board_info_t *db = (board_info_t *)dev->priv;
struct dev_mc_list *mcptr = dev->mc_list;
int mc_cnt = dev->mc_count;
u32 hash_val;
u16 i, oft, hash_table[4];
DMFE_DBUG(0, "dm9000_hash_table()", 0);
/* enable promiscuous mode */
if (dev->flags & IFF_PROMISC){
//printk(KERN_INFO "DM9KS:enable promiscuous mode\n");
iow(db, DM9KS_RXCR, ior(db,DM9KS_RXCR)|(1<<1));
return;
}else{
//printk(KERN_INFO "DM9KS:disable promiscuous mode\n");
iow(db, DM9KS_RXCR, ior(db,DM9KS_RXCR)&(~(1<<1)));
}
/* Receive all multicast packets */
if (dev->flags & IFF_ALLMULTI){
//printk(KERN_INFO "DM9KS:Pass all multicast\n");
iow(db, DM9KS_RXCR, ior(db,DM9KS_RXCR)|(1<<3));
}else{
//printk(KERN_INFO "DM9KS:Disable pass all multicast\n");
iow(db, DM9KS_RXCR, ior(db,DM9KS_RXCR)&(~(1<<3)));
}
/* Set Node address */
for (i = 0, oft = 0x10; i < 6; i++, oft++)
iow(db, oft, dev->dev_addr[i]);
/* Clear Hash Table */
for (i = 0; i < 4; i++)
hash_table[i] = 0x0;
/* broadcast address */
hash_table[3] = 0x8000;
/* the multicast address in Hash Table : 64 bits */
for (i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
hash_val = cal_CRC((char *)mcptr->dmi_addr, 6, 0) & 0x3f;
hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
}
/* Write the hash table to MAC MD table */
for (i = 0, oft = 0x16; i < 4; i++) {
iow(db, oft++, hash_table[i] & 0xff);
iow(db, oft++, (hash_table[i] >> 8) & 0xff);
}
}
/*
Hardware start transmission.
Send a packet to media from the upper layer.
*/
static int dmfe_start_xmit(struct sk_buff *skb, struct device *dev)
{
struct dmfe_board_info *db = dev->priv;
struct tx_desc *txptr;
DMFE_DBUG(0, "dmfe_start_xmit", 0);
/* Resource flag check */
if (dev->tbusy == 1) /* Resource Busy */
return 1;
/* Too large packet check */
if (skb->len > MAX_PACKET_SIZE) {
printk(KERN_WARNING "%s: big packet, size=%d\n", dev->name, (u16) skb->len);
dev_kfree_skb(skb);
return 0;
}
/* No Tx resource check, it never happen normally */
if (db->tx_queue_cnt >= TX_FREE_DESC_CNT) {
dev->tbusy = 1;
return 1;
}
/* transmit this packet */
txptr = db->tx_insert_ptr;
memcpy((char *) txptr->tx_buf_ptr, (char *) skb->data, skb->len);
txptr->tdes1 = 0xe1000000 | skb->len;
/* Point to next transmit free descriptor */
db->tx_insert_ptr = (struct tx_desc *) txptr->next_tx_desc;
/* Transmit Packet Process */
if (db->tx_packet_cnt < TX_MAX_SEND_CNT) {
txptr->tdes0 = 0x80000000; /* set owner bit to DM910X */
db->tx_packet_cnt++; /* Ready to send count */
outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling comand */
dev->trans_start = jiffies; /* saved the time stamp */
} else {
db->tx_queue_cnt++; /* queue the tx packet */
outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling comand */
}
/* Tx resource check */
if (db->tx_queue_cnt >= TX_FREE_DESC_CNT) {
dev->tbusy = 1;
}
/* free this SKB */
dev_kfree_skb(skb);
return 0;
}
/* Hardware start transmission.
* Send a packet to media from the upper layer.
*/
static int dmfe_start_xmit(struct sk_buff *skb, struct net_device *dev)
{
board_info_t *db = (board_info_t *) dev->priv;
char *data_ptr;
int i, tmplen;
DMFE_DBUG(0, "dmfe_start_xmit", 0);
if (db->tx_pkt_cnt > 1) return 1;
netif_stop_queue(dev);
/* Disable all interrupt */
iow(db, 0xff, 0x80);
/* Move data to DM9000 TX RAM */
data_ptr = (char *) skb->data;
outb(0xf8, db->ioaddr);
db->sent_pkt_len = skb->len;
if (db->io_mode == DM9000_BYTE_MODE) { /* Byte mode */
for (i = 0; i < skb->len; i++)
outb((data_ptr[i] & 0xff), db->io_data);
} else if (db->io_mode == DM9000_WORD_MODE) { /* Word mode */
tmplen = (skb->len + 1) / 2;
for (i = 0; i < tmplen; i++)
outw(((u16 *) data_ptr)[i], db->io_data);
} else { /* DWord mode */
tmplen = (skb->len + 3) / 4;
for (i = 0; i < tmplen; i++)
outl(((u32 *) data_ptr)[i], db->io_data);
}
/* TX control: First packet immediately send, second packet queue */
if (db->tx_pkt_cnt == 0) { /* First Packet */
db->tx_pkt_cnt++;
/* Set TX length to DM9000 */
iow(db, 0xfc, skb->len & 0xff);
iow(db, 0xfd, (skb->len >> 8) & 0xff);
/* Issue TX polling command */
iow(db, 0x2, 0x1); /* Cleared after TX complete */
/* saved the time stamp */
dev->trans_start = jiffies;
} else { /* Second packet */
/*
A periodic timer routine
*/
static void dmfe_timer(unsigned long data)
{
struct net_device * dev = (struct net_device *)data;
board_info_t *db = (board_info_t *)dev->priv;
DMFE_DBUG(0, "dmfe_timer()", 0);
if (db->cont_rx_pkt_cnt>=CONT_RX_PKT_CNT)
{
db->cont_rx_pkt_cnt=0;
iow(db, DM9KS_IMR, DM9KS_REGFF);
}
/* Set timer again */
db->timer.expires = DMFE_TIMER_WUT;
add_timer(&db->timer);
return;
}
/* Open the interface.
* The interface is opened whenever "ifconfig" actives it.
*/
static int dmfe_open(struct net_device *dev)
{
board_info_t *db = (board_info_t *) dev->priv;
DMFE_DBUG(0, "dmfe_open", 0);
if (request_irq(dev->irq, &dmfe_interrupt, /*SA_INTERRUPT*/SA_SHIRQ, dev->name/*"DM9000 device"*/, dev))
{
return -EAGAIN;
}
/* Initilize DM910X board */
dmfe_init_dm9000(dev);
/* Init driver variable */
db->dbug_cnt = 0;
db->runt_length_counter = 0;
db->long_length_counter = 0;
db->reset_counter = 0;
/* set and active a timer process */
init_timer(&db->timer);
db->timer.expires = DMFE_TIMER_WUT * 2;
db->timer.data = (unsigned long) dev;
db->timer.function = &dmfe_timer;
add_timer(&db->timer); // Move to DM9000 initiallization was finished.
#if defined(AUTOMDIX)
/* set and active a timer process for Auto-MDIX */
init_timer(&db->mdix_timer);
db->mdix_timer.expires = DMFE_TIMER_MDIX;
db->mdix_timer.data = (unsigned long) dev;
db->mdix_timer.function = &dmfe_mdix_timer;
add_timer(&db->mdix_timer);
#endif
netif_start_queue(dev);
enable_irq(dev->irq);
return 0;
}
struct net_device * __init dmfe_probe(void)
{
struct net_device *dev;
int err;
DMFE_DBUG(0, "dmfe_probe()",0);
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
dev = init_etherdev(NULL, sizeof(struct board_info));
//ether_setup(dev);
#else
dev= alloc_etherdev(sizeof(struct board_info));
#endif
if(!dev)
return ERR_PTR(-ENOMEM);
SET_MODULE_OWNER(dev);
err = dmfe_probe1(dev);
if (err)
goto out;
#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
err = register_netdev(dev);
if (err)
goto out1;
#endif
return dev;
out1:
release_region(dev->base_addr,2);
out:
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
kfree(dev);
#else
free_netdev(dev);
#endif
return ERR_PTR(err);
}
/*
Open the interface.
The interface is opened whenever "ifconfig" actives it.
*/
static int dmfe_open(struct device *dev)
{
struct dmfe_board_info *db = dev->priv;
DMFE_DBUG(0, "dmfe_open", 0);
if (request_irq(dev->irq, &dmfe_interrupt, SA_SHIRQ, dev->name, dev))
return -EAGAIN;
/* Allocated Tx/Rx descriptor memory */
db->desc_pool_ptr = kmalloc(sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, GFP_KERNEL | GFP_DMA);
if (db->desc_pool_ptr == NULL)
return -ENOMEM;
if ((u32) db->desc_pool_ptr & 0x1f)
db->first_tx_desc = (struct tx_desc *) (((u32) db->desc_pool_ptr & ~0x1f) + 0x20);
else
db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
/* Allocated Tx buffer memory */
db->buf_pool_ptr = kmalloc(TX_BUF_ALLOC * TX_DESC_CNT + 4, GFP_KERNEL | GFP_DMA);
if (db->buf_pool_ptr == NULL) {
kfree(db->desc_pool_ptr);
return -ENOMEM;
}
if ((u32) db->buf_pool_ptr & 0x3)
db->buf_pool_start = (char *) (((u32) db->buf_pool_ptr & ~0x3) + 0x4);
else
db->buf_pool_start = db->buf_pool_ptr;
/* system variable init */
db->cr6_data = CR6_DEFAULT | dmfe_cr6_user_set;
db->tx_packet_cnt = 0;
db->tx_queue_cnt = 0;
db->rx_avail_cnt = 0;
db->link_failed = 0;
db->wait_reset = 0;
db->in_reset_state = 0;
db->rx_error_cnt = 0;
if (!chkmode || (db->chip_id == PCI_DM9132_ID) || (db->chip_revesion >= 0x02000030)) {
//db->cr6_data &= ~CR6_SFT; /* Used Tx threshold */
//db->cr6_data |= CR6_NO_PURGE; /* No purge if rx unavailable */
db->cr0_data = 0xc00000; /* TX/RX desc burst mode */
db->dm910x_chk_mode = 4; /* Enter the normal mode */
} else {
db->cr0_data = 0;
db->dm910x_chk_mode = 1; /* Enter the check mode */
}
/* Initilize DM910X board */
dmfe_init_dm910x(dev);
/* Active System Interface */
dev->tbusy = 0; /* Can transmit packet */
dev->start = 1; /* interface ready */
MOD_INC_USE_COUNT;
/* set and active a timer process */
init_timer(&db->timer);
db->timer.expires = DMFE_TIMER_WUT;
db->timer.data = (unsigned long) dev;
db->timer.function = &dmfe_timer;
add_timer(&db->timer);
return 0;
}
/*
Search DM910X board ,allocate space and register it
*/
int dmfe_probe(struct device *dev)
{
unsigned long pci_iobase;
u16 dm9102_count = 0;
u8 pci_irqline;
static int index = 0; /* For multiple call */
struct dmfe_board_info *db; /* Point a board information structure */
int i;
struct pci_dev *net_dev = NULL;
DMFE_DBUG(0, "dmfe_probe()", 0);
if (!pci_present())
return -ENODEV;
index = 0;
while ((net_dev = pci_find_class(PCI_CLASS_NETWORK_ETHERNET << 8, net_dev)))
{
u32 pci_id;
u32 dev_rev;
u8 pci_cmd;
index++;
if (pci_read_config_dword(net_dev, PCI_VENDOR_ID, &pci_id) != DMFE_SUCC)
continue;
if ((pci_id != PCI_DM9102_ID) && (pci_id != PCI_DM9132_ID))
continue;
/* read PCI IO base address and IRQ to check */
pci_iobase = net_dev->base_address[0];
pci_irqline = net_dev->irq;
pci_iobase &= ~0x7f; /* mask off bit0~6 */
/* Enable Master/IO access, Disable memory access */
pci_read_config_byte(net_dev, PCI_COMMAND, &pci_cmd);
pci_cmd |= PCI_COMMAND_IO + PCI_COMMAND_MASTER;
pci_cmd &= ~PCI_COMMAND_MEMORY;
pci_write_config_byte(net_dev, PCI_COMMAND, pci_cmd);
/* Set Latency Timer 80h */
pci_write_config_byte(net_dev, PCI_LATENCY_TIMER, 0x80);
/* Read Chip revesion */
pci_read_config_dword(net_dev, PCI_REVISION_ID, &dev_rev);
/* IO range check */
if (check_region(pci_iobase, CHK_IO_SIZE(pci_id, dev_rev)))
continue;
/* Interrupt check */
if (pci_irqline == 0) {
printk(KERN_ERR "dmfe: Interrupt wrong : IRQ=%d\n", pci_irqline);
continue;
}
/* Found DM9102 card and PCI resource allocated OK */
dm9102_count++; /* Found a DM9102 card */
/* Init network device */
dev = init_etherdev(dev, 0);
/* Allocated board information structure */
db = (void *) (kmalloc(sizeof(*db), GFP_KERNEL | GFP_DMA));
memset(db, 0, sizeof(*db));
dev->priv = db; /* link device and board info */
db->next_dev = dmfe_root_dev;
dmfe_root_dev = dev;
db->chip_id = pci_id; /* keep Chip vandor/Device ID */
db->ioaddr = pci_iobase;
db->chip_revesion = dev_rev;
db->net_dev = net_dev;
dev->base_addr = pci_iobase;
dev->irq = pci_irqline;
dev->open = &dmfe_open;
dev->hard_start_xmit = &dmfe_start_xmit;
dev->stop = &dmfe_stop;
dev->get_stats = &dmfe_get_stats;
dev->set_multicast_list = &dmfe_set_filter_mode;
dev->do_ioctl = &dmfe_do_ioctl;
request_region(pci_iobase, CHK_IO_SIZE(pci_id, dev_rev), dev->name);
/* read 64 word srom data */
for (i = 0; i < 64; i++)
((u16 *) db->srom)[i] = read_srom_word(pci_iobase, i);
/* Set Node address */
for (i = 0; i < 6; i++)
dev->dev_addr[i] = db->srom[20 + i];
dev = 0; /* NULL device */
}
return dm9102_count ? 0 : -ENODEV;
}
/*
Get statistics from driver.
*/
static struct net_device_stats * dmfe_get_stats(struct net_device *dev)
{
board_info_t *db = (board_info_t *)dev->priv;
DMFE_DBUG(0, "dmfe_get_stats", 0);
return &db->stats;
}
static irqreturn_t dmfe_interrupt(int irq, void *dev_id) /* for kernel 2.6.20*/
#endif
#endif
{
struct net_device *dev = dev_id;
board_info_t *db;
int int_status,i;
u8 reg_save;
DMFE_DBUG(0, "dmfe_interrupt()", 0);
/* A real interrupt coming */
db = (board_info_t *)dev->priv;
spin_lock(&db->lock);
/* Save previous register address */
reg_save = inb(db->io_addr);
/* Disable all interrupt */
iow(db, DM9KS_IMR, DM9KS_DISINTR);
/* Got DM9000/DM9010 interrupt status */
int_status = ior(db, DM9KS_ISR); /* Got ISR */
iow(db, DM9KS_ISR, int_status); /* Clear ISR status */
/* Link status change */
if (int_status & DM9KS_LINK_INTR)
{
netif_stop_queue(dev);
for(i=0; i<500; i++) /*wait link OK, waiting time =0.5s */
{
phy_read(db,0x1);
if(phy_read(db,0x1) & 0x4) /*Link OK*/
{
/* wait for detected Speed */
for(i=0; i<200;i++)
udelay(1000);
/* set media speed */
if(phy_read(db,0)&0x2000) db->Speed =100;
else db->Speed =10;
break;
}
udelay(1000);
}
netif_wake_queue(dev);
//printk("[INTR]i=%d speed=%d\n",i, (int)(db->Speed));
}
/* Received the coming packet */
if (int_status & DM9KS_RX_INTR)
dmfe_packet_receive(dev);
/* Trnasmit Interrupt check */
if (int_status & DM9KS_TX_INTR)
dmfe_tx_done(0);
if (db->cont_rx_pkt_cnt>=CONT_RX_PKT_CNT)
{
iow(db, DM9KS_IMR, 0xa2);
}
else
{
/* Re-enable interrupt mask */
iow(db, DM9KS_IMR, DM9KS_REGFF);
}
/* Restore previous register address */
outb(reg_save, db->io_addr);
spin_unlock(&db->lock);
#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
return IRQ_HANDLED;
#endif
}
/*
Hardware start transmission.
Send a packet to media from the upper layer.
*/
static int dmfe_start_xmit(struct sk_buff *skb, struct net_device *dev)
{
board_info_t *db = (board_info_t *)dev->priv;
char * data_ptr;
int i, tmplen;
u16 MDWAH, MDWAL;
#ifdef TDBUG /* check TX FIFO pointer */
u16 MDWAH1, MDWAL1;
u16 tx_ptr;
#endif
DMFE_DBUG(0, "dmfe_start_xmit", 0);
if (db->chip_revision != 0x1A)
{
if(db->Speed == 10)
{if (db->tx_pkt_cnt >= 1) return 1;}
else
{if (db->tx_pkt_cnt >= 2) return 1;}
}else
if (db->tx_pkt_cnt >= 2) return 1;
/* packet counting */
db->tx_pkt_cnt++;
db->stats.tx_packets++;
db->stats.tx_bytes+=skb->len;
if (db->chip_revision != 0x1A)
{
if (db->Speed == 10)
{if (db->tx_pkt_cnt >= 1) netif_stop_queue(dev);}
else
{if (db->tx_pkt_cnt >= 2) netif_stop_queue(dev);}
}else
if (db->tx_pkt_cnt >= 2) netif_stop_queue(dev);
/* Disable all interrupt */
iow(db, DM9KS_IMR, DM9KS_DISINTR);
MDWAH = ior(db,DM9KS_MDWAH);
MDWAL = ior(db,DM9KS_MDWAL);
/* Set TX length to reg. 0xfc & 0xfd */
iow(db, DM9KS_TXPLL, (skb->len & 0xff));
iow(db, DM9KS_TXPLH, (skb->len >> 8) & 0xff);
/* Move data to TX SRAM */
data_ptr = (char *)skb->data;
outb(DM9KS_MWCMD, db->io_addr); // Write data into SRAM trigger
switch(db->io_mode)
{
case DM9KS_BYTE_MODE:
for (i = 0; i < skb->len; i++)
outb((data_ptr[i] & 0xff), db->io_data);
break;
case DM9KS_WORD_MODE:
tmplen = (skb->len + 1) / 2;
for (i = 0; i < tmplen; i++)
outw(((u16 *)data_ptr)[i], db->io_data);
break;
case DM9KS_DWORD_MODE:
tmplen = (skb->len + 3) / 4;
for (i = 0; i< tmplen; i++)
outl(((u32 *)data_ptr)[i], db->io_data);
break;
}
#ifndef ETRANS
/* Issue TX polling command */
iow(db, DM9KS_TCR, 0x1); /* Cleared after TX complete*/
#endif
#ifdef TDBUG /* check TX FIFO pointer */
MDWAH1 = ior(db,DM9KS_MDWAH);
MDWAL1 = ior(db,DM9KS_MDWAL);
tx_ptr = (MDWAH<<8)|MDWAL;
switch (db->io_mode)
{
case DM9KS_BYTE_MODE:
tx_ptr += skb->len;
break;
case DM9KS_WORD_MODE:
tx_ptr += ((skb->len + 1) / 2)*2;
break;
case DM9KS_DWORD_MODE:
tx_ptr += ((skb->len+3)/4)*4;
break;
}
if (tx_ptr > 0x0bff)
tx_ptr -= 0x0c00;
if (tx_ptr != ((MDWAH1<<8)|MDWAL1))
printk("[dm9ks:TX FIFO ERROR\n");
#endif
/* Saved the time stamp */
dev->trans_start = jiffies;
db->cont_rx_pkt_cnt =0;
/* Free this SKB */
dev_kfree_skb(skb);
/* Re-enable interrupt */
iow(db, DM9KS_IMR, DM9KS_REGFF);
return 0;
}
/*
Initilize dm9000 board
*/
static void dmfe_init_dm9000(struct net_device *dev)
{
board_info_t *db = (board_info_t *)dev->priv;
DMFE_DBUG(0, "dmfe_init_dm9000()", 0);
spin_lock_init(&db->lock);
iow(db, DM9KS_GPR, 0); /* GPR (reg_1Fh)bit GPIO0=0 pre-activate PHY */
mdelay(20); /* wait for PHY power-on ready */
/* do a software reset and wait 20us */
iow(db, DM9KS_NCR, 3);
udelay(20); /* wait 20us at least for software reset ok */
iow(db, DM9KS_NCR, 3); /* NCR (reg_00h) bit[0] RST=1 & Loopback=1, reset on */
udelay(20); /* wait 20us at least for software reset ok */
/* I/O mode */
db->io_mode = ior(db, DM9KS_ISR) >> 6; /* ISR bit7:6 keeps I/O mode */
/* Set PHY */
db->op_mode = media_mode;
set_PHY_mode(db);
/* Program operating register */
iow(db, DM9KS_NCR, 0);
iow(db, DM9KS_TCR, 0); /* TX Polling clear */
iow(db, DM9KS_BPTR, 0x3f); /* Less 3kb, 600us */
iow(db, DM9KS_SMCR, 0); /* Special Mode */
iow(db, DM9KS_NSR, 0x2c); /* clear TX status */
iow(db, DM9KS_ISR, 0x0f); /* Clear interrupt status */
iow(db, DM9KS_TCR2, 0x80); /* Set LED mode 1 */
if (db->chip_revision == 0x1A){
/* Data bus current driving/sinking capability */
iow(db, DM9KS_BUSCR, 0x01); /* default: 2mA */
}
#ifdef FLOW_CONTROL
iow(db, DM9KS_BPTR, 0x37);
iow(db, DM9KS_FCTR, 0x38);
iow(db, DM9KS_FCR, 0x29);
#endif
#ifdef DM8606
iow(db,0x34,1);
#endif
if (dev->features & NETIF_F_HW_CSUM){
printk(KERN_INFO "DM9KS:enable TX checksum\n");
iow(db, DM9KS_TCCR, 0x07); /* TX UDP/TCP/IP checksum enable */
}
if (db->rx_csum){
printk(KERN_INFO "DM9KS:enable RX checksum\n");
iow(db, DM9KS_RCSR, 0x02); /* RX checksum enable */
}
#ifdef ETRANS
/*If TX loading is heavy, the driver can try to anbel "early transmit".
The programmer can tune the "Early Transmit Threshold" to get
the optimization. (DM9KS_ETXCSR.[1-0])
Side Effect: It will happen "Transmit under-run". When TX under-run
always happens, the programmer can increase the value of "Early
Transmit Threshold". */
iow(db, DM9KS_ETXCSR, 0x83);
#endif
/* Set address filter table */
dm9000_hash_table(dev);
/* Activate DM9000/DM9010 */
iow(db, DM9KS_IMR, DM9KS_REGFF); /* Enable TX/RX interrupt mask */
iow(db, DM9KS_RXCR, DM9KS_REG05 | 1); /* RX enable */
/* Init Driver variable */
db->tx_pkt_cnt = 0;
netif_carrier_on(dev);
}
int __init dmfe_probe1(struct net_device *dev)
{
struct board_info *db; /* Point a board information structure */
u32 id_val;
u16 i, dm9000_found = FALSE;
u8 MAC_addr[6]={0x00,0x60,0x6E,0x33,0x44,0x55};
u8 HasEEPROM=0,chip_info;
DMFE_DBUG(0, "dmfe_probe1()",0);
/* Search All DM9000 serial NIC */
do {
outb(DM9KS_VID_L, iobase);
id_val = inb(iobase + 4);
outb(DM9KS_VID_H, iobase);
id_val |= inb(iobase + 4) << 8;
outb(DM9KS_PID_L, iobase);
id_val |= inb(iobase + 4) << 16;
outb(DM9KS_PID_H, iobase);
id_val |= inb(iobase + 4) << 24;
if (id_val == DM9KS_ID || id_val == DM9010_ID) {
/* Request IO from system */
if(!request_region(iobase, 2, dev->name))
return -ENODEV;
printk(KERN_ERR"<DM9KS> I/O: %x, VID: %x \n",iobase, id_val);
dm9000_found = TRUE;
/* Allocated board information structure */
memset(dev->priv, 0, sizeof(struct board_info));
db = (board_info_t *)dev->priv;
dmfe_dev = dev;
db->io_addr = iobase;
db->io_data = iobase + 4;
db->chip_revision = ior(db, DM9KS_CHIPR);
chip_info = ior(db,0x43);
if((db->chip_revision!=0x1A) || ((chip_info&(1<<5))!=0) || ((chip_info&(1<<2))!=1)) return -ENODEV;
/* driver system function */
dev->base_addr = iobase;
dev->irq = irq;
dev->open = &dmfe_open;
dev->hard_start_xmit = &dmfe_start_xmit;
dev->watchdog_timeo = 5*HZ;
dev->tx_timeout = dmfe_timeout;
dev->stop = &dmfe_stop;
dev->get_stats = &dmfe_get_stats;
dev->set_multicast_list = &dm9000_hash_table;
dev->do_ioctl = &dmfe_do_ioctl;
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,28)
dev->ethtool_ops = &dmfe_ethtool_ops;
#endif
#ifdef CHECKSUM
//dev->features |= NETIF_F_IP_CSUM;
dev->features |= NETIF_F_IP_CSUM|NETIF_F_SG;
#endif
db->mii.dev = dev;
db->mii.mdio_read = mdio_read;
db->mii.mdio_write = mdio_write;
db->mii.phy_id = 1;
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20)
db->mii.phy_id_mask = 0x1F;
db->mii.reg_num_mask = 0x1F;
#endif
//db->msg_enable =(debug == 0 ? DMFE_DEF_MSG_ENABLE : ((1 << debug) - 1));
/* Read SROM content */
for (i=0; i<64; i++)
((u16 *)db->srom)[i] = read_srom_word(db, i);
/* Get the PID and VID from EEPROM to check */
id_val = (((u16 *)db->srom)[4])|(((u16 *)db->srom)[5]<<16);
printk("id_val=%x\n", id_val);
if (id_val == DM9KS_ID || id_val == DM9010_ID)
HasEEPROM =1;
/* Set Node Address */
for (i=0; i<6; i++)
{
if (HasEEPROM) /* use EEPROM */
dev->dev_addr[i] = db->srom[i];
else /* No EEPROM */
dev->dev_addr[i] = MAC_addr[i];
}
}//end of if()
iobase += 0x10;
}while(!dm9000_found && iobase <= DM9KS_MAX_IO);
return dm9000_found ? 0:-ENODEV;
}
/* Search DM9000 board, allocate space and register it */
int dmfe_probe(struct net_device *dev)
{
struct board_info *db; /* Point a board information structure */
int i;
u32 id_val;
u32 iobase;
u16 dm9000_found = FALSE;
DMFE_DBUG(0, "dmfe_probe()", 0);
bwscon=ioremap_nocache(BWSCON,0x0000004);
gpfcon=ioremap_nocache(GPFCON,0x0000004);
extint0=ioremap_nocache(EXTINT0,0x0000004);
intmsk=ioremap_nocache(INTMSK,0x0000004);
writel(readl(bwscon)|0xc0000,bwscon);
writel( (readl(gpfcon) & ~(0x3 << 14)) | (0x2 << 14), gpfcon);
writel( readl(gpfcon) | (0x1 << 7), gpfcon); // Disable pull-up
writel( (readl(extint0) & ~(0xf << 28)) | (0x4 << 28), extint0); //rising edge
writel( (readl(intmsk)) & ~0x80, intmsk);
iobase = ioremap(DM9000_MIN_IO,0x400);//--
/* Search All DM9000 NIC */
do {
outb(DM9000_VID_L, iobase);
id_val = inb(iobase + 4);
outb(DM9000_VID_H, iobase);
id_val |= inb(iobase + 4) << 8;
outb(DM9000_PID_L, iobase);
id_val |= inb(iobase + 4) << 16;
outb(DM9000_PID_H, iobase);
id_val |= inb(iobase + 4) << 24;
if (id_val == DM9000_ID) {
printk("DM9000 ethernet driver V1.26 I/O: %x, VID: %x \n",
iobase, id_val);
dm9000_found = TRUE;
/* Allocated board information structure */
db = (void *) (kmalloc(sizeof (*db), GFP_KERNEL));
memset(db, 0, sizeof (*db));
dev->priv = db; /* link device and board info */
dmfe_dev = dev;
db->ioaddr = iobase;
db->io_data = iobase + 4;
/* driver system function */
ether_setup(dev);
dev->base_addr = iobase;
dev->irq = IRQ_EINT7;
dev->open = &dmfe_open;
dev->hard_start_xmit = &dmfe_start_xmit;
dev->stop = &dmfe_stop;
dev->get_stats = &dmfe_get_stats;
dev->set_multicast_list = &dm9000_hash_table;
dev->do_ioctl = &dmfe_do_ioctl;
SET_MODULE_OWNER(dev);
{
unsigned char enet_addr[6] = {0x00, 0x13, 0xf6, 0x6c, 0x87, 0x89}; //from 2.4
for (i=0; i < 6; i++) dev->dev_addr[i] = enet_addr[i];
}
/* Request IO from system */
request_region(iobase, 2, dev->name);
}
} while (!dm9000_found && (iobase+=0x10) <= DM9000_MAX_IO);
return (dm9000_found ? 0 : -ENODEV);
}
/*
Received a packet and pass to upper layer
*/
static void dmfe_packet_receive(struct net_device *dev)
{
board_info_t *db = (board_info_t *)dev->priv;
struct sk_buff *skb;
u8 rxbyte;
u16 i, GoodPacket, tmplen = 0, MDRAH, MDRAL;
u32 tmpdata;
rx_t rx;
u16 * ptr = (u16*)℞
u8* rdptr;
DMFE_DBUG(0, "dmfe_packet_receive()", 0);
db->cont_rx_pkt_cnt=0;
do {
/*store the value of Memory Data Read address register*/
MDRAH=ior(db, DM9KS_MDRAH);
MDRAL=ior(db, DM9KS_MDRAL);
ior(db, DM9KS_MRCMDX); /* Dummy read */
rxbyte = inb(db->io_data); /* Got most updated data */
#ifdef CHECKSUM
if (rxbyte&0x2) /* check RX byte */
{
printk("dm9ks: abnormal!\n");
dmfe_reset(dev);
break;
}else {
if (!(rxbyte&0x1))
break;
}
#else
if (rxbyte==0)
break;
if (rxbyte>1)
{
printk("dm9ks: Rxbyte error!\n");
dmfe_reset(dev);
break;
}
#endif
/* A packet ready now & Get status/length */
GoodPacket = TRUE;
outb(DM9KS_MRCMD, db->io_addr);
/* Read packet status & length */
switch (db->io_mode)
{
case DM9KS_BYTE_MODE:
*ptr = inb(db->io_data) +
(inb(db->io_data) << 8);
*(ptr+1) = inb(db->io_data) +
(inb(db->io_data) << 8);
break;
case DM9KS_WORD_MODE:
*ptr = inw(db->io_data);
*(ptr+1) = inw(db->io_data);
break;
case DM9KS_DWORD_MODE:
tmpdata = inl(db->io_data);
*ptr = tmpdata;
*(ptr+1) = tmpdata >> 16;
break;
default:
break;
}
/* Packet status check */
if (rx.desc.status & 0xbf)
{
GoodPacket = FALSE;
if (rx.desc.status & 0x01)
{
db->stats.rx_fifo_errors++;
printk(KERN_INFO"<RX FIFO error>\n");
}
if (rx.desc.status & 0x02)
{
db->stats.rx_crc_errors++;
printk(KERN_INFO"<RX CRC error>\n");
}
if (rx.desc.status & 0x80)
{
db->stats.rx_length_errors++;
printk(KERN_INFO"<RX Length error>\n");
}
if (rx.desc.status & 0x08)
printk(KERN_INFO"<Physical Layer error>\n");
}
if (!GoodPacket)
{
// drop this packet!!!
switch (db->io_mode)
{
case DM9KS_BYTE_MODE:
for (i=0; i<rx.desc.length; i++)
inb(db->io_data);
break;
case DM9KS_WORD_MODE:
tmplen = (rx.desc.length + 1) / 2;
for (i = 0; i < tmplen; i++)
inw(db->io_data);
break;
case DM9KS_DWORD_MODE:
tmplen = (rx.desc.length + 3) / 4;
for (i = 0; i < tmplen; i++)
inl(db->io_data);
break;
}
continue;/*next the packet*/
}
skb = dev_alloc_skb(rx.desc.length+4);
if (skb == NULL )
{
printk(KERN_INFO "%s: Memory squeeze.\n", dev->name);
/*re-load the value into Memory data read address register*/
iow(db,DM9KS_MDRAH,MDRAH);
iow(db,DM9KS_MDRAL,MDRAL);
return;
}
else
{
/* Move data from DM9000 */
skb->dev = dev;
skb_reserve(skb, 2);
rdptr = (u8*)skb_put(skb, rx.desc.length - 4);
/* Read received packet from RX SARM */
switch (db->io_mode)
{
case DM9KS_BYTE_MODE:
for (i=0; i<rx.desc.length; i++)
rdptr[i]=inb(db->io_data);
break;
case DM9KS_WORD_MODE:
tmplen = (rx.desc.length + 1) / 2;
for (i = 0; i < tmplen; i++)
((u16 *)rdptr)[i] = inw(db->io_data);
break;
case DM9KS_DWORD_MODE:
tmplen = (rx.desc.length + 3) / 4;
for (i = 0; i < tmplen; i++)
((u32 *)rdptr)[i] = inl(db->io_data);
break;
}
/* Pass to upper layer */
skb->protocol = eth_type_trans(skb,dev);
#ifdef CHECKSUM
if((rxbyte&0xe0)==0) /* receive packet no checksum fail */
skb->ip_summed = CHECKSUM_UNNECESSARY;
#endif
netif_rx(skb);
dev->last_rx=jiffies;
db->stats.rx_packets++;
db->stats.rx_bytes += rx.desc.length;
db->cont_rx_pkt_cnt++;
#ifdef RDBG /* check RX FIFO pointer */
u16 MDRAH1, MDRAL1;
u16 tmp_ptr;
MDRAH1 = ior(db,DM9KS_MDRAH);
MDRAL1 = ior(db,DM9KS_MDRAL);
tmp_ptr = (MDRAH<<8)|MDRAL;
switch (db->io_mode)
{
case DM9KS_BYTE_MODE:
tmp_ptr += rx.desc.length+4;
break;
case DM9KS_WORD_MODE:
tmp_ptr += ((rx.desc.length+1)/2)*2+4;
break;
case DM9KS_DWORD_MODE:
tmp_ptr += ((rx.desc.length+3)/4)*4+4;
break;
}
if (tmp_ptr >=0x4000)
tmp_ptr = (tmp_ptr - 0x4000) + 0xc00;
if (tmp_ptr != ((MDRAH1<<8)|MDRAL1))
printk("[dm9ks:RX FIFO ERROR\n");
#endif
if (db->cont_rx_pkt_cnt>=CONT_RX_PKT_CNT)
{
dmfe_tx_done(0);
break;
}
}
}while((rxbyte & 0x01) == DM9KS_PKT_RDY);
DMFE_DBUG(0, "[END]dmfe_packet_receive()", 0);
}
/* Initilize dm9000 board */
static void dmfe_init_dm9000(struct net_device *dev)
{
board_info_t *db = (board_info_t *) dev->priv;
DMFE_DBUG(0, "dmfe_init_dm9000()", 0);
/* set the internal PHY power-on, GPIOs normal, and wait 2ms */
iow(db, 0x1F, 0); /* GPR (reg_1Fh)bit GPIO0=0 pre-activate PHY */
udelay(20); /* wait 2ms for PHY power-on ready */
/* do a software reset and wait 20us */
iow(db, DM9000_NCR, 3);
udelay(20); /* wait 20us at least for software reset ok */
iow(db, 0, 3); /* NCR (reg_00h) bit[0] RST=1 & Loopback=1,
* reset on. Added by SPenser */
udelay(20); /* wait 20us at least for software reset ok */
// Marked by Spenser
/* set GPIO0=1 then GPIO0=0 to turn off and on the internal PHY */
iow(db, 0x1F, 1); /* GPR (reg_1Fh) bit[0] GPIO0=1 turn-off PHY */
iow(db, 0x1F, 0); /* GPR (reg_1Fh) bit[0] GPIO0=0 activate PHY */
udelay(1000); /* wait 4ms linking PHY (AUTO sense) if RX/TX */
udelay(1000);
udelay(1000);
udelay(1000);
/* I/O mode */
db->io_mode = ior(db, 0xfe) >> 6; /* ISR bit7:6 keeps I/O mode */
/* NIC Type: FASTETHER, HOMERUN, LONGRUN */
identify_nic(db);
/* Set PHY */
db->op_mode = media_mode;
set_PHY_mode(db);
/* Init needed register value */
db->reg0 = DM9000_NCR;
if ((db->nic_type != FASTETHER_NIC) && (db->op_mode & DM9000_1M_HPNA))
db->reg0 |= DM9000_EXT_MII;
/* User passed argument */
db->reg5 = reg5;
db->reg8 = reg8;
db->reg9 = reg9;
db->rega = rega;
/* Program operating register */
iow(db, 0x00, 0x08);
iow(db, 0x02, 0); /* TX Polling clear */
iow(db, 0x2f, 0); /* Special Mode */
iow(db, 0x01, 0x2c); /* clear TX status */
iow(db, 0xfe, 0x0f); /* Clear interrupt status */
iow(db, 0x08, 0x37);
iow(db, 0x09, 0x38); /* Flow control: High/Low water */
iow(db, 0x0a, 0x29); /* flow control */
/* Set address filter table */
dm9000_hash_table(dev);
/* Activate DM9000 */
iow(db, 0x05, db->reg5 | 1); /* RX enable */
iow(db, 0xff, DM9000_REGFF); /* Enable TX/RX interrupt mask */
/* Init Driver variable */
db->link_failed = 1;
db->tx_pkt_cnt = 0;
db->queue_pkt_len = 0;
dev->trans_start = 0;
netif_carrier_on(dev);
spin_lock_init(&db->lock);
}
static void dmfe_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
struct device *dev = dev_id;
struct tx_desc *txptr;
struct dmfe_board_info *db;
u32 ioaddr;
if (!dev) {
DMFE_DBUG(1, "dmfe_interrupt() without device arg", 0);
return;
}
if (dev->interrupt) {
DMFE_DBUG(1, "dmfe_interrupt() re-entry ", 0);
return;
}
/* A real interrupt coming */
dev->interrupt = 1; /* Lock interrupt */
db = (struct dmfe_board_info *) dev->priv;
ioaddr = dev->base_addr;
DMFE_DBUG(0, "dmfe_interrupt()", 0);
/* Disable all interrupt in CR7 to solve the interrupt edge problem */
outl(0, ioaddr + DCR7);
/* Got DM910X status */
db->cr5_data = inl(ioaddr + DCR5);
outl(db->cr5_data, ioaddr + DCR5);
/* printk("CR5=%x\n", db->cr5_data); */
/* Check system status */
if (db->cr5_data & 0x2000) {
/* system bus error happen */
DMFE_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
dev->tbusy = 1;
db->wait_reset = 1; /* Need to RESET */
outl(0, ioaddr + DCR7); /* disable all interrupt */
dev->interrupt = 0; /* unlock interrupt */
return;
}
/* Free the transmitted descriptor */
txptr = db->tx_remove_ptr;
while (db->tx_packet_cnt) {
/* printk("tdes0=%x\n", txptr->tdes0); */
if (txptr->tdes0 & 0x80000000)
break;
/* A packet sent completed */
db->stats.tx_packets++;
/* Transmit statistic counter */
if (txptr->tdes0 != 0x7fffffff) {
/* printk("tdes0=%x\n", txptr->tdes0); */
db->stats.collisions += (txptr->tdes0 >> 3) & 0xf;
db->stats.tx_bytes += txptr->tdes1 & 0x7ff;
if (txptr->tdes0 & TDES0_ERR_MASK)
db->stats.tx_errors++;
}
txptr = (struct tx_desc *) txptr->next_tx_desc;
db->tx_packet_cnt--;
} /* End of while */
/*
Get statistics from driver.
*/
static struct net_device_stats * dmfe_get_stats(struct net_device *dev)
{
board_info_t *db = netdev_priv(dev);
DMFE_DBUG(0, "dmfe_get_stats", 0);
return &db->stats;
}
