/*
*******************************************************************************
* open_clock
*
* Description:
* void
*
* Parameters:
* void
*
* Return value:
* void
*
* note:
* void
*
*******************************************************************************
*/
static int open_clock(struct sw_hci_hcd *sw_hci, u32 ohci)
{
DMSG_INFO("[%s]: open clock\n", sw_hci->hci_name);
if(sw_hci->sie_clk && sw_hci->phy_gate
&& sw_hci->phy_reset && !sw_hci->clk_is_open){
sw_hci->clk_is_open = 1;
clk_enable(sw_hci->phy_gate);
DMSG_DEBUG("[%s]: open clock, 0x60(0x%x), 0xcc(0x%x)\n",
sw_hci->hci_name,
(u32)USBC_Readl(SW_VA_CCM_IO_BASE + 0x60),
(u32)USBC_Readl(SW_VA_CCM_IO_BASE + 0xcc));
clk_enable(sw_hci->phy_reset);
clk_reset(sw_hci->phy_reset, 0);
DMSG_DEBUG("[%s]: open clock, 0x60(0x%x), 0xcc(0x%x)\n",
sw_hci->hci_name,
(u32)USBC_Readl(SW_VA_CCM_IO_BASE + 0x60),
(u32)USBC_Readl(SW_VA_CCM_IO_BASE + 0xcc));
if(ohci && sw_hci->ohci_gate){
clk_enable(sw_hci->ohci_gate);
}
mdelay(10);
clk_enable(sw_hci->sie_clk);
mdelay(10);
UsbPhyInit(sw_hci->usbc_no);
}else{
DMSG_PANIC("[%s]: wrn: open clock failed, (0x%p, 0x%p, 0x%p, %d, 0x%p)\n",
sw_hci->hci_name,
sw_hci->sie_clk, sw_hci->phy_gate,
sw_hci->phy_reset, sw_hci->clk_is_open,
sw_hci->ohci_gate);
}
DMSG_DEBUG("[%s]: open clock, 0x60(0x%x), 0xcc(0x%x)\n",
sw_hci->hci_name,
(u32)USBC_Readl(SW_VA_CCM_IO_BASE + 0x60),
(u32)USBC_Readl(SW_VA_CCM_IO_BASE + 0xcc));
return 0;
}
/*
*******************************************************************************
* sw_set_vbus
*
* Description:
* void
*
* Parameters:
* void
*
* Return value:
* void
*
* note:
* void
*
*******************************************************************************
*/
static void sw_set_vbus(struct sw_hci_hcd *sw_hci, int is_on)
{
DMSG_DEBUG("[%s]: sw_set_vbus cnt %d\n",
sw_hci->hci_name,
(sw_hci->usbc_no == 1) ? usb1_set_vbus_cnt : usb2_set_vbus_cnt);
if(sw_hci->usbc_no == 1){
if(is_on && usb1_set_vbus_cnt == 0){
__sw_set_vbus(sw_hci, is_on); /* power on */
}else if(!is_on && usb1_set_vbus_cnt == 1){
__sw_set_vbus(sw_hci, is_on); /* power off */
}
if(is_on){
usb1_set_vbus_cnt++;
}else{
usb1_set_vbus_cnt--;
}
}else{
if(is_on && usb2_set_vbus_cnt == 0){
__sw_set_vbus(sw_hci, is_on); /* power on */
}else if(!is_on && usb2_set_vbus_cnt == 1){
__sw_set_vbus(sw_hci, is_on); /* power off */
}
if(is_on){
usb2_set_vbus_cnt++;
}else{
usb2_set_vbus_cnt--;
}
}
return;
}
/*
*******************************************************************************
* close_clock
*
* Description:
* void
*
* Parameters:
* void
*
* Return value:
* void
*
* note:
* void
*
*******************************************************************************
*/
static int close_clock(struct sw_hci_hcd *sw_hci, u32 ohci)
{
DMSG_INFO("[%s]: close clock\n", sw_hci->hci_name);
if(sw_hci->sie_clk && sw_hci->phy_gate
&& sw_hci->phy_reset && sw_hci->clk_is_open){
sw_hci->clk_is_open = 0;
if(ohci && sw_hci->ohci_gate){
clk_disable(sw_hci->ohci_gate);
}
clk_reset(sw_hci->phy_reset, 1);
clk_disable(sw_hci->phy_reset);
clk_disable(sw_hci->phy_gate);
clk_disable(sw_hci->sie_clk);
}else{
DMSG_PANIC("[%s]: wrn: open clock failed, (0x%p, 0x%p, 0x%p, %d, 0x%p)\n",
sw_hci->hci_name,
sw_hci->sie_clk, sw_hci->phy_gate,
sw_hci->phy_reset, sw_hci->clk_is_open,
sw_hci->ohci_gate);
}
DMSG_DEBUG("[%s]: close clock, 0x60(0x%x), 0xcc(0x%x)\n",
sw_hci->hci_name,
(u32)USBC_Readl(SW_VA_CCM_IO_BASE + 0x60),
(u32)USBC_Readl(SW_VA_CCM_IO_BASE + 0xcc));
return 0;
}
static void dbg_clocks(struct sw_hci_hcd *sw_hci)
{
DMSG_DEBUG("[%s]: clock info, SW_VA_CCM_AHBMOD_OFFSET(0x%x), SW_VA_CCM_USBCLK_OFFSET(0x%x)\n",
sw_hci->hci_name,
(u32) readl(SW_VA_CCM_IO_BASE + SW_VA_CCM_AHBMOD_OFFSET),
(u32) readl(SW_VA_CCM_IO_BASE + SW_VA_CCM_USBCLK_OFFSET));
}
static void UsbPhyInit(__u32 usbc_no)
{
/* 调整 USB0 PHY 的幅度和速率 */
USBC_Phy_Write(usbc_no, 0x20, 0x14, 5);
/* DMSG_DEBUG("csr2-1: usbc%d: 0x%x\n", usbc_no, (u32)USBC_Phy_Read(usbc_no, 0x20, 5)); */
/* 调节 disconnect 域值 */
if (!sunxi_is_sun4i())
USBC_Phy_Write(usbc_no, 0x2a, 2, 2);
else
USBC_Phy_Write(usbc_no, 0x2a, 3, 2);
/* DMSG_DEBUG("csr2: usbc%d: 0x%x\n", usbc_no, (u32)USBC_Phy_Read(usbc_no, 0x2a, 2)); */
DMSG_DEBUG("csr3: usbc%d: 0x%x\n", usbc_no, (u32)readl(USBC_Phy_GetCsr(usbc_no)));
return;
}
static void print_sunxi_hci(struct sunxi_hci_hcd *sunxi_hci)
{
DMSG_DEBUG("\n------%s config------\n", sunxi_hci->hci_name);
DMSG_DEBUG("hci_name = %s\n", sunxi_hci->hci_name);
DMSG_DEBUG("irq_no = %d\n", sunxi_hci->irq_no);
DMSG_DEBUG("usbc_no = %d\n", sunxi_hci->usbc_no);
DMSG_DEBUG("usb_vbase = 0x%p\n", sunxi_hci->usb_vbase);
DMSG_DEBUG("sram_vbase = 0x%p\n", sunxi_hci->sram_vbase);
DMSG_DEBUG("clock_vbase = 0x%p\n", sunxi_hci->clock_vbase);
DMSG_DEBUG("sdram_vbase = 0x%p\n", sunxi_hci->sdram_vbase);
DMSG_DEBUG("used = %d\n", sunxi_hci->used);
DMSG_DEBUG("host_init_state = %d\n", sunxi_hci->host_init_state);
DMSG_DEBUG("gpio_name = %s\n", sunxi_hci->drv_vbus_gpio_set.gpio_name);
DMSG_DEBUG("port = %d\n", sunxi_hci->drv_vbus_gpio_set.port);
DMSG_DEBUG("port_num = %d\n", sunxi_hci->drv_vbus_gpio_set.port_num);
DMSG_DEBUG("mul_sel = %d\n", sunxi_hci->drv_vbus_gpio_set.mul_sel);
DMSG_DEBUG("pull = %d\n", sunxi_hci->drv_vbus_gpio_set.pull);
DMSG_DEBUG("drv_level = %d\n", sunxi_hci->drv_vbus_gpio_set.drv_level);
DMSG_DEBUG("data = %d\n", sunxi_hci->drv_vbus_gpio_set.data);
DMSG_DEBUG("\n--------------------------\n");
return;
}